diff --git a/firmware/boards/f1_dual/port_shared.cpp b/firmware/boards/f1_dual/port_shared.cpp
index ad7927d..3e2cbff 100644
--- a/firmware/boards/f1_dual/port_shared.cpp
+++ b/firmware/boards/f1_dual/port_shared.cpp
@@ -6,7 +6,7 @@ const CANConfig canConfig500 =
 {
     CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP,
     /*
-     For 24MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=3, Seq 1=13 and Seq 2=2. Subtract '1' for register values
+     For 32MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=4, Seq 1=13 and Seq 2=2. Subtract '1' for register values
     */
-    CAN_BTR_SJW(0) | CAN_BTR_BRP(2)  | CAN_BTR_TS1(12) | CAN_BTR_TS2(1),
+    CAN_BTR_SJW(0) | CAN_BTR_BRP(4 - 1)  | CAN_BTR_TS1(13 - 1) | CAN_BTR_TS2(2 - 1),
 };
diff --git a/firmware/boards/f1_rev2/port_shared.cpp b/firmware/boards/f1_rev2/port_shared.cpp
index ad7927d..3e2cbff 100644
--- a/firmware/boards/f1_rev2/port_shared.cpp
+++ b/firmware/boards/f1_rev2/port_shared.cpp
@@ -6,7 +6,7 @@ const CANConfig canConfig500 =
 {
     CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP,
     /*
-     For 24MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=3, Seq 1=13 and Seq 2=2. Subtract '1' for register values
+     For 32MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=4, Seq 1=13 and Seq 2=2. Subtract '1' for register values
     */
-    CAN_BTR_SJW(0) | CAN_BTR_BRP(2)  | CAN_BTR_TS1(12) | CAN_BTR_TS2(1),
+    CAN_BTR_SJW(0) | CAN_BTR_BRP(4 - 1)  | CAN_BTR_TS1(13 - 1) | CAN_BTR_TS2(2 - 1),
 };
diff --git a/firmware/boards/f1_rev3/port_shared.cpp b/firmware/boards/f1_rev3/port_shared.cpp
index ad7927d..3e2cbff 100644
--- a/firmware/boards/f1_rev3/port_shared.cpp
+++ b/firmware/boards/f1_rev3/port_shared.cpp
@@ -6,7 +6,7 @@ const CANConfig canConfig500 =
 {
     CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP,
     /*
-     For 24MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=3, Seq 1=13 and Seq 2=2. Subtract '1' for register values
+     For 32MHz http://www.bittiming.can-wiki.info/ gives us Pre-scaler=4, Seq 1=13 and Seq 2=2. Subtract '1' for register values
     */
-    CAN_BTR_SJW(0) | CAN_BTR_BRP(2)  | CAN_BTR_TS1(12) | CAN_BTR_TS2(1),
+    CAN_BTR_SJW(0) | CAN_BTR_BRP(4 - 1)  | CAN_BTR_TS1(13 - 1) | CAN_BTR_TS2(2 - 1),
 };