mirror of https://github.com/PentHertz/srsLTE.git
Initial PHY NR configuration generator
This commit is contained in:
Xavier Arteaga
Xavier Arteaga
parent
320aabec13
commit
2fbd172888
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@ -134,25 +134,6 @@ struct phy_cfg_nr_t {
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srsran_pucch_nr_resource_t& resource) const;
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};
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struct phy_cfg_nr_default_t : public phy_cfg_nr_t {
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/**
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* @brief DL reference configurations defined in TS 38.101-4 User Equipment (UE) radio transmission and reception;
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* Part 4: Performance requirements
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*/
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typedef enum {
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R_PDSCH_2_1_1 = 0, // R.PDSCH.2-1.1 TDD
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} dl_reference_t;
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/**
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* @brief UL reference configurations defined in TS 38.104 Base Station (BS) radio transmission and reception
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*/
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typedef enum {
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G_FR1_A3_8 = 0, // G-FR1-A3-8
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} ul_reference_t;
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phy_cfg_nr_default_t(const dl_reference_t& dl_reference, const ul_reference_t& ul_reference);
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};
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} // namespace srsran
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#endif // SRSRAN_PHY_CFG_NR_H
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@ -0,0 +1,146 @@
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/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2021 Software Radio Systems Limited
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*
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* By using this file, you agree to the terms and conditions set
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* forth in the LICENSE file which can be found at the top level of
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* the distribution.
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*
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*/
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#ifndef SRSRAN_PHY_CFG_NR_DEFAULT_H
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#define SRSRAN_PHY_CFG_NR_DEFAULT_H
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#include "phy_cfg_nr.h"
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namespace srsran {
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class phy_cfg_nr_default_t : public phy_cfg_nr_t
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{
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public:
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struct reference_cfg_t {
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enum {
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/**
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* @brief Carrier reference configuration for 10MHz serving cell bandwidth
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* - BW: 10 MHZ (52 PRB)
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* - PCI: 500
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* - SCS: 15 kHz
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* - SSB: 5ms
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*/
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R_CARRIER_CUSTOM_10MHZ = 0,
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} carrier = R_CARRIER_CUSTOM_10MHZ;
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enum {
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/**
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* @brief TDD custom reference 5 slot DL and 5 slot UL
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*/
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R_TDD_CUSTOM_6_4 = 0,
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} tdd = R_TDD_CUSTOM_6_4;
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enum {
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/**
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* @brief Carrier reference configuration for 10MHz serving cell bandwidth
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* - CORESET: all channel, 1 symbol
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* - Single common Search Space
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*/
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R_PDCCH_CUSTOM_COMMON_SS = 0,
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} pdcch = R_PDCCH_CUSTOM_COMMON_SS;
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enum {
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/**
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* @brief Custom fallback baseline configuration, designed for component testing
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* - Defined single common PDSCH time allocation starting at symbol index 1 and length 13
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* - No DMRS dedicated configuration
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*/
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R_PDSCH_DEFAULT = 0,
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} pdsch = R_PDSCH_DEFAULT;
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enum {
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/**
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* @brief Custom fallback baseline configuration, designed for component testing
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* - Single Time resource allocation
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* - transmission starts at symbol index 0 for 14 symbols
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* - k is 4 slots
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* - No DMRS dedicated configuration
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*/
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R_PUSCH_DEFAULT = 0,
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} pusch = R_PUSCH_DEFAULT;
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enum {
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/**
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* @brief Custom single PUCCH resource per set
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* - Format 1 for 1 or 2 bits
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* - Format 2 for more than 2 bits
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*/
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R_PUCCH_CUSTOM_ONE = 0,
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} pucch = R_PUCCH_CUSTOM_ONE;
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enum {
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/**
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* @brief Sets the delay between PDSCH and HARQ feedback timing automatically
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* - Dynamic HARQ ACK codebook
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* - Guarantees a minimum delay of 4ms
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*/
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R_HARQ_AUTO = 0,
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} harq = R_HARQ_AUTO;
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enum {
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/**
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* @brief Sets the PRACH configuration to an LTE compatible configuration
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* - Configuration index 0
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* - Frequency offset 2 PRB
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* - Root sequence 2
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*/
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R_PRACH_DEFAULT_LTE,
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} prach = R_PRACH_DEFAULT_LTE;
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};
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phy_cfg_nr_default_t(const reference_cfg_t& reference_cfg);
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private:
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/**
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* Carrier make helper methods
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*/
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static void make_carrier_custom_10MHz(srsran_carrier_nr_t& carrier);
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/**
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* TDD make helper methods
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*/
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static void make_tdd_custom_6_4(srsran_tdd_config_nr_t& tdd);
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/**
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* PDCCH make helper methods
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*/
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static void make_pdcch_custom_common_ss(srsran_pdcch_cfg_nr_t& pdcch, const srsran_carrier_nr_t& carrier);
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/**
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* PDSCH make helper methods
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*/
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static void make_pdsch_default(srsran_sch_hl_cfg_nr_t& pdsch);
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/**
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* PUSCH make helper methods
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*/
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static void make_pusch_default(srsran_sch_hl_cfg_nr_t& pusch);
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/**
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* PUCCH make helper methods
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*/
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static void make_pucch_custom_one(srsran_pucch_nr_hl_cfg_t& pucch);
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/**
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* HARQ make helper methods
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*/
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static void make_harq_auto(srsran_harq_ack_cfg_hl_t& harq, const srsran_tdd_config_nr_t& tdd_cfg);
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/**
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* PRACH make helper methods
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*/
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static void make_prach_default_lte(srsran_prach_cfg_t& prach);
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};
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} // namespace srsran
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#endif // SRSRAN_PHY_CFG_NR_DEFAULT_H
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@ -23,6 +23,7 @@ set(SOURCES arch_select.cc
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mac_pcap_net.cc
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pcap.c
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phy_cfg_nr.cc
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phy_cfg_nr_default.cc
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rlc_pcap.cc
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s1ap_pcap.cc
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security.cc
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@ -0,0 +1,221 @@
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/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2021 Software Radio Systems Limited
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*
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* By using this file, you agree to the terms and conditions set
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* forth in the LICENSE file which can be found at the top level of
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* the distribution.
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*
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*/
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#include "srsran/common/phy_cfg_nr_default.h"
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#include "srsran/srsran.h"
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namespace srsran {
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void phy_cfg_nr_default_t::make_carrier_custom_10MHz(srsran_carrier_nr_t& carrier)
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{
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carrier.nof_prb = 52;
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carrier.max_mimo_layers = 1;
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carrier.pci = 500;
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carrier.absolute_frequency_point_a = 633928;
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carrier.absolute_frequency_ssb = 634176;
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carrier.offset_to_carrier = 0;
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carrier.scs = srsran_subcarrier_spacing_15kHz;
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}
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void phy_cfg_nr_default_t::make_tdd_custom_6_4(srsran_tdd_config_nr_t& tdd)
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{
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tdd.pattern1.period_ms = 10;
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tdd.pattern1.nof_dl_slots = 6;
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tdd.pattern1.nof_dl_symbols = 0;
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tdd.pattern1.nof_ul_slots = 4;
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tdd.pattern1.nof_ul_symbols = 0;
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// Disable pattern 2
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tdd.pattern2.period_ms = 0;
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}
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void phy_cfg_nr_default_t::make_pdcch_custom_common_ss(srsran_pdcch_cfg_nr_t& pdcch, const srsran_carrier_nr_t& carrier)
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{
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pdcch.coreset_present[1] = true;
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pdcch.coreset[1].id = 1;
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for (uint32_t i = 0; i < SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE; i++) {
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pdcch.coreset[1].freq_resources[0] = i < SRSRAN_FLOOR(carrier.nof_prb, 6);
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}
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pdcch.coreset[1].duration = 1;
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pdcch.coreset[1].mapping_type = srsran_coreset_mapping_type_non_interleaved;
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pdcch.coreset[1].precoder_granularity = srsran_coreset_precoder_granularity_reg_bundle;
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pdcch.search_space_present[1] = true;
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pdcch.search_space[1].id = 1;
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pdcch.search_space[1].coreset_id = 1;
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pdcch.search_space[1].duration = 1;
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pdcch.search_space[1].nof_candidates[0] = 0;
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pdcch.search_space[1].nof_candidates[1] = 0;
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pdcch.search_space[1].nof_candidates[2] = 0;
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pdcch.search_space[1].nof_candidates[3] = 1;
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pdcch.search_space[1].nof_candidates[4] = 0;
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pdcch.search_space[1].formats[0] = srsran_dci_format_nr_0_0; // DCI format for PUSCH
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pdcch.search_space[1].formats[1] = srsran_dci_format_nr_1_0; // DCI format for PDSCH
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pdcch.search_space[1].nof_formats = 2;
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pdcch.search_space[1].type = srsran_search_space_type_common_3;
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}
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void phy_cfg_nr_default_t::make_pdsch_default(srsran_sch_hl_cfg_nr_t& pdsch)
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{
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// Select PDSCH time resource allocation
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pdsch.common_time_ra[0].k = 0;
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pdsch.common_time_ra[0].mapping_type = srsran_sch_mapping_type_A;
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pdsch.common_time_ra[0].sliv = srsran_ra_type2_to_riv(SRSRAN_NSYMB_PER_SLOT_NR - 1, 1, SRSRAN_NSYMB_PER_SLOT_NR);
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pdsch.nof_common_time_ra = 1;
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// Setup PDSCH DMRS type A position
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pdsch.typeA_pos = srsran_dmrs_sch_typeA_pos_2;
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}
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void phy_cfg_nr_default_t::make_pusch_default(srsran_sch_hl_cfg_nr_t& pusch)
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{
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// Select PUSCH time resource allocation
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pusch.common_time_ra[0].k = 4;
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pusch.common_time_ra[0].mapping_type = srsran_sch_mapping_type_A;
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pusch.common_time_ra[0].sliv = srsran_ra_type2_to_riv(SRSRAN_NSYMB_PER_SLOT_NR, 0, SRSRAN_NSYMB_PER_SLOT_NR);
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pusch.nof_common_time_ra = 1;
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// Setup PUSCH DMRS type A position
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pusch.typeA_pos = srsran_dmrs_sch_typeA_pos_2;
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}
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void phy_cfg_nr_default_t::make_pucch_custom_one(srsran_pucch_nr_hl_cfg_t& pucch)
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{
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// PUCCH Resource for format 1
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srsran_pucch_nr_resource_t resource_small = {};
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resource_small.starting_prb = 0;
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resource_small.format = SRSRAN_PUCCH_NR_FORMAT_1;
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resource_small.initial_cyclic_shift = 0;
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resource_small.nof_symbols = 14;
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resource_small.start_symbol_idx = 0;
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resource_small.time_domain_occ = 0;
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// PUCCH Resource for format 2
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srsran_pucch_nr_resource_t resource_big = {};
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resource_big.starting_prb = 51;
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resource_big.format = SRSRAN_PUCCH_NR_FORMAT_2;
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resource_big.nof_prb = 1;
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resource_big.nof_symbols = 2;
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resource_big.start_symbol_idx = 0;
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// Resource for SR
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srsran_pucch_nr_resource_t resource_sr = {};
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resource_sr.starting_prb = 51;
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resource_sr.format = SRSRAN_PUCCH_NR_FORMAT_1;
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resource_sr.initial_cyclic_shift = 0;
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resource_sr.nof_symbols = 14;
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resource_sr.start_symbol_idx = 0;
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resource_sr.time_domain_occ = 0;
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pucch.enabled = true;
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// Set format 1 for 1-2 bits
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pucch.sets[0].resources[0] = resource_small;
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pucch.sets[0].resources[1] = resource_small;
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pucch.sets[0].resources[2] = resource_small;
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pucch.sets[0].resources[3] = resource_small;
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pucch.sets[0].resources[4] = resource_small;
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pucch.sets[0].resources[5] = resource_small;
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pucch.sets[0].resources[6] = resource_small;
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pucch.sets[0].resources[7] = resource_small;
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pucch.sets[0].nof_resources = 8;
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// Set format 2 for more bits
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pucch.sets[1].resources[0] = resource_big;
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pucch.sets[1].resources[1] = resource_big;
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pucch.sets[1].resources[2] = resource_big;
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pucch.sets[1].resources[3] = resource_big;
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pucch.sets[1].resources[4] = resource_big;
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pucch.sets[1].resources[5] = resource_big;
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pucch.sets[1].resources[6] = resource_big;
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pucch.sets[1].resources[7] = resource_big;
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pucch.sets[1].nof_resources = 8;
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// Configure scheduling request
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pucch.sr_resources[1].configured = true;
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pucch.sr_resources[1].sr_id = 0;
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pucch.sr_resources[1].period = 40;
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pucch.sr_resources[1].offset = 8;
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pucch.sr_resources[1].resource = resource_sr;
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}
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void phy_cfg_nr_default_t::make_harq_auto(srsran_harq_ack_cfg_hl_t& harq, const srsran_tdd_config_nr_t& tdd_cfg)
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{
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harq.nof_dl_data_to_ul_ack = SRSRAN_MAX(tdd_cfg.pattern1.nof_dl_slots, SRSRAN_MAX_NOF_DL_DATA_TO_UL);
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for (uint32_t i = 0; i < harq.nof_dl_data_to_ul_ack; i++) {
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harq.dl_data_to_ul_ack[i] = ((harq.nof_dl_data_to_ul_ack - 4) > i) ? (harq.nof_dl_data_to_ul_ack - i) : 4;
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}
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for (uint32_t i = harq.nof_dl_data_to_ul_ack; i < SRSRAN_MAX_NOF_DL_DATA_TO_UL; i++) {
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harq.dl_data_to_ul_ack[i] = 0;
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}
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}
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void phy_cfg_nr_default_t::make_prach_default_lte(srsran_prach_cfg_t& prach)
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{
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prach.config_idx = 0;
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prach.freq_offset = 2;
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prach.root_seq_idx = 0;
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}
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phy_cfg_nr_default_t::phy_cfg_nr_default_t(const reference_cfg_t& reference_cfg)
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{
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switch (reference_cfg.carrier) {
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case reference_cfg_t::R_CARRIER_CUSTOM_10MHZ:
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make_carrier_custom_10MHz(carrier);
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break;
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}
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switch (reference_cfg.tdd) {
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case reference_cfg_t::R_TDD_CUSTOM_6_4:
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make_tdd_custom_6_4(tdd);
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break;
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}
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switch (reference_cfg.pdcch) {
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case reference_cfg_t::R_PDCCH_CUSTOM_COMMON_SS:
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make_pdcch_custom_common_ss(pdcch, carrier);
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break;
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}
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switch (reference_cfg.pdsch) {
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case reference_cfg_t::R_PDSCH_DEFAULT:
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make_pdsch_default(pdsch);
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break;
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}
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switch (reference_cfg.pusch) {
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case reference_cfg_t::R_PUSCH_DEFAULT:
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make_pusch_default(pusch);
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break;
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}
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switch (reference_cfg.pucch) {
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case reference_cfg_t::R_PUCCH_CUSTOM_ONE:
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make_pusch_default(pusch);
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break;
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}
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switch (reference_cfg.harq) {
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case reference_cfg_t::R_HARQ_AUTO:
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make_harq_auto(harq_ack, tdd);
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break;
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}
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switch (reference_cfg.prach) {
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case reference_cfg_t::R_PRACH_DEFAULT_LTE:
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make_prach_default_lte(prach);
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break;
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}
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}
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} // namespace srsran
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@ -11,6 +11,7 @@
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*/
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#include "dummy_gnb_stack.h"
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#include "srsran/common/phy_cfg_nr_default.h"
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#include "srsran/common/test_common.h"
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#include "test_bench.h"
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@ -19,199 +20,9 @@ test_bench::args_t::args_t(int argc, char** argv)
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// Flag configuration as valid
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valid = true;
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phy_cfg.carrier.nof_prb = 52;
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phy_cfg.carrier.max_mimo_layers = 1;
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phy_cfg.carrier.pci = 500;
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phy_cfg.carrier.absolute_frequency_point_a = 633928;
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phy_cfg.carrier.absolute_frequency_ssb = 634176;
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phy_cfg.carrier.offset_to_carrier = 0;
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phy_cfg.carrier.scs = srsran_subcarrier_spacing_15kHz;
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phy_cfg.ssb.periodicity_ms = 5;
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phy_cfg.ssb.position_in_burst[0] = true;
|
||||
phy_cfg.ssb.scs = srsran_subcarrier_spacing_30kHz;
|
||||
|
||||
phy_cfg.pdcch.coreset_present[1] = true;
|
||||
phy_cfg.pdcch.coreset[1].id = 1;
|
||||
phy_cfg.pdcch.coreset[1].freq_resources[0] = true;
|
||||
phy_cfg.pdcch.coreset[1].freq_resources[1] = true;
|
||||
phy_cfg.pdcch.coreset[1].freq_resources[2] = true;
|
||||
phy_cfg.pdcch.coreset[1].freq_resources[3] = true;
|
||||
phy_cfg.pdcch.coreset[1].freq_resources[4] = true;
|
||||
phy_cfg.pdcch.coreset[1].freq_resources[5] = true;
|
||||
phy_cfg.pdcch.coreset[1].freq_resources[6] = true;
|
||||
phy_cfg.pdcch.coreset[1].freq_resources[7] = true;
|
||||
phy_cfg.pdcch.coreset[1].duration = 1;
|
||||
phy_cfg.pdcch.coreset[1].mapping_type = srsran_coreset_mapping_type_non_interleaved;
|
||||
phy_cfg.pdcch.coreset[1].precoder_granularity = srsran_coreset_precoder_granularity_reg_bundle;
|
||||
phy_cfg.pdcch.coreset_present[2] = true;
|
||||
phy_cfg.pdcch.coreset[2].id = 2;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[0] = true;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[1] = true;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[2] = true;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[3] = true;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[4] = true;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[5] = true;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[6] = true;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[7] = true;
|
||||
phy_cfg.pdcch.coreset[2].duration = 1;
|
||||
phy_cfg.pdcch.coreset[2].mapping_type = srsran_coreset_mapping_type_non_interleaved;
|
||||
phy_cfg.pdcch.coreset[2].precoder_granularity = srsran_coreset_precoder_granularity_reg_bundle;
|
||||
|
||||
phy_cfg.pdcch.search_space_present[1] = true;
|
||||
phy_cfg.pdcch.search_space[1].id = 1;
|
||||
phy_cfg.pdcch.search_space[1].coreset_id = 1;
|
||||
phy_cfg.pdcch.search_space[1].duration = 1;
|
||||
phy_cfg.pdcch.search_space[1].nof_candidates[0] = 1;
|
||||
phy_cfg.pdcch.search_space[1].nof_candidates[1] = 1;
|
||||
phy_cfg.pdcch.search_space[1].nof_candidates[2] = 1;
|
||||
phy_cfg.pdcch.search_space[1].nof_candidates[3] = 0;
|
||||
phy_cfg.pdcch.search_space[1].nof_candidates[4] = 0;
|
||||
phy_cfg.pdcch.search_space[1].formats[0] = srsran_dci_format_nr_0_0; // DCI format for PUSCH
|
||||
phy_cfg.pdcch.search_space[1].formats[1] = srsran_dci_format_nr_1_0; // DCI format for PDSCH
|
||||
phy_cfg.pdcch.search_space[1].nof_formats = 2;
|
||||
phy_cfg.pdcch.search_space[1].type = srsran_search_space_type_common_3;
|
||||
|
||||
phy_cfg.pdcch.search_space_present[2] = true;
|
||||
phy_cfg.pdcch.search_space[2].id = 2;
|
||||
phy_cfg.pdcch.search_space[2].coreset_id = 2;
|
||||
phy_cfg.pdcch.search_space[2].duration = 1;
|
||||
phy_cfg.pdcch.search_space[2].nof_candidates[0] = 0;
|
||||
phy_cfg.pdcch.search_space[2].nof_candidates[1] = 2;
|
||||
phy_cfg.pdcch.search_space[2].nof_candidates[2] = 1;
|
||||
phy_cfg.pdcch.search_space[2].nof_candidates[3] = 0;
|
||||
phy_cfg.pdcch.search_space[2].nof_candidates[4] = 0;
|
||||
phy_cfg.pdcch.search_space[2].formats[0] = srsran_dci_format_nr_0_1;
|
||||
phy_cfg.pdcch.search_space[2].formats[1] = srsran_dci_format_nr_1_1;
|
||||
phy_cfg.pdcch.search_space[2].nof_formats = 2;
|
||||
phy_cfg.pdcch.search_space[2].type = srsran_search_space_type_ue;
|
||||
|
||||
phy_cfg.pdcch.ra_search_space_present = true;
|
||||
phy_cfg.pdcch.ra_search_space = phy_cfg.pdcch.search_space[1];
|
||||
phy_cfg.pdcch.ra_search_space.type = srsran_search_space_type_common_1;
|
||||
|
||||
phy_cfg.pdsch.common_time_ra[0].mapping_type = srsran_sch_mapping_type_A;
|
||||
phy_cfg.pdsch.common_time_ra[0].sliv = 40;
|
||||
phy_cfg.pdsch.common_time_ra[1].mapping_type = srsran_sch_mapping_type_A;
|
||||
phy_cfg.pdsch.common_time_ra[1].sliv = 57;
|
||||
phy_cfg.pdsch.nof_common_time_ra = 2;
|
||||
|
||||
phy_cfg.pusch.common_time_ra[0].k = 4;
|
||||
phy_cfg.pusch.common_time_ra[0].mapping_type = srsran_sch_mapping_type_A;
|
||||
phy_cfg.pusch.common_time_ra[0].sliv = 27;
|
||||
phy_cfg.pusch.common_time_ra[1].k = 5;
|
||||
phy_cfg.pusch.common_time_ra[1].mapping_type = srsran_sch_mapping_type_A;
|
||||
phy_cfg.pusch.common_time_ra[1].sliv = 27;
|
||||
phy_cfg.pusch.nof_common_time_ra = 2;
|
||||
|
||||
phy_cfg.pdsch.typeA_pos = srsran_dmrs_sch_typeA_pos_2;
|
||||
phy_cfg.pusch.typeA_pos = srsran_dmrs_sch_typeA_pos_2;
|
||||
|
||||
phy_cfg.tdd.pattern1.period_ms = 10;
|
||||
phy_cfg.tdd.pattern1.nof_dl_slots = 5;
|
||||
phy_cfg.tdd.pattern1.nof_dl_symbols = 0;
|
||||
phy_cfg.tdd.pattern1.nof_ul_slots = 5;
|
||||
phy_cfg.tdd.pattern1.nof_ul_symbols = 0;
|
||||
|
||||
phy_cfg.pdsch.dmrs_typeA.additional_pos = srsran_dmrs_sch_add_pos_1;
|
||||
phy_cfg.pdsch.dmrs_typeA.present = true;
|
||||
phy_cfg.pdsch.alloc = srsran_resource_alloc_type1;
|
||||
|
||||
phy_cfg.pucch.enabled = true;
|
||||
srsran_pucch_nr_resource_t& pucch0 = phy_cfg.pucch.sets[0].resources[0];
|
||||
srsran_pucch_nr_resource_t& pucch1 = phy_cfg.pucch.sets[0].resources[1];
|
||||
srsran_pucch_nr_resource_t& pucch2 = phy_cfg.pucch.sets[0].resources[2];
|
||||
srsran_pucch_nr_resource_t& pucch3 = phy_cfg.pucch.sets[0].resources[3];
|
||||
srsran_pucch_nr_resource_t& pucch4 = phy_cfg.pucch.sets[0].resources[4];
|
||||
srsran_pucch_nr_resource_t& pucch5 = phy_cfg.pucch.sets[0].resources[5];
|
||||
srsran_pucch_nr_resource_t& pucch6 = phy_cfg.pucch.sets[0].resources[6];
|
||||
srsran_pucch_nr_resource_t& pucch7 = phy_cfg.pucch.sets[0].resources[7];
|
||||
phy_cfg.pucch.sets[0].nof_resources = 8;
|
||||
srsran_pucch_nr_resource_t& pucch8 = phy_cfg.pucch.sets[1].resources[0];
|
||||
srsran_pucch_nr_resource_t& pucch9 = phy_cfg.pucch.sets[1].resources[1];
|
||||
srsran_pucch_nr_resource_t& pucch10 = phy_cfg.pucch.sets[1].resources[2];
|
||||
srsran_pucch_nr_resource_t& pucch11 = phy_cfg.pucch.sets[1].resources[3];
|
||||
srsran_pucch_nr_resource_t& pucch12 = phy_cfg.pucch.sets[1].resources[4];
|
||||
srsran_pucch_nr_resource_t& pucch13 = phy_cfg.pucch.sets[1].resources[5];
|
||||
srsran_pucch_nr_resource_t& pucch14 = phy_cfg.pucch.sets[1].resources[6];
|
||||
srsran_pucch_nr_resource_t& pucch15 = phy_cfg.pucch.sets[1].resources[7];
|
||||
phy_cfg.pucch.sets[1].nof_resources = 8;
|
||||
|
||||
pucch0.starting_prb = 0;
|
||||
pucch0.format = SRSRAN_PUCCH_NR_FORMAT_1;
|
||||
pucch0.initial_cyclic_shift = 0;
|
||||
pucch0.nof_symbols = 14;
|
||||
pucch0.start_symbol_idx = 0;
|
||||
pucch0.time_domain_occ = 0;
|
||||
pucch1 = pucch0;
|
||||
pucch1.initial_cyclic_shift = 4;
|
||||
pucch1.time_domain_occ = 0;
|
||||
pucch2 = pucch0;
|
||||
pucch2.initial_cyclic_shift = 8;
|
||||
pucch2.time_domain_occ = 0;
|
||||
pucch3 = pucch0;
|
||||
pucch3.initial_cyclic_shift = 0;
|
||||
pucch3.time_domain_occ = 1;
|
||||
pucch4 = pucch0;
|
||||
pucch4.initial_cyclic_shift = 0;
|
||||
pucch4.time_domain_occ = 1;
|
||||
pucch5 = pucch0;
|
||||
pucch5.initial_cyclic_shift = 4;
|
||||
pucch5.time_domain_occ = 1;
|
||||
pucch6 = pucch0;
|
||||
pucch6.initial_cyclic_shift = 0;
|
||||
pucch6.time_domain_occ = 2;
|
||||
pucch7 = pucch0;
|
||||
pucch7.initial_cyclic_shift = 4;
|
||||
pucch7.time_domain_occ = 2;
|
||||
|
||||
pucch8.starting_prb = 51;
|
||||
pucch8.format = SRSRAN_PUCCH_NR_FORMAT_2;
|
||||
pucch8.nof_prb = 1;
|
||||
pucch8.nof_symbols = 2;
|
||||
pucch8.start_symbol_idx = 0;
|
||||
|
||||
pucch9 = pucch8;
|
||||
pucch9.start_symbol_idx = 2;
|
||||
pucch10 = pucch8;
|
||||
pucch10.start_symbol_idx = 4;
|
||||
pucch11 = pucch8;
|
||||
pucch11.start_symbol_idx = 6;
|
||||
pucch12 = pucch8;
|
||||
pucch12.start_symbol_idx = 8;
|
||||
pucch13 = pucch8;
|
||||
pucch13.start_symbol_idx = 10;
|
||||
pucch14 = pucch8;
|
||||
pucch14.start_symbol_idx = 12;
|
||||
pucch15 = pucch8;
|
||||
pucch15.starting_prb = 1;
|
||||
pucch15.start_symbol_idx = 0;
|
||||
|
||||
srsran_pucch_nr_resource_t& pucch16 = phy_cfg.pucch.sr_resources[1].resource;
|
||||
pucch16.starting_prb = 0;
|
||||
pucch16.format = SRSRAN_PUCCH_NR_FORMAT_1;
|
||||
pucch16.initial_cyclic_shift = 8;
|
||||
pucch16.nof_symbols = 14;
|
||||
pucch16.start_symbol_idx = 0;
|
||||
pucch16.time_domain_occ = 2;
|
||||
|
||||
phy_cfg.pucch.sr_resources[1].configured = true;
|
||||
phy_cfg.pucch.sr_resources[1].sr_id = 0;
|
||||
phy_cfg.pucch.sr_resources[1].period = 40;
|
||||
phy_cfg.pucch.sr_resources[1].offset = 8;
|
||||
phy_cfg.pucch.sr_resources[1].resource = pucch16;
|
||||
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[0] = 8;
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[1] = 7;
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[2] = 6;
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[3] = 5;
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[4] = 4;
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[5] = 4;
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[6] = 4;
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[7] = 4;
|
||||
phy_cfg.harq_ack.harq_ack_codebook = srsran_pdsch_harq_ack_codebook_dynamic;
|
||||
|
||||
phy_cfg.prach.freq_offset = 2;
|
||||
// Load default reference configuration
|
||||
srsran::phy_cfg_nr_default_t::reference_cfg_t reference_cfg;
|
||||
phy_cfg = srsran::phy_cfg_nr_default_t(reference_cfg);
|
||||
|
||||
cell_list.resize(1);
|
||||
cell_list[0].carrier = phy_cfg.carrier;
|
||||
|
|
|
|||
Loading…
Reference in New Issue