mirror of https://github.com/PentHertz/srsLTE.git
Added PHY NR test TDD FR1.15-1 pattern
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956c4f8266
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@ -39,15 +39,22 @@ public:
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*/
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R_CARRIER_CUSTOM_20MHZ,
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R_CARRIER_COUNT
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} carrier = R_CARRIER_CUSTOM_10MHZ;
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const std::vector<std::string> R_CARRIER_STRING = {"10MHz", "20MHz", "Invalid"};
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} carrier = R_CARRIER_CUSTOM_10MHZ;
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const std::array<std::string, R_CARRIER_COUNT> R_CARRIER_STRING = {"10MHz", "20MHz"};
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enum {
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/**
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* @brief TDD custom reference 5 slot DL and 5 slot UL
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*/
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R_TDD_CUSTOM_6_4 = 0,
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} tdd = R_TDD_CUSTOM_6_4;
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/**
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* @brief TDD pattern FR1.15-1 defined in TS38.101-4 Table A.1.2-1
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*/
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R_TDD_FR1_15_1,
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R_TDD_COUNT,
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} tdd = R_TDD_CUSTOM_6_4;
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const std::array<std::string, R_TDD_COUNT> R_TDD_STRING = {"6D+4U", "FR1.15-1"};
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enum {
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/**
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@ -77,8 +84,8 @@ public:
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*/
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R_PDSCH_COUNT
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} pdsch = R_PDSCH_DEFAULT;
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const std::vector<std::string> R_PDSCH_STRING = {"default", "ts38101/5.2-1", "Invalid"};
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} pdsch = R_PDSCH_DEFAULT;
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const std::array<std::string, R_PDSCH_COUNT> R_PDSCH_STRING = {"default", "ts38101/5.2-1"};
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enum {
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/**
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@ -138,6 +145,7 @@ private:
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* TDD make helper methods
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*/
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static void make_tdd_custom_6_4(srsran_tdd_config_nr_t& tdd);
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static void make_tdd_fr1_15_1(srsran_tdd_config_nr_t& tdd);
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/**
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* PDCCH make helper methods
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@ -44,6 +44,13 @@ phy_cfg_nr_default_t::reference_cfg_t::reference_cfg_t(const std::string& args)
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}
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}
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srsran_assert(carrier != R_CARRIER_COUNT, "Invalid carrier reference configuration '%s'", param.back().c_str());
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} else if (param.front() == "tdd") {
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for (tdd = R_TDD_CUSTOM_6_4; tdd < R_TDD_COUNT; tdd = inc(tdd)) {
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if (R_TDD_STRING[tdd] == param.back()) {
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break;
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}
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}
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srsran_assert(tdd != R_TDD_COUNT, "Invalid TDD reference configuration '%s'", param.back().c_str());
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} else if (param.front() == "pdsch") {
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for (pdsch = R_PDSCH_DEFAULT; pdsch < R_PDSCH_COUNT; pdsch = inc(pdsch)) {
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if (R_PDSCH_STRING[pdsch] == param.back()) {
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@ -91,6 +98,18 @@ void phy_cfg_nr_default_t::make_tdd_custom_6_4(srsran_tdd_config_nr_t& tdd)
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tdd.pattern2.period_ms = 0;
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}
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void phy_cfg_nr_default_t::make_tdd_fr1_15_1(srsran_tdd_config_nr_t& tdd)
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{
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tdd.pattern1.period_ms = 5;
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tdd.pattern1.nof_dl_slots = 3;
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tdd.pattern1.nof_dl_symbols = 10;
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tdd.pattern1.nof_ul_slots = 1;
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tdd.pattern1.nof_ul_symbols = 2;
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// Disable pattern 2
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tdd.pattern2.period_ms = 0;
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}
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void phy_cfg_nr_default_t::make_pdcch_custom_common_ss(srsran_pdcch_cfg_nr_t& pdcch, const srsran_carrier_nr_t& carrier)
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{
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// Configure CORESET ID 1
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@ -253,7 +272,7 @@ void phy_cfg_nr_default_t::make_pucch_custom_one(srsran_pucch_nr_hl_cfg_t& pucch
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resource_big.format = SRSRAN_PUCCH_NR_FORMAT_2;
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resource_big.nof_prb = 1;
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resource_big.nof_symbols = 2;
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resource_big.start_symbol_idx = 0;
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resource_big.start_symbol_idx = 12;
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// Resource for SR
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srsran_pucch_nr_resource_t resource_sr = {};
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@ -302,11 +321,14 @@ void phy_cfg_nr_default_t::make_harq_auto(srsran_harq_ack_cfg_hl_t& harq,
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{
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// Generate as many entries as DL slots
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harq.nof_dl_data_to_ul_ack = SRSRAN_MIN(tdd_cfg.pattern1.nof_dl_slots, SRSRAN_MAX_NOF_DL_DATA_TO_UL);
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if (tdd_cfg.pattern1.nof_dl_symbols > 0) {
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harq.nof_dl_data_to_ul_ack++;
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}
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// Set PDSCH to ACK timing delay to 4 or more
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for (uint32_t n = 0; n < harq.nof_dl_data_to_ul_ack; n++) {
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// Set the first slots into the first UL slot
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if (n < (harq.nof_dl_data_to_ul_ack - 4)) {
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if (harq.nof_dl_data_to_ul_ack >= 4 and n < (harq.nof_dl_data_to_ul_ack - 4)) {
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harq.dl_data_to_ul_ack[n] = harq.nof_dl_data_to_ul_ack - n;
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continue;
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}
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@ -318,7 +340,7 @@ void phy_cfg_nr_default_t::make_harq_auto(srsran_harq_ack_cfg_hl_t& harq,
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}
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// Otherwise set delay to the first UL slot of the next TDD period
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harq.dl_data_to_ul_ack[n] = 2 * harq.nof_dl_data_to_ul_ack - n;
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harq.dl_data_to_ul_ack[n] = (tdd_cfg.pattern1.period_ms + tdd_cfg.pattern1.nof_dl_slots) - n;
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}
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// Zero the rest
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@ -355,6 +377,11 @@ phy_cfg_nr_default_t::phy_cfg_nr_default_t(const reference_cfg_t& reference_cfg)
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case reference_cfg_t::R_TDD_CUSTOM_6_4:
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make_tdd_custom_6_4(tdd);
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break;
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case reference_cfg_t::R_TDD_FR1_15_1:
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make_tdd_fr1_15_1(tdd);
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break;
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case reference_cfg_t::R_TDD_COUNT:
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srsran_terminate("Invalid TDD reference");
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}
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switch (reference_cfg.pdcch) {
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@ -25,53 +25,50 @@ if (RF_FOUND AND ENABLE_SRSUE AND ENABLE_SRSENB)
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${Boost_LIBRARIES}
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${ATOMIC_LIBS})
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add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_dl_default nr_phy_test
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--reference=carrier=${NR_PHY_TEST_BW}
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--duration=100
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--gnb.stack.pdsch.slots=0,1,2,3,4,5
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--gnb.stack.pusch.slots=none
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--gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS}
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--ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS}
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)
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foreach (NR_PHY_TEST_TDD "6D+4U" "FR1.15-1")
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set(NR_PHY_TEST_DURATION_MS 20)
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add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_ts38101/5.2-1 nr_phy_test
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--reference=carrier=${NR_PHY_TEST_BW},pdsch=ts38101/5.2-1
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--duration=100
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--gnb.stack.pdsch.mcs=27
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--gnb.stack.pdsch.start=0
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--gnb.stack.pdsch.length=52
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--gnb.stack.pdsch.slots=0,1,2,3,4,5
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--gnb.stack.pusch.slots=none
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--gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS}
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--ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS}
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)
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foreach (NR_PHY_TEST_PDSCH "default" "ts38101/5.2-1")
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add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_${NR_PHY_TEST_TDD}_dl_${NR_PHY_TEST_PDSCH} nr_phy_test
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--reference=carrier=${NR_PHY_TEST_BW},tdd=${NR_PHY_TEST_TDD},pdsch=${NR_PHY_TEST_PDSCH}
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--duration=${NR_PHY_TEST_DURATION_MS}
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--gnb.stack.pdsch.slots=0,1,2,3,4,5 # All possible DL slots
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--gnb.stack.pdsch.start=0 # Start at RB 0
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--gnb.stack.pdsch.length=52 # Full 10 MHz BW
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--gnb.stack.pdsch.mcs=28 # Maximum MCS
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--gnb.stack.pusch.slots=none
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--gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS}
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--ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS}
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)
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endforeach ()
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add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_ul_only nr_phy_test
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--reference=carrier=${NR_PHY_TEST_BW}
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--duration=100 # 100 slots
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--gnb.stack.pdsch.slots=6 # No PDSCH
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--gnb.stack.pusch.slots=6,7,8,9 # All possible UL slots
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--gnb.stack.pusch.start=0 # Start at RB 0
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--gnb.stack.pusch.length=52 # Full 10 MHz BW
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--gnb.stack.pusch.mcs=28 # Maximum MCS
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--gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS}
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--ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS}
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)
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add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_${NR_PHY_TEST_TDD}_ul_only nr_phy_test
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--reference=carrier=${NR_PHY_TEST_BW},tdd=${NR_PHY_TEST_TDD}
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--duration=${NR_PHY_TEST_DURATION_MS}
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--gnb.stack.pdsch.slots=6 # No PDSCH
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--gnb.stack.pusch.slots=6,7,8,9 # All possible UL slots
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--gnb.stack.pusch.start=0 # Start at RB 0
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--gnb.stack.pusch.length=52 # Full 10 MHz BW
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--gnb.stack.pusch.mcs=28 # Maximum MCS
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--gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS}
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--ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS}
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)
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add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_bidir nr_phy_test
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--reference=carrier=${NR_PHY_TEST_BW}
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--duration=100 # 100 slots
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--gnb.stack.pdsch.slots=0,1,2,3,4,5 # All possible DL slots
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--gnb.stack.pdsch.start=0 # Start at RB 0
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--gnb.stack.pdsch.length=52 # Full 10 MHz BW
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--gnb.stack.pdsch.mcs=28 # Maximum MCS
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--gnb.stack.pusch.slots=6,7,8,9 # All possible UL slots
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--gnb.stack.pusch.start=0 # Start at RB 0
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--gnb.stack.pusch.length=52 # Full 10 MHz BW
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--gnb.stack.pusch.mcs=28 # Maximum MCS
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--gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS}
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--ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS}
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)
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add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_${NR_PHY_TEST_TDD}_bidir nr_phy_test
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--reference=carrier=${NR_PHY_TEST_BW},tdd=${NR_PHY_TEST_TDD}
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--duration=${NR_PHY_TEST_DURATION_MS}
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--gnb.stack.pdsch.slots=0,1,2,3,4,5 # All possible DL slots
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--gnb.stack.pdsch.start=0 # Start at RB 0
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--gnb.stack.pdsch.length=52 # Full 10 MHz BW
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--gnb.stack.pdsch.mcs=28 # Maximum MCS
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--gnb.stack.pusch.slots=6,7,8,9 # All possible UL slots
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--gnb.stack.pusch.start=0 # Start at RB 0
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--gnb.stack.pusch.length=52 # Full 10 MHz BW
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--gnb.stack.pusch.mcs=28 # Maximum MCS
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--gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS}
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--ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS}
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)
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endforeach ()
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add_nr_test(nr_phy_test_10MHz_bidir_sched nr_phy_test
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--duration=100 # 100 slots
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@ -393,7 +393,7 @@ public:
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// Setup DL Data to ACK timing
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for (uint32_t i = 0; i < SRSRAN_NOF_SF_X_FRAME; i++) {
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dl_data_to_ul_ack[i] = args.phy_cfg.harq_ack.dl_data_to_ul_ack[i % SRSRAN_MAX_NOF_DL_DATA_TO_UL];
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dl_data_to_ul_ack[i] = args.phy_cfg.harq_ack.dl_data_to_ul_ack[i % args.phy_cfg.tdd.pattern1.period_ms];
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}
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// If reached this point the configuration is valid
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