mirror of https://github.com/PentHertz/srsLTE.git
feature, scheduler: Add abitility to set minimum aggregation level in PDCCH, and disable adaptive aggregation level based on target BLER
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@ -53,7 +53,9 @@ public:
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int pusch_max_mcs = 28;
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uint32_t min_nof_ctrl_symbols = 1;
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uint32_t max_nof_ctrl_symbols = 3;
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int min_aggr_level = 0;
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int max_aggr_level = 3;
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bool adaptive_aggr_level = true;
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bool pucch_mux_enabled = false;
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float target_bler = 0.05;
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float max_delta_dl_cqi = 5;
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@ -160,7 +160,9 @@ enable = false
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# Scheduler configuration options
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#
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# sched_policy: User MAC scheduling policy (E.g. time_rr, time_pf)
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# min_aggr_level: Optional minimum aggregation level index (l=log2(L) can be 0, 1, 2 or 3)
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# max_aggr_level: Optional maximum aggregation level index (l=log2(L) can be 0, 1, 2 or 3)
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# adaptive_aggr_level: Boolean flag to enable/disable adaptive aggregation level based on target BLER
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# pdsch_mcs: Optional fixed PDSCH MCS (ignores reported CQIs if specified)
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# pdsch_max_mcs: Optional PDSCH MCS limit
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# pusch_mcs: Optional fixed PUSCH MCS (ignores reported CQIs if specified)
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@ -176,7 +178,9 @@ enable = false
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[scheduler]
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#policy = time_pf
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#policy_args = 2
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#max_aggr_level = -1
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#min_aggr_level = 0
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#max_aggr_level = 3
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#adaptive_aggr_level = true
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#pdsch_mcs = -1
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#pdsch_max_mcs = -1
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#pusch_mcs = -1
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@ -69,6 +69,7 @@ inline uint32_t get_tbs_bytes(uint32_t mcs, uint32_t nof_alloc_prb, bool use_tbs
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/// Find lowest DCI aggregation level supported by the UE spectral efficiency
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uint32_t get_aggr_level(uint32_t nof_bits,
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uint32_t dl_cqi,
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uint32_t min_aggr_lvl,
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uint32_t max_aggr_lvl,
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uint32_t cell_nof_prb,
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bool use_tbs_index_alt);
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@ -47,6 +47,8 @@ struct sched_ue_cell {
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int get_dl_cqi(const rbgmask_t& rbgs) const;
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int get_ul_cqi() const;
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uint32_t get_aggr_level(uint32_t nof_bits) const;
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int set_ack_info(tti_point tti_rx, uint32_t tb_idx, bool ack);
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int set_ul_crc(tti_point tti_rx, bool crc_res);
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int set_ul_snr(tti_point tti_rx, float ul_snr, uint32_t ul_ch_code);
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@ -145,7 +145,9 @@ void parse_args(all_args_t* args, int argc, char* argv[])
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("scheduler.pdsch_max_mcs", bpo::value<int>(&args->stack.mac.sched.pdsch_max_mcs)->default_value(-1), "Optional PDSCH MCS limit")
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("scheduler.pusch_mcs", bpo::value<int>(&args->stack.mac.sched.pusch_mcs)->default_value(-1), "Optional fixed PUSCH MCS (ignores reported CQIs if specified)")
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("scheduler.pusch_max_mcs", bpo::value<int>(&args->stack.mac.sched.pusch_max_mcs)->default_value(-1), "Optional PUSCH MCS limit")
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("scheduler.max_aggr_level", bpo::value<int>(&args->stack.mac.sched.max_aggr_level)->default_value(-1), "Optional maximum aggregation level index (l=log2(L)) ")
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("scheduler.min_aggr_level", bpo::value<int>(&args->stack.mac.sched.min_aggr_level)->default_value(0), "Optional minimum aggregation level index (l=log2(L)) ")
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("scheduler.max_aggr_level", bpo::value<int>(&args->stack.mac.sched.max_aggr_level)->default_value(3), "Optional maximum aggregation level index (l=log2(L)) ")
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("scheduler.adaptive_aggr_level", bpo::value<bool>(&args->stack.mac.sched.adaptive_aggr_level)->default_value(true), "Boolean flag to enable/disable adaptive aggregation level based on target BLER")
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("scheduler.max_nof_ctrl_symbols", bpo::value<uint32_t>(&args->stack.mac.sched.max_nof_ctrl_symbols)->default_value(3), "Number of control symbols")
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("scheduler.min_nof_ctrl_symbols", bpo::value<uint32_t>(&args->stack.mac.sched.min_nof_ctrl_symbols)->default_value(1), "Minimum number of control symbols")
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("scheduler.pucch_multiplex_enable", bpo::value<bool>(&args->stack.mac.sched.pucch_mux_enabled)->default_value(false), "Enable PUCCH multiplexing")
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@ -382,10 +382,13 @@ void generate_cce_location(srsran_regs_t* regs_,
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* DCI-specific helper functions
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*******************************************************/
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uint32_t
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get_aggr_level(uint32_t nof_bits, uint32_t dl_cqi, uint32_t max_aggr_lvl, uint32_t cell_nof_prb, bool use_tbs_index_alt)
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uint32_t get_aggr_level(uint32_t nof_bits,
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uint32_t dl_cqi,
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uint32_t min_aggr_lvl,
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uint32_t max_aggr_lvl,
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uint32_t cell_nof_prb,
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bool use_tbs_index_alt)
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{
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uint32_t l = 0;
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float max_coderate = srsran_cqi_to_coderate(dl_cqi, use_tbs_index_alt);
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float coderate;
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float factor = 1.5;
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@ -396,6 +399,7 @@ get_aggr_level(uint32_t nof_bits, uint32_t dl_cqi, uint32_t max_aggr_lvl, uint32
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}
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l_max = SRSRAN_MIN(max_aggr_lvl, l_max);
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uint32_t l = min_aggr_lvl;
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do {
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coderate = srsran_pdcch_coderate(nof_bits, l);
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l++;
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@ -963,9 +963,7 @@ std::pair<bool, uint32_t> sched_ue::get_active_cell_index(uint32_t enb_cc_idx) c
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uint32_t sched_ue::get_aggr_level(uint32_t enb_cc_idx, uint32_t nof_bits)
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{
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const auto& cc = cells[enb_cc_idx];
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return srsenb::get_aggr_level(
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nof_bits, cc.get_dl_cqi(), cc.max_aggr_level, cc.cell_cfg->nof_prb(), cfg.use_tbs_index_alt);
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return cells[enb_cc_idx].get_aggr_level(nof_bits);
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}
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void sched_ue::finish_tti(tti_point tti_rx, uint32_t enb_cc_idx)
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@ -235,9 +235,23 @@ int sched_ue_cell::get_dl_cqi(const rbgmask_t& rbgs) const
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int sched_ue_cell::get_dl_cqi() const
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{
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rbgmask_t rbgmask(cell_cfg->nof_rbgs);
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rbgmask.fill(0, rbgmask.size());
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return get_dl_cqi(rbgmask);
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return std::max(0, (int)std::min(dl_cqi_ctxt.get_avg_cqi() + dl_cqi_coeff, 15.0f));
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}
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uint32_t sched_ue_cell::get_aggr_level(uint32_t nof_bits) const
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{
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uint32_t dl_cqi = 0;
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if (cell_cfg->sched_cfg->adaptive_aggr_level) {
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dl_cqi = get_dl_cqi();
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} else {
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dl_cqi = dl_cqi_ctxt.get_avg_cqi();
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}
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return srsenb::get_aggr_level(nof_bits,
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dl_cqi,
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cell_cfg->sched_cfg->min_aggr_level,
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max_aggr_level,
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cell_cfg->nof_prb(),
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ue_cfg->use_tbs_index_alt);
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}
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/*************************************************************
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