mirror of https://github.com/PentHertz/srsLTE.git
sched,nr: extend sched nr to support RAR and msg3 DCI packing.
This commit is contained in:
parent
7ab52500e9
commit
e64fcf6ea6
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@ -41,6 +41,8 @@ public:
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int cell_cfg(srsran::const_span<cell_cfg_t> cell_list) override;
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void ue_cfg(uint16_t rnti, const ue_cfg_t& cfg) override;
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int dl_rach_info(uint32_t cc, const dl_sched_rar_info_t& rar_info);
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void dl_ack_info(uint16_t rnti, uint32_t cc, uint32_t pid, uint32_t tb_idx, bool ack) override;
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void ul_crc_info(uint16_t rnti, uint32_t cc, uint32_t pid, bool crc) override;
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void ul_sr_info(slot_point slot_rx, uint16_t rnti) override;
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@ -36,6 +36,15 @@ using sched_cfg_t = sched_nr_interface::sched_cfg_t;
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using cell_cfg_t = sched_nr_interface::cell_cfg_t;
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using bwp_cfg_t = sched_nr_interface::bwp_cfg_t;
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using pdcch_cce_pos_list = srsran::bounded_vector<uint32_t, SRSRAN_SEARCH_SPACE_MAX_NOF_CANDIDATES_NR>;
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using bwp_cce_pos_list = std::array<std::array<pdcch_cce_pos_list, MAX_NOF_AGGR_LEVELS>, SRSRAN_NOF_SF_X_FRAME>;
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void get_dci_locs(const srsran_coreset_t& coreset,
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const srsran_search_space_t& search_space,
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uint16_t rnti,
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bwp_cce_pos_list& cce_locs);
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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struct bwp_params {
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const uint32_t bwp_id;
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const uint32_t cc;
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@ -56,6 +65,8 @@ struct bwp_params {
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std::vector<pusch_ra_time_cfg> pusch_ra_list;
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bwp_params(const cell_cfg_t& cell, const sched_cfg_t& sched_cfg_, uint32_t cc, uint32_t bwp_id);
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bwp_cce_pos_list rar_cce_list;
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};
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struct sched_cell_params {
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@ -79,17 +90,9 @@ struct sched_params {
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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using prb_bitmap = srsran::bounded_bitset<SRSRAN_MAX_PRB_NR, true>;
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using rbgmask_t = srsran::bounded_bitset<SCHED_NR_MAX_NOF_RBGS, true>;
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using pdcchmask_t = srsran::bounded_bitset<SCHED_NR_MAX_NOF_RBGS, true>;
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using pdcch_cce_pos_list = srsran::bounded_vector<uint32_t, SRSRAN_SEARCH_SPACE_MAX_NOF_CANDIDATES_NR>;
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using bwp_cce_pos_list = std::array<std::array<pdcch_cce_pos_list, MAX_NOF_AGGR_LEVELS>, SRSRAN_NOF_SF_X_FRAME>;
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void get_dci_locs(const srsran_coreset_t& coreset,
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const srsran_search_space_t& search_space,
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uint16_t rnti,
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bwp_cce_pos_list& cce_locs);
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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using ue_cfg_t = sched_nr_interface::ue_cfg_t;
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@ -18,11 +18,13 @@
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namespace srsenb {
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namespace sched_nr_impl {
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class slot_ue;
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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bool fill_dci_rar(prb_interval interv, const bwp_params& bwp_cfg, srsran_dci_dl_nr_t& dci);
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bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params& bwp_cfg, srsran_dci_dl_nr_t& dci);
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class slot_ue;
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bool fill_dci_msg3(const slot_ue& ue, const bwp_params& bwp_cfg, srsran_dci_ul_nr_t& dci);
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/// Generate PDCCH DL DCI fields
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void fill_dl_dci_ue_fields(const slot_ue& ue,
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@ -63,7 +63,10 @@ public:
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srsran::bounded_vector<bwp_cfg_t, SCHED_NR_MAX_BWP_PER_CELL> bwps{1}; // idx0 for BWP-common
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};
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struct sched_cfg_t {};
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struct sched_cfg_t {
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bool pdsch_enabled = true;
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bool pusch_enabled = true;
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};
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struct ue_cc_cfg_t {
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bool active = false;
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@ -66,6 +66,7 @@ private:
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uint32_t coreset_id;
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uint32_t slot_idx;
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uint32_t nof_freq_res = 0;
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const bwp_cce_pos_list& rar_cce_list;
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// List of PDCCH grants
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struct alloc_record {
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@ -59,7 +59,7 @@ struct prb_grant {
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alloc.rbgs.~rbg_bitmap();
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new (&alloc.interv) prb_interval(prbs);
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} else {
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alloc.interv = alloc.interv;
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alloc.interv = prbs;
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}
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return *this;
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}
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@ -89,7 +89,7 @@ public:
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slot_ue_map_t& ues,
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uint32_t max_nof_grants);
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alloc_result alloc_pdsch(slot_ue& ue, const prb_grant& dl_grant);
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alloc_result alloc_pusch(slot_ue& ue, const rbgmask_t& dl_mask);
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alloc_result alloc_pusch(slot_ue& ue, const prb_grant& dl_mask);
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slot_point get_pdcch_tti() const { return pdcch_slot; }
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const bwp_res_grid& res_grid() const { return bwp_grid; }
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@ -42,6 +42,8 @@ public:
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void finish();
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bool running() const { return slot_rx.valid(); }
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void enqueue_cc_event(srsran::move_callback<void()> ev);
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/// Enqueue feedback directed at a given UE in a given cell
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void enqueue_cc_feedback(uint16_t rnti, feedback_callback_t fdbk);
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@ -65,8 +67,9 @@ private:
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uint16_t rnti;
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feedback_callback_t fdbk;
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};
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std::mutex feedback_mutex;
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srsran::deque<feedback_t> pending_feedback, tmp_feedback_to_run;
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std::mutex feedback_mutex;
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srsran::deque<feedback_t> pending_feedback, tmp_feedback_to_run;
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srsran::deque<srsran::move_callback<void()> > pending_events, tmp_events_to_run;
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srsran::static_circular_map<uint16_t, slot_ue, SCHED_NR_MAX_USERS> slot_ues;
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};
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@ -93,6 +96,7 @@ public:
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void run_slot(slot_point slot_tx, uint32_t cc, dl_sched_t& dl_res, ul_sched_t& ul_res);
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void enqueue_event(uint16_t rnti, srsran::move_callback<void()> ev);
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void enqueue_cc_event(uint32_t cc, srsran::move_callback<void()> ev);
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void enqueue_cc_feedback(uint16_t rnti, uint32_t cc, slot_cc_worker::feedback_callback_t fdbk)
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{
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cc_worker_list[cc]->worker.enqueue_cc_feedback(rnti, std::move(fdbk));
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@ -158,6 +158,12 @@ int sched_nr::get_ul_sched(slot_point pusch_tti, uint32_t cc, ul_sched_t& result
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return SRSRAN_SUCCESS;
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}
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int sched_nr::dl_rach_info(uint32_t cc, const dl_sched_rar_info_t& rar_info)
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{
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sched_workers->enqueue_cc_event(cc, [this, cc, rar_info]() { cells[cc]->bwps[0].ra.dl_rach_info(rar_info); });
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return SRSRAN_SUCCESS;
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}
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void sched_nr::dl_ack_info(uint16_t rnti, uint32_t cc, uint32_t pid, uint32_t tb_idx, bool ack)
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{
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sched_workers->enqueue_cc_feedback(
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@ -74,9 +74,9 @@ void ra_sched::run_slot(bwp_slot_allocator& slot_grid, slot_ue_map_t& slot_ues)
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if (pdcch_slot >= rar_window.stop()) {
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fmt::memory_buffer str_buffer;
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fmt::format_to(str_buffer,
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"SCHED: Could not transmit RAR within the window (RA={}, Window={}, RAR={}",
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rar.prach_slot,
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"SCHED: Could not transmit RAR within the window Window={}, PRACH={}, RAR={}",
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rar_window,
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rar.prach_slot,
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pdcch_slot);
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srsran::console("%s\n", srsran::to_c_str(str_buffer));
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logger.warning("%s", srsran::to_c_str(str_buffer));
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@ -42,6 +42,20 @@ bwp_params::bwp_params(const cell_cfg_t& cell, const sched_cfg_t& sched_cfg_, ui
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srsran_assert(ret == SRSRAN_SUCCESS, "Failed to obtain RA config");
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}
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srsran_assert(not pusch_ra_list.empty(), "Time-Domain Resource Allocation not valid");
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for (uint32_t sl = 0; sl < SRSRAN_NOF_SF_X_FRAME; ++sl) {
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for (uint32_t agg_idx = 0; agg_idx < MAX_NOF_AGGR_LEVELS; ++agg_idx) {
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rar_cce_list[sl][agg_idx].resize(SRSRAN_SEARCH_SPACE_MAX_NOF_CANDIDATES_NR);
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int n = srsran_pdcch_nr_locations_coreset(&cell_cfg.bwps[0].pdcch.coreset[0],
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&cell_cfg.bwps[0].pdcch.ra_search_space,
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0,
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agg_idx,
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sl,
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rar_cce_list[sl][agg_idx].data());
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srsran_assert(n >= 0, "Failed to configure RAR DCI locations");
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rar_cce_list[sl][agg_idx].resize(n);
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}
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}
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}
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sched_cell_params::sched_cell_params(uint32_t cc_, const cell_cfg_t& cell, const sched_cfg_t& sched_cfg_) :
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@ -79,7 +79,7 @@ bool harq_proc::new_retx(slot_point slot_tx_, slot_point slot_ack_, const prb_gr
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{
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if (grant.is_alloc_type0() != prbs_.is_alloc_type0() or
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(grant.is_alloc_type0() and grant.rbgs().count() != prbs_.rbgs().count()) or
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(grant.is_alloc_type1() and grant.prbs().length() == prbs_.prbs().length())) {
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(grant.is_alloc_type1() and grant.prbs().length() != prbs_.prbs().length())) {
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return false;
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}
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if (new_retx(slot_tx_, slot_ack_)) {
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@ -19,15 +19,6 @@ namespace sched_nr_impl {
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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bool fill_dci_rar(prb_interval interv, const bwp_params& cell, srsran_dci_dl_nr_t& dci)
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{
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dci.mcs = 5;
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dci.ctx.format = srsran_dci_format_nr_1_0;
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// TODO: Fill
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return true;
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}
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template <typename DciDlOrUl>
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void fill_dci_common(const slot_ue& ue, const bwp_params& bwp_cfg, DciDlOrUl& dci)
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{
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@ -54,6 +45,36 @@ void fill_dci_common(const slot_ue& ue, const bwp_params& bwp_cfg, DciDlOrUl& dc
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dci.time_domain_assigment = 0;
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}
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bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params& bwp_cfg, srsran_dci_dl_nr_t& dci)
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{
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dci.mcs = 5;
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dci.ctx.format = srsran_dci_format_nr_rar;
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dci.ctx.ss_type = srsran_search_space_type_rar;
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dci.ctx.rnti_type = srsran_rnti_type_ra;
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dci.ctx.rnti = ra_rnti;
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dci.ctx.coreset_id = bwp_cfg.cfg.pdcch.ra_search_space.coreset_id;
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dci.freq_domain_assigment = srsran_ra_nr_type1_riv(bwp_cfg.cfg.rb_width, interv.start(), interv.length());
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// TODO: Fill
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return true;
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}
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bool fill_dci_msg3(const slot_ue& ue, const bwp_params& bwp_cfg, srsran_dci_ul_nr_t& msg3_dci)
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{
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msg3_dci.ctx.coreset_id = ue.cfg->phy().pdcch.ra_search_space.coreset_id;
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msg3_dci.ctx.rnti_type = srsran_rnti_type_tc;
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msg3_dci.ctx.rnti = ue.rnti;
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msg3_dci.ctx.ss_type = srsran_search_space_type_rar;
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if (ue.h_ul->nof_retx() == 0) {
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msg3_dci.ctx.format = srsran_dci_format_nr_rar;
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} else {
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msg3_dci.ctx.format = srsran_dci_format_nr_0_0;
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}
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fill_dci_common(ue, bwp_cfg, msg3_dci);
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return true;
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}
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void fill_dl_dci_ue_fields(const slot_ue& ue,
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const bwp_params& bwp_cfg,
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uint32_t ss_id,
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@ -25,7 +25,8 @@ coreset_region::coreset_region(const bwp_params& bwp_cfg_,
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coreset_id(coreset_id_),
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slot_idx(slot_idx_),
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pdcch_dl_list(dl_list_),
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pdcch_ul_list(ul_list_)
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pdcch_ul_list(ul_list_),
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rar_cce_list(bwp_cfg_.rar_cce_list)
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{
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const bool* res_active = &coreset_cfg->freq_resources[0];
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nof_freq_res = std::count(res_active, res_active + SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE, true);
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@ -181,6 +182,8 @@ srsran::span<const uint32_t> coreset_region::get_cce_loc_table(const alloc_recor
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return record.ue->cfg->cce_pos_list(record.ss_id)[slot_idx][record.aggr_idx];
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case pdcch_grant_type_t::ul_data:
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return record.ue->cfg->cce_pos_list(record.ss_id)[slot_idx][record.aggr_idx];
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case pdcch_grant_type_t::rar:
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return rar_cce_list[slot_idx][record.aggr_idx];
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default:
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break;
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}
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@ -116,13 +116,13 @@ alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint32_t
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// Generate DCI for RAR
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pdcch_dl_t& pdcch = bwp_pdcch_slot.dl_pdcchs.back();
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if (not fill_dci_rar(interv, *bwp_grid.cfg, pdcch.dci)) {
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if (not fill_dci_rar(interv, rar.ra_rnti, *bwp_grid.cfg, pdcch.dci)) {
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// Cancel on-going PDCCH allocation
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bwp_pdcch_slot.coresets[coreset_id]->rem_last_dci();
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return alloc_result::invalid_coderate;
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}
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// Generate RAR PDSCH
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bwp_pdcch_slot.dl_prbs.add(interv);
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bwp_pdcch_slot.dl_prbs |= interv;
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// Generate Msg3 grants in PUSCH
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uint32_t last_msg3 = msg3_rbs.start();
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@ -131,26 +131,22 @@ alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint32_t
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srsran_slot_cfg_t slot_cfg;
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slot_cfg.idx = msg3_slot.slot_idx();
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for (const auto& grant : rar.msg3_grant) {
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slot_ue& ue = ues[grant.temp_crnti];
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bool success = ue.h_ul->new_tx(
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msg3_slot, msg3_slot, prb_interval{last_msg3, last_msg3 + msg3_nof_prbs}, mcs, 100, max_harq_msg3_retx);
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slot_ue& ue = ues[grant.temp_crnti];
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prb_interval msg3_interv{last_msg3, last_msg3 + msg3_nof_prbs};
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bool success = ue.h_ul->new_tx(msg3_slot, msg3_slot, msg3_interv, mcs, 100, max_harq_msg3_retx);
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srsran_assert(success, "Failed to allocate Msg3");
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last_msg3 += msg3_nof_prbs;
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srsran_dci_ul_nr_t msg3_dci; // Create dummy Msg3 DCI
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msg3_dci.ctx.coreset_id = 1;
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msg3_dci.ctx.rnti_type = srsran_rnti_type_ra;
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msg3_dci.ctx.ss_type = srsran_search_space_type_rar;
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msg3_dci.ctx.format = srsran_dci_format_nr_0_0;
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msg3_dci.cc_id = cfg.cc;
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msg3_dci.bwp_id = cfg.bwp_id;
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msg3_dci.rv = 0;
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msg3_dci.mcs = 0;
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msg3_dci.time_domain_assigment = dai++;
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pdcch_ul_t msg3_pdcch;
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fill_dci_msg3(ue, *bwp_grid.cfg, msg3_pdcch.dci);
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msg3_pdcch.dci.time_domain_assigment = dai++;
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bwp_msg3_slot.puschs.emplace_back();
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pusch_t& pusch = bwp_msg3_slot.puschs.back();
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success = ue.cfg->phy().get_pusch_cfg(slot_cfg, msg3_dci, pusch.sch);
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success = ue.cfg->phy().get_pusch_cfg(slot_cfg, msg3_pdcch.dci, pusch.sch);
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srsran_assert(success, "Error converting DCI to PUSCH grant");
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pusch.sch.grant.tb[0].softbuffer.rx = ue.h_ul->get_softbuffer().get();
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if (ue.h_ul->nof_retx() > 0) {
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bwp_pdcch_slot.ul_pdcchs.push_back(msg3_pdcch);
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}
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}
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bwp_msg3_slot.ul_prbs.add(msg3_rbs);
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@ -244,7 +240,7 @@ alloc_result bwp_slot_allocator::alloc_pdsch(slot_ue& ue, const prb_grant& dl_gr
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return alloc_result::success;
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}
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alloc_result bwp_slot_allocator::alloc_pusch(slot_ue& ue, const rbg_bitmap& ul_mask)
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alloc_result bwp_slot_allocator::alloc_pusch(slot_ue& ue, const prb_grant& ul_prbs)
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{
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auto& bwp_pdcch_slot = bwp_grid[ue.pdcch_slot];
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auto& bwp_pusch_slot = bwp_grid[ue.pusch_slot];
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@ -257,9 +253,8 @@ alloc_result bwp_slot_allocator::alloc_pusch(slot_ue& ue, const rbg_bitmap& ul_m
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logger.warning("SCHED: Trying to allocate PUSCH for rnti=0x%x with no available HARQs", ue.rnti);
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return alloc_result::no_rnti_opportunity;
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}
|
||||
pdcch_ul_list_t& pdcchs = bwp_pdcch_slot.ul_pdcchs;
|
||||
const rbg_bitmap& pusch_mask = bwp_pusch_slot.ul_prbs.rbgs();
|
||||
if ((pusch_mask & ul_mask).any()) {
|
||||
pdcch_ul_list_t& pdcchs = bwp_pdcch_slot.ul_pdcchs;
|
||||
if (bwp_pusch_slot.ul_prbs.collides(ul_prbs)) {
|
||||
return alloc_result::sch_collision;
|
||||
}
|
||||
const uint32_t aggr_idx = 2, ss_id = 1;
|
||||
|
@ -273,10 +268,11 @@ alloc_result bwp_slot_allocator::alloc_pusch(slot_ue& ue, const rbg_bitmap& ul_m
|
|||
srsran_assert(ue.cfg->ue_cfg()->fixed_ul_mcs >= 0, "Dynamic MCS not yet supported");
|
||||
int mcs = ue.cfg->ue_cfg()->fixed_ul_mcs;
|
||||
int tbs = 100;
|
||||
bool success = ue.h_ul->new_tx(ue.pusch_slot, ue.pusch_slot, ul_mask, mcs, tbs, ue.cfg->ue_cfg()->maxharq_tx);
|
||||
bool success = ue.h_ul->new_tx(ue.pusch_slot, ue.pusch_slot, ul_prbs, mcs, tbs, ue.cfg->ue_cfg()->maxharq_tx);
|
||||
srsran_assert(success, "Failed to allocate UL HARQ");
|
||||
} else {
|
||||
srsran_assert(ue.h_ul->new_retx(ue.pusch_slot, ue.pusch_slot, ul_mask), "Failed to allocate UL HARQ retx");
|
||||
bool success = ue.h_ul->new_retx(ue.pusch_slot, ue.pusch_slot, ul_prbs);
|
||||
srsran_assert(success, "Failed to allocate UL HARQ retx");
|
||||
}
|
||||
|
||||
// Allocation Successful
|
||||
|
@ -285,7 +281,7 @@ alloc_result bwp_slot_allocator::alloc_pusch(slot_ue& ue, const rbg_bitmap& ul_m
|
|||
fill_ul_dci_ue_fields(ue, *bwp_grid.cfg, ss_id, pdcch.dci.ctx.location, pdcch.dci);
|
||||
pdcch.dci_cfg = ue.cfg->phy().get_dci_cfg();
|
||||
// Generate PUSCH
|
||||
bwp_pusch_slot.ul_prbs |= ul_mask;
|
||||
bwp_pusch_slot.ul_prbs |= ul_prbs;
|
||||
bwp_pusch_slot.puschs.emplace_back();
|
||||
pusch_t& pusch = bwp_pusch_slot.puschs.back();
|
||||
srsran_slot_cfg_t slot_cfg;
|
||||
|
|
|
@ -20,6 +20,13 @@ slot_cc_worker::slot_cc_worker(serv_cell_manager& cc_sched) :
|
|||
cell(cc_sched), cfg(cc_sched.cfg), bwp_alloc(cc_sched.bwps[0].grid), logger(srslog::fetch_basic_logger("MAC"))
|
||||
{}
|
||||
|
||||
void slot_cc_worker::enqueue_cc_event(srsran::move_callback<void()> ev)
|
||||
{
|
||||
std::lock_guard<std::mutex> lock(feedback_mutex);
|
||||
pending_events.emplace_back();
|
||||
pending_events.back() = std::move(ev);
|
||||
}
|
||||
|
||||
void slot_cc_worker::enqueue_cc_feedback(uint16_t rnti, feedback_callback_t fdbk)
|
||||
{
|
||||
std::lock_guard<std::mutex> lock(feedback_mutex);
|
||||
|
@ -33,8 +40,14 @@ void slot_cc_worker::run_feedback(ue_map_t& ue_db)
|
|||
{
|
||||
std::lock_guard<std::mutex> lock(feedback_mutex);
|
||||
tmp_feedback_to_run.swap(pending_feedback);
|
||||
tmp_events_to_run.swap(pending_events);
|
||||
}
|
||||
|
||||
for (srsran::move_callback<void()>& ev : tmp_events_to_run) {
|
||||
ev();
|
||||
}
|
||||
tmp_events_to_run.clear();
|
||||
|
||||
for (feedback_t& f : tmp_feedback_to_run) {
|
||||
if (ue_db.contains(f.rnti) and ue_db[f.rnti]->carriers[cfg.cc] != nullptr) {
|
||||
f.fdbk(*ue_db[f.rnti]->carriers[cfg.cc]);
|
||||
|
@ -102,6 +115,9 @@ void slot_cc_worker::finish()
|
|||
|
||||
void slot_cc_worker::alloc_dl_ues()
|
||||
{
|
||||
if (not cfg.sched_cfg.pdsch_enabled) {
|
||||
return;
|
||||
}
|
||||
if (slot_ues.empty()) {
|
||||
return;
|
||||
}
|
||||
|
@ -110,13 +126,15 @@ void slot_cc_worker::alloc_dl_ues()
|
|||
return;
|
||||
}
|
||||
|
||||
rbgmask_t dlmask(cfg.bwps[0].N_rbg);
|
||||
dlmask.fill(0, dlmask.size(), true);
|
||||
bwp_alloc.alloc_pdsch(ue, dlmask);
|
||||
prb_interval prbs(0, cfg.bwps[0].N_rbg);
|
||||
bwp_alloc.alloc_pdsch(ue, prbs);
|
||||
}
|
||||
|
||||
void slot_cc_worker::alloc_ul_ues()
|
||||
{
|
||||
if (not cfg.sched_cfg.pusch_enabled) {
|
||||
return;
|
||||
}
|
||||
if (slot_ues.empty()) {
|
||||
return;
|
||||
}
|
||||
|
@ -125,9 +143,8 @@ void slot_cc_worker::alloc_ul_ues()
|
|||
return;
|
||||
}
|
||||
|
||||
rbgmask_t ulmask(cfg.bwps[0].N_rbg);
|
||||
ulmask.fill(0, ulmask.size(), true);
|
||||
bwp_alloc.alloc_pusch(ue, ulmask);
|
||||
prb_interval prbs(0, cfg.bwps[0].N_rbg);
|
||||
bwp_alloc.alloc_pusch(ue, prbs);
|
||||
}
|
||||
|
||||
void slot_cc_worker::log_result() const
|
||||
|
@ -169,6 +186,16 @@ void slot_cc_worker::log_result() const
|
|||
ue.h_dl->nof_retx(),
|
||||
srsran_dci_format_nr_string(pdcch.dci.ctx.format),
|
||||
ue.pusch_slot);
|
||||
} else if (pdcch.dci.ctx.rnti_type == srsran_rnti_type_tc) {
|
||||
const slot_ue& ue = slot_ues[pdcch.dci.ctx.rnti];
|
||||
fmt::format_to(fmtbuf,
|
||||
"SCHED: UL Msg3, cc={}, tc-rnti=0x{:x}, pid={}, nrtx={}, f={}, tti_pusch={}",
|
||||
cell.cfg.cc,
|
||||
ue.rnti,
|
||||
pdcch.dci.pid,
|
||||
ue.h_dl->nof_retx(),
|
||||
srsran_dci_format_nr_string(pdcch.dci.ctx.format),
|
||||
ue.pusch_slot);
|
||||
} else {
|
||||
fmt::format_to(fmtbuf, "SCHED: unknown rnti format");
|
||||
}
|
||||
|
@ -198,6 +225,11 @@ void sched_worker_manager::enqueue_event(uint16_t rnti, srsran::move_callback<vo
|
|||
next_slot_events.push_back(ue_event_t{rnti, std::move(ev)});
|
||||
}
|
||||
|
||||
void sched_worker_manager::enqueue_cc_event(uint32_t cc, srsran::move_callback<void()> ev)
|
||||
{
|
||||
cc_worker_list[cc]->worker.enqueue_cc_event(std::move(ev));
|
||||
}
|
||||
|
||||
void sched_worker_manager::run_slot(slot_point slot_tx, uint32_t cc, dl_sched_t& dl_res, ul_sched_t& ul_res)
|
||||
{
|
||||
srsran::bounded_vector<std::condition_variable*, SRSRAN_MAX_CARRIERS> waiting_cvars;
|
||||
|
|
|
@ -73,9 +73,9 @@ private:
|
|||
srsran::phy_cfg_nr_t phy_cfg = {};
|
||||
bool valid = false;
|
||||
|
||||
srsenb::sched_nr sched;
|
||||
srsran::slot_point pdsch_slot, pusch_slot;
|
||||
srslog::basic_logger& sched_logger;
|
||||
std::unique_ptr<srsenb::sched_nr> sched;
|
||||
srsran::slot_point pdsch_slot, pusch_slot;
|
||||
srslog::basic_logger& sched_logger;
|
||||
|
||||
std::mutex metrics_mutex;
|
||||
metrics_t metrics = {};
|
||||
|
@ -291,7 +291,7 @@ private:
|
|||
logger.debug("NACK received!");
|
||||
}
|
||||
|
||||
sched.dl_ack_info(rnti, 0, ack_bit->pid, 0, is_ok);
|
||||
sched->dl_ack_info(rnti, 0, ack_bit->pid, 0, is_ok);
|
||||
}
|
||||
|
||||
// Process SR
|
||||
|
@ -324,7 +324,6 @@ public:
|
|||
rnti(args.rnti),
|
||||
phy_cfg(args.phy_cfg),
|
||||
ss_id(args.ss_id),
|
||||
sched(srsenb::sched_nr_interface::sched_cfg_t{}),
|
||||
use_dummy_sched(args.use_dummy_sched),
|
||||
sched_logger(srslog::fetch_basic_logger("MAC"))
|
||||
{
|
||||
|
@ -332,14 +331,18 @@ public:
|
|||
sched_logger.set_level(srslog::basic_levels::debug);
|
||||
|
||||
// create sched object
|
||||
srsenb::sched_nr_interface::sched_cfg_t sched_cfg{};
|
||||
sched_cfg.pdsch_enabled = args.pdsch.slots != "" and args.pdsch.slots != "none";
|
||||
sched_cfg.pusch_enabled = args.pusch.slots != "" and args.pusch.slots != "none";
|
||||
sched.reset(new srsenb::sched_nr{sched_cfg});
|
||||
std::vector<srsenb::sched_nr_interface::cell_cfg_t> cells_cfg = srsenb::get_default_cells_cfg(1, phy_cfg);
|
||||
sched.cell_cfg(cells_cfg);
|
||||
sched->cell_cfg(cells_cfg);
|
||||
|
||||
// add UE to scheduler
|
||||
srsenb::sched_nr_interface::ue_cfg_t ue_cfg = srsenb::get_default_ue_cfg(1, phy_cfg);
|
||||
ue_cfg.fixed_dl_mcs = args.pdsch.mcs;
|
||||
ue_cfg.fixed_ul_mcs = args.pusch.mcs;
|
||||
sched.ue_cfg(args.rnti, ue_cfg);
|
||||
sched->ue_cfg(args.rnti, ue_cfg);
|
||||
|
||||
dl.mcs = args.pdsch.mcs;
|
||||
ul.mcs = args.pusch.mcs;
|
||||
|
@ -413,7 +416,7 @@ public:
|
|||
}
|
||||
|
||||
if (not use_dummy_sched) {
|
||||
int ret = sched.get_dl_sched(pdsch_slot, 0, dl_sched);
|
||||
int ret = sched->get_dl_sched(pdsch_slot, 0, dl_sched);
|
||||
|
||||
for (pdsch_t& pdsch : dl_sched.pdsch) {
|
||||
// Set TBS
|
||||
|
@ -459,7 +462,7 @@ public:
|
|||
}
|
||||
|
||||
if (not use_dummy_sched) {
|
||||
int ret = sched.get_ul_sched(pusch_slot, 0, ul_sched);
|
||||
int ret = sched->get_ul_sched(pusch_slot, 0, ul_sched);
|
||||
|
||||
for (pusch_t& pusch : ul_sched.pusch) {
|
||||
pusch.data[0] = rx_harq_proc[pusch.pid].get_tb(pusch.sch.grant.tb[0].tbs).data();
|
||||
|
@ -547,14 +550,14 @@ public:
|
|||
void dl_ack_info(uint16_t rnti_, uint32_t cc, uint32_t pid, uint32_t tb_idx, bool ack)
|
||||
{
|
||||
if (not use_dummy_sched) {
|
||||
sched.dl_ack_info(rnti_, cc, pid, tb_idx, ack);
|
||||
sched->dl_ack_info(rnti_, cc, pid, tb_idx, ack);
|
||||
}
|
||||
}
|
||||
|
||||
void ul_crc_info(uint16_t rnti_, uint32_t cc, uint32_t pid, bool crc)
|
||||
{
|
||||
if (not use_dummy_sched) {
|
||||
sched.ul_crc_info(rnti_, cc, pid, crc);
|
||||
sched->ul_crc_info(rnti_, cc, pid, crc);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -612,6 +615,18 @@ public:
|
|||
|
||||
void rach_detected(const rach_info_t& rach_info) override
|
||||
{
|
||||
if (not use_dummy_sched) {
|
||||
srsenb::sched_nr_interface::dl_sched_rar_info_t ra_info;
|
||||
ra_info.preamble_idx = rach_info.preamble;
|
||||
ra_info.ta_cmd = rach_info.time_adv;
|
||||
ra_info.ofdm_symbol_idx = 0;
|
||||
ra_info.msg3_size = 7;
|
||||
ra_info.freq_idx = 0;
|
||||
ra_info.prach_slot = pdsch_slot - TX_ENB_DELAY;
|
||||
ra_info.temp_crnti = rnti;
|
||||
sched->dl_rach_info(0, ra_info);
|
||||
}
|
||||
|
||||
std::unique_lock<std::mutex> lock(metrics_mutex);
|
||||
prach_metrics_t& prach_metrics = metrics.prach[rach_info.preamble];
|
||||
prach_metrics.avg_ta = SRSRAN_VEC_SAFE_CMA((float)rach_info.time_adv, prach_metrics.avg_ta, prach_metrics.count);
|
||||
|
|
Loading…
Reference in New Issue