mirror of https://github.com/rusefi/rusefi.git
global_port.h (#5388)
* global_port.h * global_port.h --------- Co-authored-by: rusefillc <sdfsdfqsf2334234234>
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@ -60,36 +60,6 @@ typedef unsigned int time_t;
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#define EFI_ERROR_CODE 0xffffffff
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#define EFI_ERROR_CODE 0xffffffff
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/**
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#include "global_port.h"
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* rusEfi is placing some of data structures into CCM memory simply
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* in order to use that memory - no magic about which RAM is faster etc.
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* That said, CCM/TCM could be faster as there will be less bus contention
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* with DMA.
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*
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* Please note that DMA does not work with CCM memory
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*/
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#if defined(STM32F4XX)
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// CCM memory is 64k
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#define CCM_OPTIONAL __attribute__((section(".ram4")))
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#define SDRAM_OPTIONAL __attribute__((section(".ram7")))
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#define NO_CACHE // F4 has no cache, do nothing
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#elif defined(STM32F7XX)
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// DTCM memory is 128k
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#define CCM_OPTIONAL __attribute__((section(".ram3")))
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//TODO: update LD file!
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#define SDRAM_OPTIONAL __attribute__((section(".ram7")))
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// SRAM2 is 16k and set to disable dcache
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#define NO_CACHE __attribute__((section(".ram2")))
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#elif defined(STM32H7XX)
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// DTCM memory is 128k
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#define CCM_OPTIONAL __attribute__((section(".ram5")))
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//TODO: update LD file!
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#define SDRAM_OPTIONAL __attribute__((section(".ram8")))
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// SRAM3 is 32k and set to disable dcache
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#define NO_CACHE __attribute__((section(".ram3")))
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#else /* this MCU doesn't need these */
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#define CCM_OPTIONAL
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#define NO_CACHE
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#endif
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#define UNIT_TEST_BUSY_WAIT_CALLBACK() {}
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#define UNIT_TEST_BUSY_WAIT_CALLBACK() {}
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@ -0,0 +1,3 @@
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/* this MCU doesn't need these */
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#define CCM_OPTIONAL
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#define NO_CACHE
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@ -0,0 +1,3 @@
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/* this MCU doesn't need these */
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#define CCM_OPTIONAL
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#define NO_CACHE
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@ -0,0 +1,13 @@
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/**
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* rusEfi is placing some of data structures into CCM memory simply
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* in order to use that memory - no magic about which RAM is faster etc.
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* That said, CCM/TCM could be faster as there will be less bus contention
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* with DMA.
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*
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* Please note that DMA does not work with CCM memory
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*/
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// CCM memory is 64k
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#define CCM_OPTIONAL __attribute__((section(".ram4")))
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#define SDRAM_OPTIONAL __attribute__((section(".ram7")))
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#define NO_CACHE // F4 has no cache, do nothing
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@ -0,0 +1,6 @@
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// DTCM memory is 128k
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#define CCM_OPTIONAL __attribute__((section(".ram3")))
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//TODO: update LD file!
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#define SDRAM_OPTIONAL __attribute__((section(".ram7")))
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// SRAM2 is 16k and set to disable dcache
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#define NO_CACHE __attribute__((section(".ram2")))
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@ -0,0 +1,6 @@
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// DTCM memory is 128k
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#define CCM_OPTIONAL __attribute__((section(".ram5")))
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//TODO: update LD file!
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#define SDRAM_OPTIONAL __attribute__((section(".ram8")))
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// SRAM3 is 32k and set to disable dcache
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#define NO_CACHE __attribute__((section(".ram3")))
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