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zcash-fpga
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updates to enable the ILA core

This commit is contained in:
bsdevlin 2019-07-02 19:41:55 +08:00
parent 692d051e55
commit 001049f6b7
7 changed files with 3357 additions and 3 deletions
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4
aws/cl_zcash/build/scripts/synth_cl_zcash.tcl
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@ -15,6 +15,7 @@
#Param needed to avoid clock name collisions
set_param sta.enableAutoGenClkNamePersistence 0
set_param chipscope.enablePRFlow true
set CL_MODULE $CL_MODULE
set VDEFINES $VDEFINES
@ -99,7 +100,8 @@ read_ip [ list \
#Read IP for virtual jtag / ILA/VIO
read_ip [ list \
$HDK_SHELL_DESIGN_DIR/ip/ila_0/ila_0.xci\
$HDK_SHELL_DESIGN_DIR/ip/ila_0/ila_0.xci \
$CL_DIR/ip/ila_2/ila_2.xci \
$HDK_SHELL_DESIGN_DIR/ip/cl_debug_bridge/cl_debug_bridge.xci \
$HDK_SHELL_DESIGN_DIR/ip/ila_vio_counter/ila_vio_counter.xci \
$HDK_SHELL_DESIGN_DIR/ip/vio_0/vio_0.xci

82
aws/cl_zcash/design/cl_zcash.sv
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@ -25,6 +25,7 @@ module cl_zcash
`include "cl_zcash_defines.vh" // CL Defines for cl_hello_world
localparam USE_AXI4 = "NO";
localparam USE_ILA = "YES";
logic rst_main_n_sync;
@ -231,4 +232,85 @@ zcash_fpga_top (
.axi_lite_if (zcash_axi_lite_if)
);
generate
if (USE_ILA == "YES") begin: ILA_GEN
// Integrated Logic Analyzers (ILA)
ila_0 CL_ILA_0 (
.clk (clk_main_a0),
.probe0 (sh_ocl_awvalid_q),
.probe1 (sh_ocl_awaddr_q ),
.probe2 (ocl_sh_awready_q),
.probe3 (sh_ocl_arvalid_q),
.probe4 (sh_ocl_araddr_q ),
.probe5 (ocl_sh_arready_q)
);
ila_0 CL_ILA_1 (
.clk (clk_main_a0),
.probe0 (ocl_sh_bvalid_q),
.probe1 (sh_cl_glcount0_q),
.probe2 (sh_ocl_bready_q),
.probe3 (ocl_sh_rvalid_q),
.probe4 ({32'b0,ocl_sh_rdata_q[31:0]}),
.probe5 (sh_ocl_rready_q)
);
la_2 CL_ILA_2 (
.clk(clk_main_a0),
.probe0(zcash_fpga_top.bls12_381_top.tx_if.val), // input wire [0:0] probe0
.probe1(zcash_fpga_top.bls12_381_top.tx_if.sop), // input wire [0:0] probe1
.probe2(zcash_fpga_top.bls12_381_top.tx_if.eop), // input wire [0:0] probe2
.probe3(zcash_fpga_top.bls12_381_top.tx_if.rdy), // input wire [0:0] probe3
.probe4(zcash_fpga_top.bls12_381_top.tx_if.dat), // input wire [63:0] probe4
.probe5(zcash_fpga_top.bls12_381_top.interrupt_state), // input wire [7:0] probe5
.probe6(zcash_fpga_top.bls12_381_top.idx_out_if.val), // input wire [0:0] probe6
.probe7(zcash_fpga_top.bls12_381_top.idx_out_if.sop), // input wire [0:0] probe7
.probe8(zcash_fpga_top.bls12_381_top.idx_out_if.eop), // input wire [0:0] probe8
.probe9(zcash_fpga_top.bls12_381_top.idx_out_if.rdy), // input wire [0:0] probe9
.probe10(zcash_fpga_top.bls12_381_top.idx_out_if.dat), // input wire [18:0] probe10
.probe11(zcash_fpga_top.bls12_381_top.interrupt_in_if.val), // input wire [0:0] probe11
.probe12(zcash_fpga_top.bls12_381_top.interrupt_in_if.sop), // input wire [0:0] probe12
.probe13(zcash_fpga_top.bls12_381_top.interrupt_in_if.eop), // input wire [0:0] probe13
.probe14(zcash_fpga_top.bls12_381_top.interrupt_in_if.rdy), // input wire [0:0] probe14
.probe15(zcash_fpga_top.bls12_381_top.interrupt_in_if.dat), // input wire [380:0] probe15
.probe16(zcash_fpga_top.bls12_381_top.interrupt_out_if.val), // input wire [0:0] probe16
.probe17(zcash_fpga_top.bls12_381_top.interrupt_out_if.sop), // input wire [0:0] probe17
.probe18(zcash_fpga_top.bls12_381_top.interrupt_out_if.eop), // input wire [0:0] probe18
.probe19(zcash_fpga_top.bls12_381_top.interrupt_out_if.rdy), // input wire [0:0] probe19
.probe20(zcash_fpga_top.bls12_381_top.interrupt_out_if.dat), // input wire [63:0] probe20
.probe21(zcash_fpga_top.bls12_381_top.curr_inst_pt), // input wire [31:0] probe21
.probe22(zcash_fpga_top.bls12_381_top.inst_state), // input wire [7:0] probe22
.probe23(), // input wire [0:0] probe23
.probe24(), // input wire [0:0] probe24
.probe25(), // input wire [0:0] probe25
.probe26(), // input wire [0:0] probe26
.probe27(), // input wire [0:0] probe27
.probe28(), // input wire [0:0] probe28
.probe29(), // input wire [0:0] probe29
.probe30(), // input wire [0:0] probe30
.probe31() // input wire [0:0] probe31
);
// Debug Bridge
cl_debug_bridge CL_DEBUG_BRIDGE (
.clk(clk_main_a0),
.S_BSCAN_drck(drck),
.S_BSCAN_shift(shift),
.S_BSCAN_tdi(tdi),
.S_BSCAN_update(update),
.S_BSCAN_sel(sel),
.S_BSCAN_tdo(tdo),
.S_BSCAN_tms(tms),
.S_BSCAN_tck(tck),
.S_BSCAN_runtest(runtest),
.S_BSCAN_reset(reset),
.S_BSCAN_capture(capture),
.S_BSCAN_bscanid_en(bscanid_en)
);
end
endgenerate
endmodule

4
aws/cl_zcash/ip/cl_sde_ip_setup.tcl
View File

@ -9,6 +9,7 @@ axis_dwidth_converter_8_to_64/axis_dwidth_converter_8_to_64.xci
axis_dwidth_converter_48_to_8/axis_dwidth_converter_48_to_8.xci
axis_dwidth_converter_4_to_8/axis_dwidth_converter_4_to_8.xci
axis_dwidth_converter_8_to_4/axis_dwidth_converter_8_to_4.xci
ila_2/ila_2.xci
}
upgrade_ip [get_ips *]
@ -19,4 +20,5 @@ generate_target all [get_files axis_dwidth_converter_64_to_8/axis_dwidth_conver
generate_target all [get_files axis_dwidth_converter_8_to_64/axis_dwidth_converter_8_to_64.xci]
generate_target all [get_files axis_dwidth_converter_48_to_8/axis_dwidth_converter_48_to_8.xci]
generate_target all [get_files axis_dwidth_converter_4_to_8/axis_dwidth_converter_4_to_8.xci]
generate_target all [get_files axis_dwidth_converter_8_to_4/axis_dwidth_converter_8_to_4.xci]
generate_target all [get_files axis_dwidth_converter_8_to_4/axis_dwidth_converter_8_to_4.xci]
generate_target all [get_files ila_2/ila_2.xci]

3263
aws/cl_zcash/ip/ila_2.xci Normal file
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File diff suppressed because it is too large Load Diff

3
aws/cl_zcash/ip/mk_clean
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@ -5,4 +5,5 @@ rm -rf axi_fifo_mm_s_0/
rm -rf axis_dwidth_converter_48_to_8/
rm -rf axi_fifo_mm_s_lite/
rm -rf axis_dwidth_converter_4_to_8/
rm -rf axis_dwidth_converter_8_to_4/
rm -rf axis_dwidth_converter_8_to_4/
rm -rf ila_2/

2
aws/cl_zcash/ip/run_cl_sde_ip_flow
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@ -5,6 +5,7 @@ mkdir axis_dwidth_converter_8_to_64
mkdir axis_dwidth_converter_48_to_8
mkdir axis_dwidth_converter_4_to_8
mkdir axis_dwidth_converter_8_to_4
mkdir ila_2
cp axi_fifo_mm_s_0.xci axi_fifo_mm_s_0/axi_fifo_mm_s_0.xci
cp axi_fifo_mm_s_lite.xci axi_fifo_mm_s_lite/axi_fifo_mm_s_lite.xci
@ -13,6 +14,7 @@ cp axis_dwidth_converter_8_to_64.xci axis_dwidth_converter_8_to_64/axis_dwidth_c
cp axis_dwidth_converter_48_to_8.xci axis_dwidth_converter_48_to_8/axis_dwidth_converter_48_to_8.xci
cp axis_dwidth_converter_4_to_8.xci axis_dwidth_converter_4_to_8/axis_dwidth_converter_4_to_8.xci
cp axis_dwidth_converter_8_to_4.xci axis_dwidth_converter_8_to_4/axis_dwidth_converter_8_to_4.xci
cp ila_2.xci ila_2/ila_2.xci
vivado -mode batch -source cl_sde_ip_setup.tcl

2
aws/cl_zcash/verif/scripts/top.vivado.f
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@ -72,6 +72,8 @@ ${CL_ROOT}/ip/axis_dwidth_converter_48_to_8/sim/axis_dwidth_converter_48_to_8.v
${CL_ROOT}/ip/axis_dwidth_converter_4_to_8/sim/axis_dwidth_converter_4_to_8.v
${CL_ROOT}/ip/axis_dwidth_converter_8_to_4/sim/axis_dwidth_converter_8_to_4.v
${CL_ROOT}/ip/ila_2/sim/ila_2.v
-f ${ZCASH_DIR}/zcash_fpga/src/rtl/top/include.f