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debug module

This commit is contained in:
bsdevlin 2019-04-04 14:07:22 -04:00
parent a253e9e2cb
commit 16e1d86ac7
1 changed files with 49 additions and 0 deletions
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ip_cores/util/src/rtl/debug_if.sv Normal file
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/*
Just used to allow debug to be added to an interface in Vivado easily.
Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
module debug_if #(
parameter DAT_BYTS,
parameter DAT_BITS = DAT_BYTS*8,
parameter MOD_BITS = $clog2(DAT_BYTS),
parameter CTL_BITS
) (
if_axi_stream i_if
);
(* mark_debug = "true" *) logic rdy;
(* mark_debug = "true" *) logic val;
(* mark_debug = "true" *) logic err;
(* mark_debug = "true" *) logic sop;
(* mark_debug = "true" *) logic eop;
(* mark_debug = "true" *) logic [CTL_BITS-1:0] ctl;
(* mark_debug = "true" *) logic [DAT_BITS-1:0] dat;
(* mark_debug = "true" *) logic [MOD_BITS-1:0] mod;
always_comb begin
rdy = i_if.rdy;
val = i_if.val;
err = i_if.err;
sop = i_if.sop;
eop = i_if.eop;
ctl = i_if.ctl;
dat = i_if.dat;
mod = i_if.mod;
end
endmodule