UART wrapper
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bsdevlin
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/*
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Wraps around the UART block and provides basic functionality
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Copyright (C) 2019 Benjamin Devlin and Zcash Foundation
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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module uart_wrapper (
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input i_clk,
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input i_rst,
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// Interfaces to UART
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input i_rx_uart,
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output logic o_tx_uart,
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// Interfaces to user logic
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if_axi_stream.source tx_if,
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if_axi_stream.sink rx_if
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);
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(* mark_debug = "true" *) enum {UART_STARTUP, UART_LOOPBACK, UART_STREAM} uart_state;
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(* mark_debug = "true" *) logic interrupt;
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(* mark_debug = "true" *) logic [31:0] uart_axi_wdata, uart_axi_rdata;
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(* mark_debug = "true" *) logic [3:0] uart_axi_awaddr, uart_axi_araddr;
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(* mark_debug = "true" *) logic [1:0] uart_axi_rresp;
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(* mark_debug = "true" *) logic uart_axi_awready, uart_axi_awvalid, uart_axi_arvalid, uart_axi_arready, uart_axi_rvalid, uart_axi_wready;
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(* mark_debug = "true" *) logic sop_l, eop_l;
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always_ff @ (posedge i_clk) begin
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if (i_rst) begin
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uart_axi_wdata <= 0;
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uart_axi_awvalid <= 0;
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uart_axi_arvalid <= 0;
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uart_axi_araddr <= 0;
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uart_state <= UART_STARTUP;
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sop_l <= 0;
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eop_l <= 0;
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tx_if.reset_source();
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rx_if.rdy <= 0;
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end else begin
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if (uart_axi_awvalid && uart_axi_awready) uart_axi_awvalid <= 0;
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if (uart_axi_arvalid && uart_axi_arready) uart_axi_arvalid <= 0;
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if (tx_if.val && tx_if.rdy) tx_if.val <= 0;
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case (uart_state)
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UART_STARTUP: begin
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uart_axi_wdata[4] <= 1; // Enable interrupt
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uart_axi_awvalid <= 1;
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uart_axi_awaddr <= 'hc;
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if (uart_axi_awvalid && uart_axi_awready) begin
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uart_state <= UART_LOOPBACK;
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uart_axi_awaddr <= 'h4;
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end
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end
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UART_LOOPBACK: begin
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// Just read data and put it back on write interface
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uart_axi_araddr <= 0;
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if (interrupt) uart_axi_arvalid <= 1;
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if (uart_axi_rvalid && uart_axi_rresp == 0) begin
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uart_axi_wdata <= uart_axi_rdata;
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uart_axi_awvalid <= 1;
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uart_axi_awaddr <= 'h4;
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// Switch modes if we detect a null character
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if (uart_axi_rdata == 0) begin
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uart_state <= UART_STREAM;
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end
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end
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end
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UART_STREAM: begin
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// In this mode we connect to an axi stream, and create the sop/eop signals based on line return - eop is 8'h0a
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// Data is decoded as hex
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// TODO we should really read fifo status and not interrupt
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if(~sop_l)
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rx_if.rdy <= 1;
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uart_axi_araddr <= 0;
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if (interrupt) uart_axi_arvalid <= 1;
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// Code for rx
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if (uart_axi_rvalid && uart_axi_rresp == 0) begin
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tx_if.dat <= uart_axi_rdata;
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tx_if.val <= 1;
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tx_if.sop <= ~sop_l;
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if (~sop_l) begin
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sop_l <= 1;
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end
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if (uart_axi_rdata == 8'h0a) begin
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tx_if.eop <= 1;
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sop_l <= 0;
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end
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// Switch modes if null character
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if (uart_axi_rdata == 0) begin
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tx_if.val <= 0;
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sop_l <= 0;
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eop_l <= 0;
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uart_state <= UART_LOOPBACK;
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end
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end
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// Logic for tx
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if (rx_if.val && rx_if.rdy) begin
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uart_axi_wdata <= rx_if.dat;
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uart_axi_awvalid <= 1;
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uart_axi_awaddr <= 'h4;
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if (rx_if.eop) begin
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eop_l <= 1;
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rx_if.rdy <= 0;
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end
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end
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if (eop_l && ~uart_axi_awvalid) begin
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uart_axi_wdata <= 8'h0a;
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uart_axi_awvalid <= 1;
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uart_axi_awaddr <= 'h4;
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eop_l <= 0;
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sop_l <= 0;
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end
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end
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endcase
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end
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end
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axi_uartlite_0 uart (
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.s_axi_aclk(i_clk), // input wire s_axi_aclk
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.s_axi_aresetn(~i_rst), // input wire s_axi_aresetn
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.interrupt(interrupt), // output wire interrupt
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.s_axi_awaddr(uart_axi_awaddr), // input wire [3 : 0] s_axi_awaddr
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.s_axi_awvalid(uart_axi_awvalid), // input wire s_axi_awvalid
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.s_axi_awready(uart_axi_awready), // output wire s_axi_awready
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.s_axi_wdata(uart_axi_wdata), // input wire [31 : 0] s_axi_wdata
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.s_axi_wstrb('d0), // input wire [3 : 0] s_axi_wstrb
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.s_axi_wvalid(uart_axi_awvalid), // input wire s_axi_wvalid
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.s_axi_wready(uart_axi_wready), // output wire s_axi_wready
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.s_axi_bresp(), // output wire [1 : 0] s_axi_bresp
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.s_axi_bvalid(), // output wire s_axi_bvalid
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.s_axi_bready(1'b1), // input wire s_axi_bready
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.s_axi_araddr(uart_axi_araddr), // input wire [3 : 0] s_axi_araddr
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.s_axi_arvalid(uart_axi_arvalid), // input wire s_axi_arvalid
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.s_axi_arready(uart_axi_arready), // output wire s_axi_arready
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.s_axi_rdata(uart_axi_rdata), // output wire [31 : 0] s_axi_rdata
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.s_axi_rresp(uart_axi_rresp), // output wire [1 : 0] s_axi_rresp
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.s_axi_rvalid(uart_axi_rvalid), // output wire s_axi_rvalid
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.s_axi_rready(1'd1), // input wire s_axi_rready
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.rx(i_rx_uart), // input wire rx
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.tx(o_tx_uart) // output wire tx
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);
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endmodule
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