bug fix for pipeline, and added in lookahead dbl
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76c394f26b
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@ -26,21 +26,17 @@ module pipeline_if_single #(
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if_axi_stream.source o_if
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);
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// Need pipeline stage to store temp data
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if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) if_r (i_if.i_clk);
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always_ff @ (i_if.i_clk) begin
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always_ff @ (posedge i_if.i_clk) begin
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if (i_rst) begin
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o_if.reset_source();
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if_r.reset_source();
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if_r.rdy <= 0;
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i_if.rdy <= 0;
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end else begin
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i_if.rdy <= ~o_if.val || (o_if.val && o_if.rdy && ~if_r.val);
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i_if.rdy <= ~o_if.val || (o_if.val && o_if.rdy);
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// Data transfer cases
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@ -51,13 +47,14 @@ always_ff @ (i_if.i_clk) begin
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if_r.val <= 0;
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// Second case - second interface not valid
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end else begin
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o_if.copy_if(i_if.dat, i_if.val, i_if.sop, i_if.eop, i_if.err, i_if.mod, i_if.ctl);
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o_if.copy_if(i_if.dat, i_if.val && i_if.rdy, i_if.sop, i_if.eop, i_if.err, i_if.mod, i_if.ctl);
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end
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end
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// Check for case where input is valid so we need to store in second interface
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if (i_if.rdy && (o_if.val && ~o_if.rdy)) begin
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if_r.copy_if(i_if.dat, i_if.val, i_if.sop, i_if.eop, i_if.err, i_if.mod, i_if.ctl);
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i_if.rdy <= 0;
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end
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end
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end
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@ -56,7 +56,7 @@ logic [255:0] k_l;
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jb_point_t p_n, p_q, p_dbl, p_add;
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logic p_dbl_in_val, p_dbl_in_rdy, p_dbl_out_err, p_dbl_out_val, p_dbl_out_rdy, p_dbl_done;
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logic p_add_in_val, p_add_in_rdy, p_add_out_err, p_add_out_val, p_add_out_rdy, p_add_done;
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logic special_dbl;
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logic special_dbl, lookahead_dbl;
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enum {IDLE, DOUBLE_ADD, ADD_ONLY, FINISHED} state;
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@ -77,14 +77,17 @@ always_ff @ (posedge i_clk) begin
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p_dbl_done <= 0;
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p_add_done <= 0;
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special_dbl <= 0;
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lookahead_dbl <= 0;
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end else begin
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p_dbl_out_rdy <= 1;
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p_add_out_rdy <= 1;
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case (state)
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{IDLE}: begin
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p_dbl_out_rdy <= 1;
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p_add_out_rdy <= 1;
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p_dbl_done <= 1;
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p_add_done <= 1;
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special_dbl <= 0;
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lookahead_dbl <= 0;
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o_rdy <= 1;
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o_err <= 0;
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p_q <= 0; // p_q starts at 0
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@ -118,6 +121,12 @@ always_ff @ (posedge i_clk) begin
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special_dbl <= 0;
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end
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p_n <= p_dbl;
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// We can look ahead and start the next double
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if ((k_l >> 1) != 0 && ~lookahead_dbl && ~p_add_done) begin
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p_dbl_in_val <= 1;
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lookahead_dbl <= 1;
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p_dbl_out_rdy <= 0; // Want to make sure we don't output while still waiting for add
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end
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end
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if (p_add_out_val && p_add_out_rdy) begin
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p_add_done <= 1;
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@ -126,6 +135,8 @@ always_ff @ (posedge i_clk) begin
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// Update variables and issue new commands
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if (p_add_done && p_dbl_done) begin
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lookahead_dbl <= 0;
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p_dbl_out_rdy <= 1;
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p_add_done <= 0;
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p_dbl_done <= 0;
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k_l <= k_l >> 1;
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@ -143,7 +154,7 @@ always_ff @ (posedge i_clk) begin
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// Don't need to double on the final bit
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if ((k_l >> 1) != 0)
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p_dbl_in_val <= 1;
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p_dbl_in_val <= ~lookahead_dbl; // Don't do if we already started
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else
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p_dbl_done <= 1;
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