bugfix for pipeline block and added pipelines to arbitrator output

2019-04-15 19:01:06 -04:00 · 2019-04-15 19:01:06 -04:00 · 76c394f26b
parent 34ec3f3b88
commit 76c394f26b
6 changed files with 149 additions and 37 deletions
--- a/ip_cores/common/src/rtl/pipeline_if.sv
+++ b/ip_cores/common/src/rtl/pipeline_if.sv
@ -23,7 +23,7 @@ module pipeline_if  #(
  parameter NUM_STAGES = 1
 ) (
  input i_rst,
-  if_axi_stream   i_if,
+  if_axi_stream i_if,
  if_axi_stream o_if
 );
  
@ -31,34 +31,33 @@ genvar g0;
 generate
  if (NUM_STAGES == 0) begin
    
-    always_comb o_if.copy_if_comb(i_if.dat, i_if.val, i_if.sop, i_if.eop, i_if.err, i_if.mod, i_if.ctl);
+    always_comb begin
+      o_if.copy_if_comb(i_if.dat, i_if.val, i_if.sop, i_if.eop, i_if.err, i_if.mod, i_if.ctl);
+      i_if.rdy = o_if.rdy;
+    end
    
  end else begin
    
-    if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) if_stage [NUM_STAGES-1:0] (i_if.i_clk) ;
+    if_axi_stream #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) if_stage [NUM_STAGES:0] (i_if.i_clk) ;
    
    for (g0 = 0; g0 < NUM_STAGES; g0++) begin : GEN_STAGE
-      if (g0 == 0)
-        pipeline_if_single #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) 
-          pipeline_if_single (
-            .i_rst ( i_rst ),
-            .i_if(i_if ),
-            .o_if(if_stage[g0])
-          );
-        else if (g0 == NUM_STAGES-1)
-          pipeline_if_single #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) 
-            pipeline_if_single (
-              .i_rst ( i_rst ),
-              .i_if(if_stage[g0-1]),
-              .o_if( o_if )
-            );
-         else
-           pipeline_if_single #(.DAT_BYTS(DAT_BYTS), .CTL_BITS(CTL_BITS)) 
-             pipeline_if_single (
-               .i_rst ( i_rst ),
-               .i_if(if_stage[g0-1]),
-               .o_if(if_stage[g0])
-             );
+      pipeline_if_single #(
+        .DAT_BYTS(DAT_BYTS),
+        .CTL_BITS(CTL_BITS)
+      ) 
+      pipeline_if_single (
+        .i_rst ( i_rst ),
+        .i_if(if_stage[g0]),
+        .o_if(if_stage[g0+1])
+      );
+    end
+    
+    always_comb begin
+      o_if.copy_if_comb(if_stage[NUM_STAGES].dat, if_stage[NUM_STAGES].val, if_stage[NUM_STAGES].sop, if_stage[NUM_STAGES].eop, if_stage[NUM_STAGES].err, if_stage[NUM_STAGES].mod, if_stage[NUM_STAGES].ctl);
+      if_stage[NUM_STAGES].rdy = o_if.rdy;
+      
+      if_stage[0].copy_if_comb(i_if.dat, i_if.val, i_if.sop, i_if.eop, i_if.err, i_if.mod, i_if.ctl);
+      i_if.rdy = if_stage[0].rdy;
    end
    
  end
--- a/ip_cores/common/src/tb/pipeline_if_tb.sv
+++ b/ip_cores/common/src/tb/pipeline_if_tb.sv
@ -0,0 +1,93 @@
+/*
+  Copyright (C) 2019  Benjamin Devlin and Zcash Foundation
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program.  If not, see <https://www.gnu.org/licenses/>.
+*/
+`timescale 1ps/1ps
+
+module pipeline_if_tb ();
+import common_pkg::*;
+
+localparam CLK_PERIOD = 100;
+
+
+logic clk, rst;
+
+if_axi_stream #(.DAT_BYTS(8), .CTL_BITS(8)) in_if(clk);
+if_axi_stream #(.DAT_BYTS(8), .CTL_BITS(8)) out_if(clk);
+
+initial begin
+  rst = 0;
+  repeat(2) #(20*CLK_PERIOD) rst = ~rst;
+end
+
+initial begin
+  clk = 0;
+  forever #CLK_PERIOD clk = ~clk;
+end
+
+localparam LEVEL = 2;
+
+pipeline_if  #(
+  .DAT_BYTS (in_if.DAT_BYTS),
+  .CTL_BITS (in_if.CTL_BITS),
+  .NUM_STAGES (LEVEL)
+)
+pipeline_if (
+  .i_rst (rst),
+  .i_if(in_if),
+  .o_if(out_if)
+);
+
+
+task test_pipeline();
+begin
+  integer signed get_len;
+  logic [common_pkg::MAX_SIM_BYTS*8-1:0] expected,  get_dat;
+  integer unsigned size;
+  integer i, max;
+
+  $display("Running test_pipeline...");
+  i = 0;
+  max = 1000;
+
+  #100ns;
+
+  while (i < max) begin
+    size = 1 + ($urandom() % (max-1));
+    expected = random_vector(size);
+    fork
+      in_if.put_stream(expected, size, i);
+      out_if.get_stream(get_dat, get_len);
+    join
+
+    common_pkg::compare_and_print(get_dat, expected);
+    $display("test_pipeline PASSED loop %d/%d", i, max);
+    i = i + 1;
+  end
+
+  $display("test_pipeline PASSED");
+end
+endtask;
+
+initial begin
+  out_if.rdy = 0;
+  in_if.reset_source();
+  #(40*CLK_PERIOD);
+
+  test_pipeline();
+
+  #1us $finish();
+end
+endmodule
--- a/ip_cores/util/src/rtl/resource_share.sv
+++ b/ip_cores/util/src/rtl/resource_share.sv
@ -20,9 +20,10 @@
 */ 

 module resource_share # (
-  parameter NUM_IN,
-  parameter OVR_WRT_BIT,
-  parameter PIPELINE_ARB
+  parameter NUM_IN = 4,
+  parameter OVR_WRT_BIT = 0,
+  parameter PIPELINE_IN = 0,
+  parameter PIPELINE_OUT = 0
 ) (
  input i_clk, i_rst,

@ -39,7 +40,7 @@ packet_arb # (
  .CTL_BITS    ( i_axi[0].CTL_BITS ),
  .NUM_IN      ( NUM_IN       ),
  .OVR_WRT_BIT ( OVR_WRT_BIT  ),
-  .PIPELINE    ( PIPELINE_ARB )
+  .PIPELINE    ( PIPELINE_IN )
 )
 packet_arb_mult (
  .i_clk ( i_clk ),
@ -49,16 +50,30 @@ packet_arb_mult (
 );

 // Demuxing
+if_axi_stream #(.DAT_BYTS(i_res.DAT_BYTS), .CTL_BITS(i_res.CTL_BITS)) int_axi [NUM_IN-1:0] (i_res.i_clk);
+
 genvar gen0;
 logic [NUM_IN-1:0] rdy;
 generate 
  for (gen0 = 0; gen0 < NUM_IN; gen0++) begin: GEN_DEMUX
    always_comb begin
-      rdy[gen0] = o_axi[gen0].rdy;
-      o_axi[gen0].copy_if_comb(i_res.dat, i_res.val && i_res.ctl[OVR_WRT_BIT +: $clog2(NUM_IN)] == gen0,
+      rdy[gen0] = int_axi[gen0].rdy;
+      int_axi[gen0].copy_if_comb(i_res.dat, i_res.val && i_res.ctl[OVR_WRT_BIT +: $clog2(NUM_IN)] == gen0,
          i_res.sop, i_res.eop, i_res.err, i_res.mod, i_res.ctl);
-      o_axi[gen0].ctl[OVR_WRT_BIT +: $clog2(NUM_IN)] = 0;
+      int_axi[gen0].ctl[OVR_WRT_BIT +: $clog2(NUM_IN)] = 0;
    end 
+    
+    pipeline_if  #(
+      .DAT_BYTS   ( i_res.DAT_BYTS ),
+      .CTL_BITS   ( i_res.CTL_BITS ),
+      .NUM_STAGES ( PIPELINE_OUT   )
+    )
+    pipeline_if (
+      .i_rst ( i_rst         ),
+      .i_if  ( int_axi[gen0] ),
+      .o_if  ( o_axi[gen0]   )
+    );
+    
  end
 endgenerate

--- a/zcash_fpga/src/rtl/secp256k1/secp256k1_point_mult.sv
+++ b/zcash_fpga/src/rtl/secp256k1/secp256k1_point_mult.sv
@ -233,7 +233,8 @@ localparam ARB_BIT = 8;
 resource_share # (
  .NUM_IN ( 2 ),
  .OVR_WRT_BIT ( ARB_BIT ),
-  .PIPELINE_ARB ( 0 )
+  .PIPELINE_IN ( 0 ),
+  .PIPELINE_OUT ( 0 )
 )
 resource_share_mod (
  .i_clk ( i_clk ),
@ -247,7 +248,8 @@ resource_share_mod (
 resource_share # (
  .NUM_IN ( 2 ),
  .OVR_WRT_BIT ( ARB_BIT ),
-  .PIPELINE_ARB ( 0 )
+  .PIPELINE_IN ( 0 ),
+  .PIPELINE_OUT ( 0 )
 )
 resource_share_mult (
  .i_clk ( i_clk ),
--- a/zcash_fpga/src/rtl/secp256k1/secp256k1_point_mult_endo.sv
+++ b/zcash_fpga/src/rtl/secp256k1/secp256k1_point_mult_endo.sv
@ -264,7 +264,8 @@ localparam ARB_BIT = 10;
 resource_share # (
  .NUM_IN ( 2 ),
  .OVR_WRT_BIT ( ARB_BIT ),
-  .PIPELINE_ARB ( 1 )
+  .PIPELINE_IN ( 1 ),
+  .PIPELINE_OUT ( 0 )
 )
 resource_share_mod (
  .i_clk ( i_clk ),
@ -278,7 +279,8 @@ resource_share_mod (
 resource_share # (
  .NUM_IN ( 3 ),
  .OVR_WRT_BIT ( ARB_BIT ),
-  .PIPELINE_ARB ( 1 )
+  .PIPELINE_IN ( 1 ),
+  .PIPELINE_OUT ( 0 )
 )
 resource_share_mult (
  .i_clk ( i_clk ),
--- a/zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv
+++ b/zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv
@ -466,7 +466,8 @@ secp256k1_mod (
 resource_share # (
  .NUM_IN ( 2 ),
  .OVR_WRT_BIT ( ARB_BIT ),
-  .PIPELINE_ARB ( 0 )
+  .PIPELINE_IN ( 0 ),
+  .PIPELINE_OUT ( 1 )
 )
 resource_share_mod (
  .i_clk ( i_clk ),
@ -480,7 +481,7 @@ resource_share_mod (
 resource_share # (
  .NUM_IN ( 3 ),
  .OVR_WRT_BIT ( ARB_BIT ),
-  .PIPELINE_ARB ( 0 )
+  .PIPELINE_IN ( 0 )
 )
 resource_share_mult (
  .i_clk ( i_clk ),