bug fix and updates
This commit is contained in:
bsdevlin
parent
ca899c7d17
commit
445a712f60
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@ -4,6 +4,7 @@ class zcash_fpga:
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import serial
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import codecs
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import struct
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import struct
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def byt_to_ver(a):
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return 'v{}.{}.{}'.format(a[2], a[1], a[0])
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@ -12,14 +13,17 @@ class zcash_fpga:
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return a[::-1].decode("utf-8")
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def byt_to_hex(a):
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return a.hex()
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return '0x' + a.hex()
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def byt_to_int(a):
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return int.from_bytes(a, byteorder='little')
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fpga_msg_type_dict = {'FPGA_IGNORE_RPL':int('80000002', 16),
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'FPGA_STATUS_RPL':int('80000001', 16),
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'RESET_FPGA_RPL':int('80000000', 16),
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'VERIFY_SECP256K1_SIG_RPL':int('80000101', 16)}
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fpga_msg_dict = {fpga_msg_type_dict['VERIFY_SECP256K1_SIG_RPL']:{'name':'VERIFY_SECP256K1_SIG_RPL', 'feilds':[(8, 'index', byt_to_hex), (1, 'bm', byt_to_hex), (2, 'cycle_cnt', byt_to_hex)]},
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fpga_msg_dict = {fpga_msg_type_dict['VERIFY_SECP256K1_SIG_RPL']:{'name':'VERIFY_SECP256K1_SIG_RPL', 'feilds':[(8, 'index', byt_to_int), (1, 'bm', byt_to_hex), (2, 'cycle_cnt', byt_to_int)]},
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fpga_msg_type_dict['FPGA_IGNORE_RPL']:{'name':'FPGA_IGNORE_RPL', 'feilds':[(8, 'ignored_header', byt_to_hex)]},
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fpga_msg_type_dict['FPGA_STATUS_RPL']:{'name':'FPGA_STATUS_RPL', 'feilds':[(4, 'version', byt_to_ver), (8, 'build_date', byt_to_str), (8, 'buid_host', byt_to_str), (8, 'cmd_cap', byt_to_hex)]},
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fpga_msg_type_dict['RESET_FPGA_RPL']:{'name':'RESET_FPGA_RPL', 'feilds':[]}}
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@ -27,8 +31,6 @@ class zcash_fpga:
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def __init__(self, COM='COM4'):
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self.s = self.serial.Serial(COM, 921600, timeout=1)
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#Clear any pending messages
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self.get_reply()
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#Test getting FPGA status
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self.get_status()
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print("Connected...")
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@ -51,7 +53,6 @@ class zcash_fpga:
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msg_list = self.parse_reply(res)
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if msg_list and len(msg_list) > 0:
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for msg in msg_list:
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print (msg)
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self.print_reply(msg)
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return msg_list
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else:
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@ -60,15 +61,14 @@ class zcash_fpga:
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def secp256k1_verify_sig(self, index, hsh, r, s, Qx, Qy):
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cmd = '00000101000000B0'
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cmd = format(index, 'x').ljust(16, '0') + cmd
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cmd = format(s, 'x').ljust(64, '0') + cmd
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cmd = format(r, 'x').ljust(64, '0') + cmd
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cmd = format(hsh, 'x').ljust(64, '0') + cmd
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cmd = format(Qx, 'x').ljust(64, '0') + cmd
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cmd = format(Qy, 'x').ljust(64, '0') + cmd
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cmd = format(index, 'x').rjust(16, '0') + cmd
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cmd = format(s, 'x').rjust(64, '0') + cmd
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cmd = format(r, 'x').rjust(64, '0') + cmd
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cmd = format(hsh, 'x').rjust(64, '0') + cmd
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cmd = format(Qx, 'x').rjust(64, '0') + cmd
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cmd = format(Qy, 'x').rjust(64, '0') + cmd
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#Need to swap cmd byte order
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cmd = "".join(reversed([cmd[i:i+2] for i in range(0, len(cmd), 2)]))
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self.s.write(self.codecs.decode(cmd, 'hex'))
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res = self.get_reply()[0] # Just look at the first reply
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if res is not None and (self.struct.unpack('<I', res[4:8])[0] != self.fpga_msg_type_dict['VERIFY_SECP256K1_SIG_RPL']):
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@ -115,7 +115,7 @@ def example_secp256k1_sig():
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zf.reset_fpga() # Reset incase something went wrong last run
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index = 1234
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index = 1
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hsh = 34597931798561447004034205848155169322219865803759328163562698792725658370004
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r = 550117237093786687120086685263208063857013211911888854762107796665370524299
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s = 100440748044460701692736849796872767381221821858945401325418288486792652245963
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@ -40,9 +40,6 @@ logic uart_axi_awready, uart_axi_awvalid, uart_axi_arvalid, uart_axi_arready, ua
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logic [15:0] tx_byt_cnt, tx_byt_len, rx_byt_cnt, rx_byt_len;
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debug_if #(.DAT_BYTS (1), .CTL_BITS (1)) txuart_debug_if (.i_if(tx_if));
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debug_if #(.DAT_BYTS (1), .CTL_BITS (1)) rxuart_debug_if (.i_if(rx_if));
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always_ff @ (posedge i_clk) begin
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if (i_rst) begin
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uart_axi_wdata <= 0;
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@ -33,12 +33,15 @@ module secp256k1_point_dbl
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output logic o_err,
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// Interface to 256bit multiplier (mod p)
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if_axi_stream.source o_mult_if,
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if_axi_stream.source i_mult_if,
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if_axi_stream.sink i_mult_if,
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// Interface to only mod reduction block
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if_axi_stream.source o_mod_if,
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if_axi_stream.source i_mod_if
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if_axi_stream.sink i_mod_if
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);
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debug_if #(.DAT_BYTS (2*256/8), .CTL_BITS (16)) o_mult_debug (.i_if(o_mult_if));
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debug_if #(.DAT_BYTS (256/8), .CTL_BITS (16)) i_mult_debug (.i_if(i_mult_if));
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/*
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* These are the equations that need to be computed, they are issued as variables
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* become valid. We have a bitmask to track what equation results are valid which
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@ -60,7 +63,7 @@ module secp256k1_point_dbl
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* 13. (o_p.z) = 2*(i_p.y) mod p
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* 14. (o_p.z) = o_p.y * i_p.z mod p [eq14]
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*/
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logic [14:0] eq_val, eq_wait;
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(* mark_debug = "true" *) logic [14:0] eq_val, eq_wait;
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// Temporary variables
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logic [255:0] A, B, C, D, E;
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@ -13,8 +13,6 @@ localparam DAT_BYTS = 8;
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localparam DAT_BITS = DAT_BYTS*8;
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import zcash_fpga_pkg::*;
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debug_if #(.DAT_BYTS (8), .CTL_BITS (1)) tx_debug_if (.i_if(if_cmd_rx));
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debug_if #(.DAT_BYTS (8), .CTL_BITS (1)) rx_debug_if (.i_if(if_cmd_tx));
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// 256 bit inverse calculation
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if_axi_stream #(.DAT_BYTS(256/8)) bin_inv_in_if(i_clk);
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@ -45,7 +43,7 @@ typedef enum {IDLE = 0,
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IGNORE = 8,
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FINISHED = 9} secp256k1_state_t;
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(* mark_debug = "true" *) secp256k1_state_t secp256k1_state;
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secp256k1_state_t secp256k1_state;
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header_t header, header_l;
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secp256k1_ver_t secp256k1_ver;
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// Other temporary values
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