update files for AWS
This commit is contained in:
bsdevlin
parent
1971db944d
commit
5c513ef8a7
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setx VIVADO C:\Xilinx\Vivado\2018.3\bin\vivado.bat
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%VIVADO% -mode batch -nojournal -log vivado.log -source create_dcp_from_cl_windows.tcl -tclargs 19_04_22-123549 DEFAULT 1.4.8 0x04261818 0xF002 0x1D0F 0x1D51 0xFEDC A0 B1 C0 2 0
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# Amazon FPGA Hardware Development Kit
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#
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# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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#
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# Licensed under the Amazon Software License (the "License"). You may not use
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# this file except in compliance with the License. A copy of the License is
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# located at
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#
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# http://aws.amazon.com/asl/
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#
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# or in the "license" file accompanying this file. This file is distributed on
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# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
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# implied. See the License for the specific language governing permissions and
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# limitations under the License.
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package require tar
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## Do not edit $TOP
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set TOP top_sp
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## Replace with the name of your module
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set CL_MODULE zcash_cl_sde
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#################################################
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## Command-line Arguments
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#################################################
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set timestamp [lindex $argv 0]
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set strategy [lindex $argv 1]
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set hdk_version [lindex $argv 2]
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set shell_version [lindex $argv 3]
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set device_id [lindex $argv 4]
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set vendor_id [lindex $argv 5]
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set subsystem_id [lindex $argv 6]
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set subsystem_vendor_id [lindex $argv 7]
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set clock_recipe_a [lindex $argv 8]
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set clock_recipe_b [lindex $argv 9]
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set clock_recipe_c [lindex $argv 10]
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set uram_option [lindex $argv 11]
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set notify_via_sns [lindex $argv 12]
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##################################################
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## Flow control variables
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##################################################
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set cl.synth 1
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set implement 1
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#################################################
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## Generate CL_routed.dcp (Done by User)
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#################################################
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puts "AWS FPGA Scripts";
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puts "Creating Design Checkpoint from Custom Logic source code";
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puts "HDK Version: $hdk_version";
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puts "Shell Version: $shell_version";
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puts "Vivado Script Name: $argv0";
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puts "Strategy: $strategy";
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puts "PCI Device ID $device_id";
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puts "PCI Vendor ID $vendor_id";
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puts "PCI Subsystem ID $subsystem_id";
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puts "PCI Subsystem Vendor ID $subsystem_vendor_id";
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puts "Clock Recipe A: $clock_recipe_a";
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puts "Clock Recipe B: $clock_recipe_b";
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puts "Clock Recipe C: $clock_recipe_c";
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puts "URAM option: $uram_option";
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puts "Notify when done: $notify_via_sns";
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set CL_DIR {C:\Users\bsdevlin\git\aws-fpga\hdk\cl\developer_designs\zcash_fpga}
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set HDK_SHELL_DIR {C:\Users\bsdevlin\git\aws-fpga\hdk\common\shell_v04261818}
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set HDK_SHELL_DESIGN_DIR {C:\Users\bsdevlin\git\aws-fpga\hdk\common\shell_v04261818\design}
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set ZCASH_DIR {C:\Users\bsdevlin\git\zcash-fpga}
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##################################################
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### Output Directories used by step_user.tcl
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##################################################
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set implDir $CL_DIR/build/checkpoints
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set rptDir $CL_DIR/build/reports
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set cacheDir $HDK_SHELL_DESIGN_DIR/cache/ddr4_phy
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puts "All reports and intermediate results will be time stamped with $timestamp";
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set_msg_config -id {Chipscope 16-3} -suppress
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set_msg_config -string {AXI_QUAD_SPI} -suppress
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# Suppress Warnings
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# These are to avoid warning messages that may not be real issues. A developer
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# may comment them out if they wish to see more information from warning
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# messages.
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set_msg_config -id {Common 17-55} -suppress
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set_msg_config -id {Designutils 20-1567} -suppress
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set_msg_config -id {IP_Flow 19-2162} -suppress
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set_msg_config -id {Project 1-498} -suppress
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set_msg_config -id {Route 35-328} -suppress
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set_msg_config -id {Vivado 12-508} -suppress
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set_msg_config -id {Constraints 18-4866} -suppress
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set_msg_config -id {filemgmt 56-12} -suppress
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set_msg_config -id {Constraints 18-4644} -suppress
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set_msg_config -id {Coretcl 2-64} -suppress
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set_msg_config -id {Vivado 12-4739} -suppress
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set_msg_config -id {Vivado 12-5201} -suppress
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set_msg_config -id {DRC CKLD-1} -suppress
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set_msg_config -id {IP_Flow 19-2248} -suppress
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set_msg_config -id {Opt 31-155} -suppress
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set_msg_config -id {Synth 8-115} -suppress
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set_msg_config -id {Synth 8-3936} -suppress
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set_msg_config -id {Vivado 12-1023} -suppress
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set_msg_config -id {Constraints 18-550} -suppress
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set_msg_config -id {Synth 8-3295} -suppress
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set_msg_config -id {Synth 8-3321} -suppress
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set_msg_config -id {Synth 8-3331} -suppress
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set_msg_config -id {Synth 8-3332} -suppress
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set_msg_config -id {Synth 8-350} -suppress
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set_msg_config -id {Synth 8-3848} -suppress
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set_msg_config -id {Synth 8-3917} -suppress
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set_msg_config -id {Synth 8-6014} -suppress
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set_msg_config -id {Vivado 12-1580} -suppress
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set_msg_config -id {Constraints 18-619} -suppress
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set_msg_config -id {DRC CKLD-2} -suppress
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set_msg_config -id {DRC REQP-1853} -suppress
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set_msg_config -id {Timing 38-436} -suppress
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
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# Check that an email address has been set, else unset notify_via_sns
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if {[string compare $notify_via_sns "1"] == 0} {
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if {![info exists env(EMAIL)]} {
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) EMAIL variable empty! Completition notification will *not* be sent!";
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set notify_via_sns 0;
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} else {
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) EMAIL address for completion notification set to $env(EMAIL).";
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}
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}
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##################################################
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### Strategy options
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##################################################
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switch $strategy {
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"BASIC" {
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puts "BASIC strategy."
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source $HDK_SHELL_DIR\\build\\scripts\\strategy_BASIC.tcl
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}
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"EXPLORE" {
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puts "EXPLORE strategy."
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source $HDK_SHELL_DIR\\build\\scripts\\strategy_EXPLORE.tcl
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}
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"TIMING" {
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puts "TIMING strategy."
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source $HDK_SHELL_DIR\build\scripts\strategy_TIMING.tcl
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}
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"CONGESTION" {
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puts "CONGESTION strategy."
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source $HDK_SHELL_DIR/build/scripts/strategy_CONGESTION.tcl
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}
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"DEFAULT" {
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puts "DEFAULT strategy."
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source $HDK_SHELL_DIR\\build\\scripts\\strategy_DEFAULT.tcl
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}
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default {
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puts "$strategy is NOT a valid strategy. Defaulting to strategy DEFAULT."
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source $HDK_SHELL_DIR/build/scripts/strategy_DEFAULT.tcl
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}
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}
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#Encrypt source code
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source encrypt.tcl
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#Set the Device Type
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source $HDK_SHELL_DIR/build/scripts/device_type.tcl
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#Procedure for running various implementation steps (impl_step)
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source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
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########################################
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## Generate clocks based on Recipe
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########################################
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
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source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
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#################################################################
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##### Do not remove this setting. Need to workaround bug in Vivado
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##################################################################
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set_param hd.clockRoutingWireReduction false
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##################################################
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### CL XPR OOC Synthesis
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##################################################
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if {${cl.synth}} {
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source -notrace ./synth_${CL_MODULE}.tcl
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}
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##################################################
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### Implementation
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##################################################
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if {$implement} {
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########################
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# Link Design
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########################
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if {$link} {
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####Create in-memory prjoect and setup IP cache location
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create_project -part [DEVICE_TYPE] -in_memory
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set_property IP_REPO_PATHS $cacheDir [current_project]
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puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Combining Shell and CL design checkpoints";
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add_files $HDK_SHELL_DIR/build/checkpoints/from_aws/SH_CL_BB_routed.dcp
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add_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp
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set_property SCOPED_TO_CELLS {WRAPPER_INST/CL} [get_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp]
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#Read the constraints, note *DO NOT* read cl_clocks_aws (clocks originating from AWS shell)
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read_xdc [ list \
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$CL_DIR/build/constraints/cl_pnr_user.xdc
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]
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set_property PROCESSING_ORDER late [get_files cl_pnr_user.xdc]
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puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running link_design";
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link_design -top $TOP -part [DEVICE_TYPE] -reconfig_partitions {WRAPPER_INST/SH WRAPPER_INST/CL}
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puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - PLATFORM.IMPL==[get_property PLATFORM.IMPL [current_design]]";
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##################################################
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# Apply Clock Properties for Clock Table Recipes
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##################################################
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. ";
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# Apply properties to clocks
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source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl
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# Write post-link checkpoint
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puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Writing post-link_design checkpoint ${timestamp}.post_link.dcp";
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write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.post_link.dcp
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}
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########################
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# CL Optimize
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########################
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if {$opt} {
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puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running optimization";
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impl_step opt_design $TOP $opt_options $opt_directive $opt_preHookTcl $opt_postHookTcl
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if {$psip} {
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impl_step opt_design $TOP "-merge_equivalent_drivers -sweep"
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}
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}
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########################
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# CL Place
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########################
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if {$place} {
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puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running placement";
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if {$psip} {
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append place_options " -fanout_opt"
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}
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impl_step place_design $TOP $place_options $place_directive $place_preHookTcl $place_postHookTcl
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}
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##############################
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# CL Post-Place Optimization
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##############################
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if {$phys_opt} {
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puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-place optimization";
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impl_step phys_opt_design $TOP $phys_options $phys_directive $phys_preHookTcl $phys_postHookTcl
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}
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########################
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# CL Route
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########################
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if {$route} {
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puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Routing design";
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impl_step route_design $TOP $route_options $route_directive $route_preHookTcl $route_postHookTcl
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}
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##############################
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# CL Post-Route Optimization
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##############################
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set SLACK [get_property SLACK [get_timing_paths]]
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#Post-route phys_opt will not be run if slack is positive or greater than -200ps.
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if {$route_phys_opt && $SLACK > -0.400 && $SLACK < 0} {
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puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-route optimization";
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impl_step route_phys_opt_design $TOP $post_phys_options $post_phys_directive $post_phys_preHookTcl $post_phys_postHookTcl
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}
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##############################
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# Final Implmentation Steps
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##############################
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# Report final timing
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report_timing_summary -file $CL_DIR/build/reports/${timestamp}.SH_CL_final_timing_summary.rpt
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# This is what will deliver to AWS
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Writing final DCP to to_aws directory.";
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write_checkpoint -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp
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# Generate debug probes file
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write_debug_probes -force -no_partial_ltxfile -file $CL_DIR/build/checkpoints/${timestamp}.debug_probes.ltx
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close_project
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}
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# ################################################
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# Create Manifest and Tarball for delivery
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# ################################################
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# Create a zipped tar file, that would be used for createFpgaImage EC2 API
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Compress files for sending to AWS. "
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# Create manifest file
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set manifest_file [open "$CL_DIR/build/checkpoints/to_aws/${timestamp}.manifest.txt" w]
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set hash [lindex [split [exec sha256sum $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp] ] 0]
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set TOOL_VERSION $::env(VIVADO_TOOL_VERSION)
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set vivado_version [string range [version -short] 0 5]
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puts "vivado_version is $vivado_version\n"
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puts $manifest_file "manifest_format_version=2\n"
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puts $manifest_file "pci_vendor_id=$vendor_id\n"
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puts $manifest_file "pci_device_id=$device_id\n"
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puts $manifest_file "pci_subsystem_id=$subsystem_id\n"
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puts $manifest_file "pci_subsystem_vendor_id=$subsystem_vendor_id\n"
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puts $manifest_file "dcp_hash=$hash\n"
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puts $manifest_file "shell_version=$shell_version\n"
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puts $manifest_file "tool_version=v$vivado_version\n"
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puts $manifest_file "dcp_file_name=${timestamp}.SH_CL_routed.dcp\n"
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puts $manifest_file "hdk_version=$hdk_version\n"
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puts $manifest_file "date=$timestamp\n"
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puts $manifest_file "clock_recipe_a=$clock_recipe_a\n"
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puts $manifest_file "clock_recipe_b=$clock_recipe_b\n"
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puts $manifest_file "clock_recipe_c=$clock_recipe_c\n"
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close $manifest_file
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# Delete old tar file with same name
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if { [file exists $CL_DIR/build/checkpoints/to_aws/${timestamp}.Developer_CL.tar] } {
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puts "Deleting old tar file with same name.";
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file delete -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.Developer_CL.tar
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}
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# Tar checkpoint to aws
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cd $CL_DIR/build/checkpoints
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tar::create to_aws/${timestamp}.Developer_CL.tar [glob to_aws/${timestamp}*]
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Finished creating final tar file in to_aws directory.";
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if {[string compare $notify_via_sns "1"] == 0} {
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Calling notification script to send e-mail to $env(EMAIL)";
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exec $env(HDK_COMMON_DIR)/scripts/notify_via_sns.py
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}
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";
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@ -18,23 +18,25 @@
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# Add check if /build and /build/src_port_encryption directories exist
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# Add check if the vivado_keyfile exist
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set ZCASH_DIR $::env(ZCASH_DIR)
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set HDK_SHELL_DIR $::env(HDK_SHELL_DIR)
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set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR)
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set CL_DIR $::env(CL_DIR)
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#set ZCASH_DIR $::env(ZCASH_DIR)
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#set HDK_SHELL_DIR $::env(HDK_SHELL_DIR)
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#set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR)
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#set CL_DIR $::env(CL_DIR)
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set TARGET_DIR $CL_DIR/build/src_post_encryption
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set UNUSED_TEMPLATES_DIR $HDK_SHELL_DESIGN_DIR/interfaces
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# Remove any previously encrypted files, that may no longer be used
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exec rm -f $TARGET_DIR/*
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#exec del -f $TARGET_DIR/*
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#---- Developr would replace this section with design files ----
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## Change file names and paths below to reflect your CL area. DO NOT include AWS RTL files.
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set fileName "${ZCASH_DIR}/zcash_fpga/src/rtl/top/include.f"
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catch {set fptr [open $fileName r]} ;
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set contents [read -nonewline $fptr] ;#Read the file contents
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@ -99,7 +101,7 @@ file copy -force $CL_DIR/design/axi_prot_chk.sv $TARGET_DIR
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# Make sure files have write permissions for the encryption
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exec chmod +w {*}[glob $TARGET_DIR/*]
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#exec chmod +w {*}[glob $TARGET_DIR/*]
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# encrypt .v/.sv/.vh/inc as verilog files
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#encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
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@ -0,0 +1,146 @@
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# Amazon FPGA Hardware Development Kit
|
||||
#
|
||||
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
#
|
||||
# Licensed under the Amazon Software License (the "License"). You may not use
|
||||
# this file except in compliance with the License. A copy of the License is
|
||||
# located at
|
||||
#
|
||||
# http://aws.amazon.com/asl/
|
||||
#
|
||||
# or in the "license" file accompanying this file. This file is distributed on
|
||||
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
|
||||
# implied. See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
#Param needed to avoid clock name collisions
|
||||
set_param sta.enableAutoGenClkNamePersistence 0
|
||||
set CL_MODULE $CL_MODULE
|
||||
|
||||
create_project -in_memory -part [DEVICE_TYPE] -force
|
||||
|
||||
########################################
|
||||
## Generate clocks based on Recipe
|
||||
########################################
|
||||
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
|
||||
|
||||
source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
|
||||
|
||||
#############################
|
||||
## Read design files
|
||||
#############################
|
||||
|
||||
#Convenience to set the root of the RTL directory
|
||||
set ENC_SRC_DIR $CL_DIR\\build\\src_post_encryption
|
||||
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's Custom Logic files post encryption.";
|
||||
|
||||
#---- User would replace this section -----
|
||||
|
||||
# Reading the .sv and .v files, as proper designs would not require
|
||||
# reading .v, .vh, nor .inc files
|
||||
|
||||
read_verilog -sv [glob ../src_post_encryption/*.v]
|
||||
read_verilog -sv [glob ../src_post_encryption/*.sv]
|
||||
|
||||
#---- End of section replaced by User ----
|
||||
|
||||
puts "AWS FPGA: Reading AWS Shell design";
|
||||
|
||||
#Read AWS Design files
|
||||
read_verilog [ list \
|
||||
$HDK_SHELL_DESIGN_DIR/lib/lib_pipe.sv \
|
||||
$HDK_SHELL_DESIGN_DIR/lib/bram_2rw.sv \
|
||||
$HDK_SHELL_DESIGN_DIR/lib/flop_fifo.sv \
|
||||
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sync.v \
|
||||
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv \
|
||||
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v \
|
||||
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_acc_axl.sv \
|
||||
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_gen_axl.sv \
|
||||
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sh_ddr.sv \
|
||||
$HDK_SHELL_DESIGN_DIR/interfaces/cl_ports.vh
|
||||
]
|
||||
|
||||
puts "AWS FPGA: Reading IP blocks";
|
||||
|
||||
# User IP
|
||||
read_ip [ list \
|
||||
$CL_DIR/ip/axis_dwidth_converter_64_to_8/axis_dwidth_converter_64_to_8.xci \
|
||||
$CL_DIR/ip/axis_dwidth_converter_8_to_64/axis_dwidth_converter_8_to_64.xci
|
||||
]
|
||||
|
||||
puts "AWS FPGA: Generating IP blocks";
|
||||
|
||||
set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_64_to_8.xci]
|
||||
set_property generate_synth_checkpoint false [get_files axis_dwidth_converter_8_to_64.xci]
|
||||
|
||||
generate_target all [get_ips axis_dwidth_converter_64_to_8]
|
||||
generate_target all [get_ips axis_dwidth_converter_8_to_64]
|
||||
|
||||
#Read DDR IP
|
||||
read_ip [ list \
|
||||
$HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci
|
||||
]
|
||||
|
||||
#Read IP for axi register slices
|
||||
read_ip [ list \
|
||||
$HDK_SHELL_DESIGN_DIR/ip/axi_register_slice/axi_register_slice.xci \
|
||||
$HDK_SHELL_DESIGN_DIR/ip/axi_register_slice_light/axi_register_slice_light.xci
|
||||
]
|
||||
|
||||
#Read IP for virtual jtag / ILA/VIO
|
||||
read_ip [ list \
|
||||
$HDK_SHELL_DESIGN_DIR/ip/cl_debug_bridge/cl_debug_bridge.xci \
|
||||
$CL_DIR/ip/ila_axi4/ila_axi4.xci \
|
||||
$CL_DIR/ip/ila_axi4_512/ila_axi4_512.xci \
|
||||
$CL_DIR/ip/ila_axis/ila_axis.xci \
|
||||
$CL_DIR/ip/ila_sde_c2h_dm/ila_sde_c2h_dm.xci \
|
||||
$CL_DIR/ip/ila_sde_h2c_dm/ila_sde_h2c_dm.xci \
|
||||
$CL_DIR/ip/ila_sde_c2h_buf/ila_sde_c2h_buf.xci \
|
||||
$CL_DIR/ip/ila_sde_h2c_buf/ila_sde_h2c_buf.xci \
|
||||
$CL_DIR/ip/ila_sde_wb/ila_sde_wb.xci \
|
||||
$CL_DIR/ip/ila_sde_ps/ila_sde_ps.xci
|
||||
]
|
||||
|
||||
puts "AWS FPGA: Reading AWS constraints";
|
||||
|
||||
#Read all the constraints
|
||||
#
|
||||
# cl_clocks_aws.xdc - AWS auto-generated clock constraint. ***DO NOT MODIFY***
|
||||
# cl_ddr.xdc - AWS provided DDR pin constraints. ***DO NOT MODIFY***
|
||||
# cl_synth_user.xdc - Developer synthesis constraints.
|
||||
read_xdc [ list \
|
||||
$CL_DIR/build/constraints/cl_clocks_aws.xdc \
|
||||
$HDK_SHELL_DIR/build/constraints/cl_ddr.xdc \
|
||||
$HDK_SHELL_DIR/build/constraints/cl_synth_aws.xdc \
|
||||
$CL_DIR/build/constraints/cl_synth_user.xdc
|
||||
]
|
||||
|
||||
#Do not propagate local clock constraints for clocks generated in the SH
|
||||
set_property USED_IN {synthesis implementation OUT_OF_CONTEXT} [get_files cl_clocks_aws.xdc]
|
||||
set_property PROCESSING_ORDER EARLY [get_files cl_clocks_aws.xdc]
|
||||
|
||||
########################
|
||||
# CL Synthesis
|
||||
########################
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthesis.";
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
|
||||
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
|
||||
|
||||
set failval [catch {exec grep "FAIL" failfast.csv}]
|
||||
if { $failval==0 } {
|
||||
puts "AWS FPGA: FATAL ERROR--Resource utilization error; check failfast.csv for details"
|
||||
exit 1
|
||||
}
|
||||
|
||||
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) writing post synth checkpoint.";
|
||||
write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp
|
||||
#write_checkpoint -force $CL_DIR/build/checkpoints/CL.post_synth.dcp
|
||||
|
||||
|
||||
close_project
|
||||
#Set param back to default value
|
||||
set_param sta.enableAutoGenClkNamePersistence 1
|
||||
|
|
@ -248,7 +248,7 @@ logic rst_if, rst_100, rst_200, rst_300;
|
|||
always_comb begin
|
||||
clk_if = clk_main_a0;
|
||||
clk_100 = clk_main_a0; // 125MHz
|
||||
clk_200 = clk_extra_a2; // 187MHz
|
||||
clk_200 = clk_main_a0; // 187MHz
|
||||
clk_300 = clk_extra_b0; // 300MHz
|
||||
end
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue