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zcash-fpga
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Bugfix for cycle count

This commit is contained in:
bsdevlin 2019-04-11 10:09:24 -04:00
parent b9e5c42b8e
commit aa2d2c1bba
1 changed files with 2 additions and 2 deletions
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4
zcash_fpga/src/rtl/secp256k1/secp256k1_top.sv
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@ -319,7 +319,7 @@ always_ff @ (posedge i_clk) begin
end
{3}: begin
cnt <= $bits(verify_secp256k1_sig_rpl_t)/8;
msg <= verify_secp256k1_sig_rpl(secp256k1_ver, index);
msg <= verify_secp256k1_sig_rpl(secp256k1_ver, index, timeout);
secp256k1_state <= FINISHED;
end
endcase
@ -386,7 +386,7 @@ always_ff @ (posedge i_clk) begin
end
if (secp256k1_ver.TIMEOUT_FAIL && secp256k1_state != FINISHED) begin
cnt <= $bits(verify_secp256k1_sig_rpl_t)/8;
msg <= verify_secp256k1_sig_rpl(secp256k1_ver, index);
msg <= verify_secp256k1_sig_rpl(secp256k1_ver, index, timeout);
secp256k1_state <= FINISHED;
end
end