Top level files

bittware_xupvvh/synth/bittware_xupvvh_top.xdc

@@ -129,6 +129,67 @@ connect_debug_port u_ila_1/probe21 [get_nets [list uart_wrapper/uart_debug_if/rd
 connect_debug_port u_ila_1/probe24 [get_nets [list uart_wrapper/uart_debug_if/sop]]
 connect_debug_port u_ila_1/probe31 [get_nets [list uart_wrapper/uart_debug_if/val]]
 
+connect_debug_port u_ila_0/probe0 [get_nets [list {zcash_fpga_top/control_top/debug_if2/dat[0]} {zcash_fpga_top/control_top/debug_if2/dat[1]} {zcash_fpga_top/control_top/debug_if2/dat[2]} {zcash_fpga_top/control_top/debug_if2/dat[3]} {zcash_fpga_top/control_top/debug_if2/dat[4]} {zcash_fpga_top/control_top/debug_if2/dat[5]} {zcash_fpga_top/control_top/debug_if2/dat[6]} {zcash_fpga_top/control_top/debug_if2/dat[7]}]]
+connect_debug_port u_ila_0/probe1 [get_nets [list {uart_wrapper/rx_byt_len[0]} {uart_wrapper/rx_byt_len[1]} {uart_wrapper/rx_byt_len[2]} {uart_wrapper/rx_byt_len[3]} {uart_wrapper/rx_byt_len[4]} {uart_wrapper/rx_byt_len[5]} {uart_wrapper/rx_byt_len[6]} {uart_wrapper/rx_byt_len[7]} {uart_wrapper/rx_byt_len[8]} {uart_wrapper/rx_byt_len[9]} {uart_wrapper/rx_byt_len[10]} {uart_wrapper/rx_byt_len[11]} {uart_wrapper/rx_byt_len[12]} {uart_wrapper/rx_byt_len[13]} {uart_wrapper/rx_byt_len[14]} {uart_wrapper/rx_byt_len[15]}]]
+connect_debug_port u_ila_0/probe2 [get_nets [list {uart_wrapper/rx_byt_cnt[0]} {uart_wrapper/rx_byt_cnt[1]} {uart_wrapper/rx_byt_cnt[2]} {uart_wrapper/rx_byt_cnt[3]} {uart_wrapper/rx_byt_cnt[4]} {uart_wrapper/rx_byt_cnt[5]} {uart_wrapper/rx_byt_cnt[6]} {uart_wrapper/rx_byt_cnt[7]} {uart_wrapper/rx_byt_cnt[8]} {uart_wrapper/rx_byt_cnt[9]} {uart_wrapper/rx_byt_cnt[10]} {uart_wrapper/rx_byt_cnt[11]} {uart_wrapper/rx_byt_cnt[12]} {uart_wrapper/rx_byt_cnt[13]} {uart_wrapper/rx_byt_cnt[14]} {uart_wrapper/rx_byt_cnt[15]}]]
+connect_debug_port u_ila_0/probe3 [get_nets [list {uart_wrapper/tx_byt_cnt[0]} {uart_wrapper/tx_byt_cnt[1]} {uart_wrapper/tx_byt_cnt[2]} {uart_wrapper/tx_byt_cnt[3]} {uart_wrapper/tx_byt_cnt[4]} {uart_wrapper/tx_byt_cnt[5]} {uart_wrapper/tx_byt_cnt[6]} {uart_wrapper/tx_byt_cnt[7]} {uart_wrapper/tx_byt_cnt[8]} {uart_wrapper/tx_byt_cnt[9]} {uart_wrapper/tx_byt_cnt[10]} {uart_wrapper/tx_byt_cnt[11]} {uart_wrapper/tx_byt_cnt[12]} {uart_wrapper/tx_byt_cnt[13]} {uart_wrapper/tx_byt_cnt[14]} {uart_wrapper/tx_byt_cnt[15]}]]
+connect_debug_port u_ila_0/probe4 [get_nets [list {uart_wrapper/uart_axi_araddr[0]} {uart_wrapper/uart_axi_araddr[1]} {uart_wrapper/uart_axi_araddr[2]} {uart_wrapper/uart_axi_araddr[3]}]]
+connect_debug_port u_ila_0/probe6 [get_nets [list {uart_wrapper/uart_axi_bresp[1]}]]
+connect_debug_port u_ila_0/probe12 [get_nets [list {uart_wrapper/uart_axi_wdata[0]} {uart_wrapper/uart_axi_wdata[1]} {uart_wrapper/uart_axi_wdata[2]} {uart_wrapper/uart_axi_wdata[3]} {uart_wrapper/uart_axi_wdata[4]} {uart_wrapper/uart_axi_wdata[5]} {uart_wrapper/uart_axi_wdata[6]} {uart_wrapper/uart_axi_wdata[7]} {uart_wrapper/uart_axi_wdata[8]} {uart_wrapper/uart_axi_wdata[9]} {uart_wrapper/uart_axi_wdata[10]} {uart_wrapper/uart_axi_wdata[11]} {uart_wrapper/uart_axi_wdata[12]} {uart_wrapper/uart_axi_wdata[13]} {uart_wrapper/uart_axi_wdata[14]} {uart_wrapper/uart_axi_wdata[15]} {uart_wrapper/uart_axi_wdata[16]} {uart_wrapper/uart_axi_wdata[17]} {uart_wrapper/uart_axi_wdata[18]} {uart_wrapper/uart_axi_wdata[19]} {uart_wrapper/uart_axi_wdata[20]} {uart_wrapper/uart_axi_wdata[21]} {uart_wrapper/uart_axi_wdata[22]} {uart_wrapper/uart_axi_wdata[23]} {uart_wrapper/uart_axi_wdata[24]} {uart_wrapper/uart_axi_wdata[25]} {uart_wrapper/uart_axi_wdata[26]} {uart_wrapper/uart_axi_wdata[27]} {uart_wrapper/uart_axi_wdata[28]} {uart_wrapper/uart_axi_wdata[29]} {uart_wrapper/uart_axi_wdata[30]} {uart_wrapper/uart_axi_wdata[31]}]]
+connect_debug_port u_ila_0/probe13 [get_nets [list {uart_wrapper/uart_state[0]} {uart_wrapper/uart_state[1]} {uart_wrapper/uart_state[2]} {uart_wrapper/uart_state[3]} {uart_wrapper/uart_state[4]} {uart_wrapper/uart_state[5]} {uart_wrapper/uart_state[6]} {uart_wrapper/uart_state[7]} {uart_wrapper/uart_state[8]} {uart_wrapper/uart_state[9]} {uart_wrapper/uart_state[10]} {uart_wrapper/uart_state[11]} {uart_wrapper/uart_state[12]} {uart_wrapper/uart_state[13]} {uart_wrapper/uart_state[14]} {uart_wrapper/uart_state[15]} {uart_wrapper/uart_state[16]} {uart_wrapper/uart_state[17]} {uart_wrapper/uart_state[18]} {uart_wrapper/uart_state[19]} {uart_wrapper/uart_state[20]} {uart_wrapper/uart_state[21]} {uart_wrapper/uart_state[22]} {uart_wrapper/uart_state[23]} {uart_wrapper/uart_state[24]} {uart_wrapper/uart_state[25]} {uart_wrapper/uart_state[26]} {uart_wrapper/uart_state[27]} {uart_wrapper/uart_state[28]} {uart_wrapper/uart_state[29]} {uart_wrapper/uart_state[30]} {uart_wrapper/uart_state[31]}]]
+connect_debug_port u_ila_0/probe16 [get_nets [list zcash_fpga_top/control_top/debug_if2/ctl]]
+connect_debug_port u_ila_0/probe19 [get_nets [list zcash_fpga_top/control_top/debug_if2/eop]]
+connect_debug_port u_ila_0/probe21 [get_nets [list zcash_fpga_top/control_top/debug_if2/err]]
+connect_debug_port u_ila_0/probe26 [get_nets [list zcash_fpga_top/control_top/debug_if2/mod]]
+connect_debug_port u_ila_0/probe27 [get_nets [list zcash_fpga_top/control_top/debug_if2/rdy]]
+connect_debug_port u_ila_0/probe30 [get_nets [list zcash_fpga_top/control_top/debug_if2/sop]]
+connect_debug_port u_ila_0/probe34 [get_nets [list uart_wrapper/uart_axi_arvalid]]
+connect_debug_port u_ila_0/probe36 [get_nets [list uart_wrapper/uart_axi_awvalid]]
+connect_debug_port u_ila_0/probe38 [get_nets [list uart_wrapper/uart_axi_wready]]
+connect_debug_port u_ila_0/probe40 [get_nets [list zcash_fpga_top/control_top/debug_if2/val]]
+connect_debug_port u_ila_1/probe0 [get_nets [list {zcash_fpga_top/control_top/debug_if0/mod[0]} {zcash_fpga_top/control_top/debug_if0/mod[1]} {zcash_fpga_top/control_top/debug_if0/mod[2]}]]
+connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/control_top/debug_if1/dat[0]} {zcash_fpga_top/control_top/debug_if1/dat[1]} {zcash_fpga_top/control_top/debug_if1/dat[2]} {zcash_fpga_top/control_top/debug_if1/dat[3]} {zcash_fpga_top/control_top/debug_if1/dat[4]} {zcash_fpga_top/control_top/debug_if1/dat[5]} {zcash_fpga_top/control_top/debug_if1/dat[6]} {zcash_fpga_top/control_top/debug_if1/dat[7]} {zcash_fpga_top/control_top/debug_if1/dat[8]} {zcash_fpga_top/control_top/debug_if1/dat[9]} {zcash_fpga_top/control_top/debug_if1/dat[10]} {zcash_fpga_top/control_top/debug_if1/dat[11]} {zcash_fpga_top/control_top/debug_if1/dat[12]} {zcash_fpga_top/control_top/debug_if1/dat[13]} {zcash_fpga_top/control_top/debug_if1/dat[14]} {zcash_fpga_top/control_top/debug_if1/dat[15]} {zcash_fpga_top/control_top/debug_if1/dat[16]} {zcash_fpga_top/control_top/debug_if1/dat[17]} {zcash_fpga_top/control_top/debug_if1/dat[18]} {zcash_fpga_top/control_top/debug_if1/dat[19]} {zcash_fpga_top/control_top/debug_if1/dat[20]} {zcash_fpga_top/control_top/debug_if1/dat[21]} {zcash_fpga_top/control_top/debug_if1/dat[22]} {zcash_fpga_top/control_top/debug_if1/dat[23]} {zcash_fpga_top/control_top/debug_if1/dat[24]} {zcash_fpga_top/control_top/debug_if1/dat[25]} {zcash_fpga_top/control_top/debug_if1/dat[26]} {zcash_fpga_top/control_top/debug_if1/dat[27]} {zcash_fpga_top/control_top/debug_if1/dat[28]} {zcash_fpga_top/control_top/debug_if1/dat[29]} {zcash_fpga_top/control_top/debug_if1/dat[30]} {zcash_fpga_top/control_top/debug_if1/dat[31]} {zcash_fpga_top/control_top/debug_if1/dat[32]} {zcash_fpga_top/control_top/debug_if1/dat[33]} {zcash_fpga_top/control_top/debug_if1/dat[34]} {zcash_fpga_top/control_top/debug_if1/dat[35]} {zcash_fpga_top/control_top/debug_if1/dat[36]} {zcash_fpga_top/control_top/debug_if1/dat[37]} {zcash_fpga_top/control_top/debug_if1/dat[38]} {zcash_fpga_top/control_top/debug_if1/dat[39]} {zcash_fpga_top/control_top/debug_if1/dat[40]} {zcash_fpga_top/control_top/debug_if1/dat[41]} {zcash_fpga_top/control_top/debug_if1/dat[42]} {zcash_fpga_top/control_top/debug_if1/dat[43]} {zcash_fpga_top/control_top/debug_if1/dat[44]} {zcash_fpga_top/control_top/debug_if1/dat[45]} {zcash_fpga_top/control_top/debug_if1/dat[46]} {zcash_fpga_top/control_top/debug_if1/dat[47]} {zcash_fpga_top/control_top/debug_if1/dat[48]} {zcash_fpga_top/control_top/debug_if1/dat[49]} {zcash_fpga_top/control_top/debug_if1/dat[50]} {zcash_fpga_top/control_top/debug_if1/dat[51]} {zcash_fpga_top/control_top/debug_if1/dat[52]} {zcash_fpga_top/control_top/debug_if1/dat[53]} {zcash_fpga_top/control_top/debug_if1/dat[54]} {zcash_fpga_top/control_top/debug_if1/dat[55]} {zcash_fpga_top/control_top/debug_if1/dat[56]} {zcash_fpga_top/control_top/debug_if1/dat[57]} {zcash_fpga_top/control_top/debug_if1/dat[58]} {zcash_fpga_top/control_top/debug_if1/dat[59]} {zcash_fpga_top/control_top/debug_if1/dat[60]} {zcash_fpga_top/control_top/debug_if1/dat[61]} {zcash_fpga_top/control_top/debug_if1/dat[62]} {zcash_fpga_top/control_top/debug_if1/dat[63]}]]
+connect_debug_port u_ila_1/probe2 [get_nets [list {zcash_fpga_top/control_top/debug_if1/mod[0]} {zcash_fpga_top/control_top/debug_if1/mod[1]} {zcash_fpga_top/control_top/debug_if1/mod[2]}]]
+connect_debug_port u_ila_1/probe3 [get_nets [list {zcash_fpga_top/control_top/debug_if0/dat[0]} {zcash_fpga_top/control_top/debug_if0/dat[1]} {zcash_fpga_top/control_top/debug_if0/dat[2]} {zcash_fpga_top/control_top/debug_if0/dat[3]} {zcash_fpga_top/control_top/debug_if0/dat[4]} {zcash_fpga_top/control_top/debug_if0/dat[5]} {zcash_fpga_top/control_top/debug_if0/dat[6]} {zcash_fpga_top/control_top/debug_if0/dat[7]} {zcash_fpga_top/control_top/debug_if0/dat[8]} {zcash_fpga_top/control_top/debug_if0/dat[9]} {zcash_fpga_top/control_top/debug_if0/dat[10]} {zcash_fpga_top/control_top/debug_if0/dat[11]} {zcash_fpga_top/control_top/debug_if0/dat[12]} {zcash_fpga_top/control_top/debug_if0/dat[13]} {zcash_fpga_top/control_top/debug_if0/dat[14]} {zcash_fpga_top/control_top/debug_if0/dat[15]} {zcash_fpga_top/control_top/debug_if0/dat[16]} {zcash_fpga_top/control_top/debug_if0/dat[17]} {zcash_fpga_top/control_top/debug_if0/dat[18]} {zcash_fpga_top/control_top/debug_if0/dat[19]} {zcash_fpga_top/control_top/debug_if0/dat[20]} {zcash_fpga_top/control_top/debug_if0/dat[21]} {zcash_fpga_top/control_top/debug_if0/dat[22]} {zcash_fpga_top/control_top/debug_if0/dat[23]} {zcash_fpga_top/control_top/debug_if0/dat[24]} {zcash_fpga_top/control_top/debug_if0/dat[25]} {zcash_fpga_top/control_top/debug_if0/dat[26]} {zcash_fpga_top/control_top/debug_if0/dat[27]} {zcash_fpga_top/control_top/debug_if0/dat[28]} {zcash_fpga_top/control_top/debug_if0/dat[29]} {zcash_fpga_top/control_top/debug_if0/dat[30]} {zcash_fpga_top/control_top/debug_if0/dat[31]} {zcash_fpga_top/control_top/debug_if0/dat[32]} {zcash_fpga_top/control_top/debug_if0/dat[33]} {zcash_fpga_top/control_top/debug_if0/dat[34]} {zcash_fpga_top/control_top/debug_if0/dat[35]} {zcash_fpga_top/control_top/debug_if0/dat[36]} {zcash_fpga_top/control_top/debug_if0/dat[37]} {zcash_fpga_top/control_top/debug_if0/dat[38]} {zcash_fpga_top/control_top/debug_if0/dat[39]} {zcash_fpga_top/control_top/debug_if0/dat[40]} {zcash_fpga_top/control_top/debug_if0/dat[41]} {zcash_fpga_top/control_top/debug_if0/dat[42]} {zcash_fpga_top/control_top/debug_if0/dat[43]} {zcash_fpga_top/control_top/debug_if0/dat[44]} {zcash_fpga_top/control_top/debug_if0/dat[45]} {zcash_fpga_top/control_top/debug_if0/dat[46]} {zcash_fpga_top/control_top/debug_if0/dat[47]} {zcash_fpga_top/control_top/debug_if0/dat[48]} {zcash_fpga_top/control_top/debug_if0/dat[49]} {zcash_fpga_top/control_top/debug_if0/dat[50]} {zcash_fpga_top/control_top/debug_if0/dat[51]} {zcash_fpga_top/control_top/debug_if0/dat[52]} {zcash_fpga_top/control_top/debug_if0/dat[53]} {zcash_fpga_top/control_top/debug_if0/dat[54]} {zcash_fpga_top/control_top/debug_if0/dat[55]} {zcash_fpga_top/control_top/debug_if0/dat[56]} {zcash_fpga_top/control_top/debug_if0/dat[57]} {zcash_fpga_top/control_top/debug_if0/dat[58]} {zcash_fpga_top/control_top/debug_if0/dat[59]} {zcash_fpga_top/control_top/debug_if0/dat[60]} {zcash_fpga_top/control_top/debug_if0/dat[61]} {zcash_fpga_top/control_top/debug_if0/dat[62]} {zcash_fpga_top/control_top/debug_if0/dat[63]}]]
+connect_debug_port u_ila_1/probe4 [get_nets [list zcash_fpga_top/control_top/debug_if0/ctl]]
+connect_debug_port u_ila_1/probe5 [get_nets [list zcash_fpga_top/control_top/debug_if1/ctl]]
+connect_debug_port u_ila_1/probe6 [get_nets [list zcash_fpga_top/control_top/debug_if1/eop]]
+connect_debug_port u_ila_1/probe7 [get_nets [list zcash_fpga_top/control_top/debug_if0/eop]]
+connect_debug_port u_ila_1/probe8 [get_nets [list zcash_fpga_top/control_top/debug_if0/err]]
+connect_debug_port u_ila_1/probe9 [get_nets [list zcash_fpga_top/control_top/debug_if1/err]]
+connect_debug_port u_ila_1/probe10 [get_nets [list zcash_fpga_top/control_top/debug_if0/rdy]]
+connect_debug_port u_ila_1/probe11 [get_nets [list zcash_fpga_top/control_top/debug_if1/rdy]]
+connect_debug_port u_ila_1/probe12 [get_nets [list zcash_fpga_top/control_top/debug_if1/sop]]
+connect_debug_port u_ila_1/probe13 [get_nets [list zcash_fpga_top/control_top/debug_if0/sop]]
+connect_debug_port u_ila_1/probe14 [get_nets [list zcash_fpga_top/control_top/debug_if0/val]]
+connect_debug_port u_ila_1/probe15 [get_nets [list zcash_fpga_top/control_top/debug_if1/val]]
+
+
+
+
+#Timing paths for CDC
+set_bus_skew -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] 2.500
+set_max_delay -datapath_only -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_wr_ptr/* }]] 2.500
+set_bus_skew -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] 1.667
+set_max_delay -datapath_only -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_rx/cdc_fifo/synchronizer_rd_ptr/* }]] 1.667
+set_bus_skew -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/synchronizer_wr_ptr/* }]] 1.667
+set_max_delay -datapath_only -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/synchronizer_wr_ptr/* }]] 1.667
+set_bus_skew -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/synchronizer_rd_ptr/* }]] 2.500
+set_max_delay -datapath_only -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/control_top/cdc_fifo_tx/cdc_fifo/synchronizer_rd_ptr/* }]] 2.500
+set_bus_skew -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_in/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_in/synchronizer_wr_ptr/* }]] 1.667
+set_max_delay -datapath_only -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_in/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_in/synchronizer_wr_ptr/* }]] 1.667
+set_bus_skew -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_in/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_in/synchronizer_rd_ptr/* }]] 2.500
+set_max_delay -datapath_only -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_in/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_in/synchronizer_rd_ptr/* }]] 2.500
+set_bus_skew -from [get_pins -filter { NAME =~  "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_in/* }]] -to [get_pins -filter { NAME =~  "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_in/* }]] 2.500
+set_max_delay -datapath_only -from [get_pins -filter { NAME =~  "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_in/* }]] -to [get_pins -filter { NAME =~  "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_in/* }]] 2.500
+set_bus_skew -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/synchronizer_wr_ptr/* }]] 2.500
+set_max_delay -datapath_only -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/synchronizer_wr_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/synchronizer_wr_ptr/* }]] 2.500
+set_bus_skew -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/synchronizer_rd_ptr/* }]] 1.667
+set_max_delay -datapath_only -from [get_pins -filter { NAME =~  "*dat_reg[0]*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/synchronizer_rd_ptr/* }]] -to [get_pins -filter { NAME =~  "*dat_reg[1]*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/synchronizer_rd_ptr/* }]] 1.667
+set_bus_skew -from [get_pins -filter { NAME =~  "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/* }]] -to [get_pins -filter { NAME =~  "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/* }]] 1.667
+set_max_delay -datapath_only -from [get_pins -filter { NAME =~  "*ram*C" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/* }]] -to [get_pins -filter { NAME =~  "*o_dat_b*D" } -of_objects [get_cells -hierarchical -filter {NAME =~ zcash_fpga_top/equihash_verif_top/dup_check_fifo_out/* }]] 1.667
+
+
 create_debug_core u_ila_0 ila
 set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
 set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
@@ -139,174 +200,98 @@ set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
 set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
 set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
 set_property port_width 1 [get_debug_ports u_ila_0/clk]
-connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_mmcm/inst/clk_300]]
+connect_debug_port u_ila_0/clk [get_nets [list clk_300]]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-set_property port_width 8 [get_debug_ports u_ila_0/probe0]
+set_property port_width 2 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {zcash_fpga_top/control_top/debug_if2/dat[0]} {zcash_fpga_top/control_top/debug_if2/dat[1]} {zcash_fpga_top/control_top/debug_if2/dat[2]} {zcash_fpga_top/control_top/debug_if2/dat[3]} {zcash_fpga_top/control_top/debug_if2/dat[4]} {zcash_fpga_top/control_top/debug_if2/dat[5]} {zcash_fpga_top/control_top/debug_if2/dat[6]} {zcash_fpga_top/control_top/debug_if2/dat[7]}]]
+connect_debug_port u_ila_0/probe0 [get_nets [list {uart_wrapper/uart_axi_rresp[0]} {uart_wrapper/uart_axi_rresp[1]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-set_property port_width 16 [get_debug_ports u_ila_0/probe1]
+set_property port_width 8 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {uart_wrapper/rx_byt_len[0]} {uart_wrapper/rx_byt_len[1]} {uart_wrapper/rx_byt_len[2]} {uart_wrapper/rx_byt_len[3]} {uart_wrapper/rx_byt_len[4]} {uart_wrapper/rx_byt_len[5]} {uart_wrapper/rx_byt_len[6]} {uart_wrapper/rx_byt_len[7]} {uart_wrapper/rx_byt_len[8]} {uart_wrapper/rx_byt_len[9]} {uart_wrapper/rx_byt_len[10]} {uart_wrapper/rx_byt_len[11]} {uart_wrapper/rx_byt_len[12]} {uart_wrapper/rx_byt_len[13]} {uart_wrapper/rx_byt_len[14]} {uart_wrapper/rx_byt_len[15]}]]
+connect_debug_port u_ila_0/probe1 [get_nets [list {uart_wrapper/rxuart_debug_if/dat[0]} {uart_wrapper/rxuart_debug_if/dat[1]} {uart_wrapper/rxuart_debug_if/dat[2]} {uart_wrapper/rxuart_debug_if/dat[3]} {uart_wrapper/rxuart_debug_if/dat[4]} {uart_wrapper/rxuart_debug_if/dat[5]} {uart_wrapper/rxuart_debug_if/dat[6]} {uart_wrapper/rxuart_debug_if/dat[7]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-set_property port_width 16 [get_debug_ports u_ila_0/probe2]
+set_property port_width 8 [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {uart_wrapper/rx_byt_cnt[0]} {uart_wrapper/rx_byt_cnt[1]} {uart_wrapper/rx_byt_cnt[2]} {uart_wrapper/rx_byt_cnt[3]} {uart_wrapper/rx_byt_cnt[4]} {uart_wrapper/rx_byt_cnt[5]} {uart_wrapper/rx_byt_cnt[6]} {uart_wrapper/rx_byt_cnt[7]} {uart_wrapper/rx_byt_cnt[8]} {uart_wrapper/rx_byt_cnt[9]} {uart_wrapper/rx_byt_cnt[10]} {uart_wrapper/rx_byt_cnt[11]} {uart_wrapper/rx_byt_cnt[12]} {uart_wrapper/rx_byt_cnt[13]} {uart_wrapper/rx_byt_cnt[14]} {uart_wrapper/rx_byt_cnt[15]}]]
+connect_debug_port u_ila_0/probe2 [get_nets [list {uart_wrapper/txuart_debug_if/dat[0]} {uart_wrapper/txuart_debug_if/dat[1]} {uart_wrapper/txuart_debug_if/dat[2]} {uart_wrapper/txuart_debug_if/dat[3]} {uart_wrapper/txuart_debug_if/dat[4]} {uart_wrapper/txuart_debug_if/dat[5]} {uart_wrapper/txuart_debug_if/dat[6]} {uart_wrapper/txuart_debug_if/dat[7]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-set_property port_width 16 [get_debug_ports u_ila_0/probe3]
+set_property port_width 2 [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {uart_wrapper/tx_byt_cnt[0]} {uart_wrapper/tx_byt_cnt[1]} {uart_wrapper/tx_byt_cnt[2]} {uart_wrapper/tx_byt_cnt[3]} {uart_wrapper/tx_byt_cnt[4]} {uart_wrapper/tx_byt_cnt[5]} {uart_wrapper/tx_byt_cnt[6]} {uart_wrapper/tx_byt_cnt[7]} {uart_wrapper/tx_byt_cnt[8]} {uart_wrapper/tx_byt_cnt[9]} {uart_wrapper/tx_byt_cnt[10]} {uart_wrapper/tx_byt_cnt[11]} {uart_wrapper/tx_byt_cnt[12]} {uart_wrapper/tx_byt_cnt[13]} {uart_wrapper/tx_byt_cnt[14]} {uart_wrapper/tx_byt_cnt[15]}]]
+connect_debug_port u_ila_0/probe3 [get_nets [list {uart_wrapper/uart_axi_awaddr[2]} {uart_wrapper/uart_axi_awaddr[3]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-set_property port_width 4 [get_debug_ports u_ila_0/probe4]
+set_property port_width 8 [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {uart_wrapper/uart_axi_araddr[0]} {uart_wrapper/uart_axi_araddr[1]} {uart_wrapper/uart_axi_araddr[2]} {uart_wrapper/uart_axi_araddr[3]}]]
+connect_debug_port u_ila_0/probe4 [get_nets [list {uart_wrapper/tx_byt_len[8]} {uart_wrapper/tx_byt_len[9]} {uart_wrapper/tx_byt_len[10]} {uart_wrapper/tx_byt_len[11]} {uart_wrapper/tx_byt_len[12]} {uart_wrapper/tx_byt_len[13]} {uart_wrapper/tx_byt_len[14]} {uart_wrapper/tx_byt_len[15]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-set_property port_width 4 [get_debug_ports u_ila_0/probe5]
+set_property port_width 32 [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {uart_wrapper/uart_axi_awaddr[0]} {uart_wrapper/uart_axi_awaddr[1]} {uart_wrapper/uart_axi_awaddr[2]} {uart_wrapper/uart_axi_awaddr[3]}]]
+connect_debug_port u_ila_0/probe5 [get_nets [list {uart_wrapper/uart_axi_rdata[0]} {uart_wrapper/uart_axi_rdata[1]} {uart_wrapper/uart_axi_rdata[2]} {uart_wrapper/uart_axi_rdata[3]} {uart_wrapper/uart_axi_rdata[4]} {uart_wrapper/uart_axi_rdata[5]} {uart_wrapper/uart_axi_rdata[6]} {uart_wrapper/uart_axi_rdata[7]} {uart_wrapper/uart_axi_rdata[8]} {uart_wrapper/uart_axi_rdata[9]} {uart_wrapper/uart_axi_rdata[10]} {uart_wrapper/uart_axi_rdata[11]} {uart_wrapper/uart_axi_rdata[12]} {uart_wrapper/uart_axi_rdata[13]} {uart_wrapper/uart_axi_rdata[14]} {uart_wrapper/uart_axi_rdata[15]} {uart_wrapper/uart_axi_rdata[16]} {uart_wrapper/uart_axi_rdata[17]} {uart_wrapper/uart_axi_rdata[18]} {uart_wrapper/uart_axi_rdata[19]} {uart_wrapper/uart_axi_rdata[20]} {uart_wrapper/uart_axi_rdata[21]} {uart_wrapper/uart_axi_rdata[22]} {uart_wrapper/uart_axi_rdata[23]} {uart_wrapper/uart_axi_rdata[24]} {uart_wrapper/uart_axi_rdata[25]} {uart_wrapper/uart_axi_rdata[26]} {uart_wrapper/uart_axi_rdata[27]} {uart_wrapper/uart_axi_rdata[28]} {uart_wrapper/uart_axi_rdata[29]} {uart_wrapper/uart_axi_rdata[30]} {uart_wrapper/uart_axi_rdata[31]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
 set_property port_width 1 [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {uart_wrapper/uart_axi_bresp[1]}]]
+connect_debug_port u_ila_0/probe6 [get_nets [list uart_wrapper/txuart_debug_if/ctl]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-set_property port_width 8 [get_debug_ports u_ila_0/probe7]
+set_property port_width 1 [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {uart_wrapper/txuart_debug_if/dat[0]} {uart_wrapper/txuart_debug_if/dat[1]} {uart_wrapper/txuart_debug_if/dat[2]} {uart_wrapper/txuart_debug_if/dat[3]} {uart_wrapper/txuart_debug_if/dat[4]} {uart_wrapper/txuart_debug_if/dat[5]} {uart_wrapper/txuart_debug_if/dat[6]} {uart_wrapper/txuart_debug_if/dat[7]}]]
+connect_debug_port u_ila_0/probe7 [get_nets [list uart_wrapper/rxuart_debug_if/ctl]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-set_property port_width 16 [get_debug_ports u_ila_0/probe8]
+set_property port_width 1 [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {uart_wrapper/tx_byt_len[0]} {uart_wrapper/tx_byt_len[1]} {uart_wrapper/tx_byt_len[2]} {uart_wrapper/tx_byt_len[3]} {uart_wrapper/tx_byt_len[4]} {uart_wrapper/tx_byt_len[5]} {uart_wrapper/tx_byt_len[6]} {uart_wrapper/tx_byt_len[7]} {uart_wrapper/tx_byt_len[8]} {uart_wrapper/tx_byt_len[9]} {uart_wrapper/tx_byt_len[10]} {uart_wrapper/tx_byt_len[11]} {uart_wrapper/tx_byt_len[12]} {uart_wrapper/tx_byt_len[13]} {uart_wrapper/tx_byt_len[14]} {uart_wrapper/tx_byt_len[15]}]]
+connect_debug_port u_ila_0/probe8 [get_nets [list uart_wrapper/txuart_debug_if/eop]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-set_property port_width 32 [get_debug_ports u_ila_0/probe9]
+set_property port_width 1 [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {uart_wrapper/uart_axi_rdata[0]} {uart_wrapper/uart_axi_rdata[1]} {uart_wrapper/uart_axi_rdata[2]} {uart_wrapper/uart_axi_rdata[3]} {uart_wrapper/uart_axi_rdata[4]} {uart_wrapper/uart_axi_rdata[5]} {uart_wrapper/uart_axi_rdata[6]} {uart_wrapper/uart_axi_rdata[7]} {uart_wrapper/uart_axi_rdata[8]} {uart_wrapper/uart_axi_rdata[9]} {uart_wrapper/uart_axi_rdata[10]} {uart_wrapper/uart_axi_rdata[11]} {uart_wrapper/uart_axi_rdata[12]} {uart_wrapper/uart_axi_rdata[13]} {uart_wrapper/uart_axi_rdata[14]} {uart_wrapper/uart_axi_rdata[15]} {uart_wrapper/uart_axi_rdata[16]} {uart_wrapper/uart_axi_rdata[17]} {uart_wrapper/uart_axi_rdata[18]} {uart_wrapper/uart_axi_rdata[19]} {uart_wrapper/uart_axi_rdata[20]} {uart_wrapper/uart_axi_rdata[21]} {uart_wrapper/uart_axi_rdata[22]} {uart_wrapper/uart_axi_rdata[23]} {uart_wrapper/uart_axi_rdata[24]} {uart_wrapper/uart_axi_rdata[25]} {uart_wrapper/uart_axi_rdata[26]} {uart_wrapper/uart_axi_rdata[27]} {uart_wrapper/uart_axi_rdata[28]} {uart_wrapper/uart_axi_rdata[29]} {uart_wrapper/uart_axi_rdata[30]} {uart_wrapper/uart_axi_rdata[31]}]]
+connect_debug_port u_ila_0/probe9 [get_nets [list uart_wrapper/rxuart_debug_if/eop]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-set_property port_width 8 [get_debug_ports u_ila_0/probe10]
+set_property port_width 1 [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {uart_wrapper/rxuart_debug_if/dat[0]} {uart_wrapper/rxuart_debug_if/dat[1]} {uart_wrapper/rxuart_debug_if/dat[2]} {uart_wrapper/rxuart_debug_if/dat[3]} {uart_wrapper/rxuart_debug_if/dat[4]} {uart_wrapper/rxuart_debug_if/dat[5]} {uart_wrapper/rxuart_debug_if/dat[6]} {uart_wrapper/rxuart_debug_if/dat[7]}]]
+connect_debug_port u_ila_0/probe10 [get_nets [list uart_wrapper/rxuart_debug_if/err]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
-set_property port_width 2 [get_debug_ports u_ila_0/probe11]
+set_property port_width 1 [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list {uart_wrapper/uart_axi_rresp[0]} {uart_wrapper/uart_axi_rresp[1]}]]
+connect_debug_port u_ila_0/probe11 [get_nets [list uart_wrapper/txuart_debug_if/err]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-set_property port_width 32 [get_debug_ports u_ila_0/probe12]
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list {uart_wrapper/uart_axi_wdata[0]} {uart_wrapper/uart_axi_wdata[1]} {uart_wrapper/uart_axi_wdata[2]} {uart_wrapper/uart_axi_wdata[3]} {uart_wrapper/uart_axi_wdata[4]} {uart_wrapper/uart_axi_wdata[5]} {uart_wrapper/uart_axi_wdata[6]} {uart_wrapper/uart_axi_wdata[7]} {uart_wrapper/uart_axi_wdata[8]} {uart_wrapper/uart_axi_wdata[9]} {uart_wrapper/uart_axi_wdata[10]} {uart_wrapper/uart_axi_wdata[11]} {uart_wrapper/uart_axi_wdata[12]} {uart_wrapper/uart_axi_wdata[13]} {uart_wrapper/uart_axi_wdata[14]} {uart_wrapper/uart_axi_wdata[15]} {uart_wrapper/uart_axi_wdata[16]} {uart_wrapper/uart_axi_wdata[17]} {uart_wrapper/uart_axi_wdata[18]} {uart_wrapper/uart_axi_wdata[19]} {uart_wrapper/uart_axi_wdata[20]} {uart_wrapper/uart_axi_wdata[21]} {uart_wrapper/uart_axi_wdata[22]} {uart_wrapper/uart_axi_wdata[23]} {uart_wrapper/uart_axi_wdata[24]} {uart_wrapper/uart_axi_wdata[25]} {uart_wrapper/uart_axi_wdata[26]} {uart_wrapper/uart_axi_wdata[27]} {uart_wrapper/uart_axi_wdata[28]} {uart_wrapper/uart_axi_wdata[29]} {uart_wrapper/uart_axi_wdata[30]} {uart_wrapper/uart_axi_wdata[31]}]]
+connect_debug_port u_ila_0/probe12 [get_nets [list uart_wrapper/txuart_debug_if/mod]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-set_property port_width 32 [get_debug_ports u_ila_0/probe13]
+set_property port_width 1 [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {uart_wrapper/uart_state[0]} {uart_wrapper/uart_state[1]} {uart_wrapper/uart_state[2]} {uart_wrapper/uart_state[3]} {uart_wrapper/uart_state[4]} {uart_wrapper/uart_state[5]} {uart_wrapper/uart_state[6]} {uart_wrapper/uart_state[7]} {uart_wrapper/uart_state[8]} {uart_wrapper/uart_state[9]} {uart_wrapper/uart_state[10]} {uart_wrapper/uart_state[11]} {uart_wrapper/uart_state[12]} {uart_wrapper/uart_state[13]} {uart_wrapper/uart_state[14]} {uart_wrapper/uart_state[15]} {uart_wrapper/uart_state[16]} {uart_wrapper/uart_state[17]} {uart_wrapper/uart_state[18]} {uart_wrapper/uart_state[19]} {uart_wrapper/uart_state[20]} {uart_wrapper/uart_state[21]} {uart_wrapper/uart_state[22]} {uart_wrapper/uart_state[23]} {uart_wrapper/uart_state[24]} {uart_wrapper/uart_state[25]} {uart_wrapper/uart_state[26]} {uart_wrapper/uart_state[27]} {uart_wrapper/uart_state[28]} {uart_wrapper/uart_state[29]} {uart_wrapper/uart_state[30]} {uart_wrapper/uart_state[31]}]]
+connect_debug_port u_ila_0/probe13 [get_nets [list uart_wrapper/rxuart_debug_if/mod]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
 set_property port_width 1 [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list uart_wrapper/rxuart_debug_if/ctl]]
+connect_debug_port u_ila_0/probe14 [get_nets [list uart_wrapper/txuart_debug_if/rdy]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
 set_property port_width 1 [get_debug_ports u_ila_0/probe15]
-connect_debug_port u_ila_0/probe15 [get_nets [list uart_wrapper/txuart_debug_if/ctl]]
+connect_debug_port u_ila_0/probe15 [get_nets [list uart_wrapper/rxuart_debug_if/rdy]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
 set_property port_width 1 [get_debug_ports u_ila_0/probe16]
-connect_debug_port u_ila_0/probe16 [get_nets [list zcash_fpga_top/control_top/debug_if2/ctl]]
+connect_debug_port u_ila_0/probe16 [get_nets [list uart_wrapper/rxuart_debug_if/sop]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
 set_property port_width 1 [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list uart_wrapper/rxuart_debug_if/eop]]
+connect_debug_port u_ila_0/probe17 [get_nets [list uart_wrapper/txuart_debug_if/sop]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
 set_property port_width 1 [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list uart_wrapper/txuart_debug_if/eop]]
+connect_debug_port u_ila_0/probe18 [get_nets [list uart_wrapper/uart_axi_arready]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
 set_property port_width 1 [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list zcash_fpga_top/control_top/debug_if2/eop]]
+connect_debug_port u_ila_0/probe19 [get_nets [list uart_wrapper/uart_axi_awready]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
 set_property port_width 1 [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list uart_wrapper/txuart_debug_if/err]]
+connect_debug_port u_ila_0/probe20 [get_nets [list uart_wrapper/uart_axi_rvalid]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
 set_property port_width 1 [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list zcash_fpga_top/control_top/debug_if2/err]]
+connect_debug_port u_ila_0/probe21 [get_nets [list uart_wrapper/rxuart_debug_if/val]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
 set_property port_width 1 [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list uart_wrapper/rxuart_debug_if/err]]
+connect_debug_port u_ila_0/probe22 [get_nets [list uart_wrapper/txuart_debug_if/val]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
-set_property port_width 1 [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list uart_wrapper/interrupt]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
-set_property port_width 1 [get_debug_ports u_ila_0/probe24]
-connect_debug_port u_ila_0/probe24 [get_nets [list uart_wrapper/txuart_debug_if/mod]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
-set_property port_width 1 [get_debug_ports u_ila_0/probe25]
-connect_debug_port u_ila_0/probe25 [get_nets [list uart_wrapper/rxuart_debug_if/mod]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
-set_property port_width 1 [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list zcash_fpga_top/control_top/debug_if2/mod]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
-set_property port_width 1 [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list zcash_fpga_top/control_top/debug_if2/rdy]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
-set_property port_width 1 [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list uart_wrapper/rxuart_debug_if/rdy]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
-set_property port_width 1 [get_debug_ports u_ila_0/probe29]
-connect_debug_port u_ila_0/probe29 [get_nets [list uart_wrapper/txuart_debug_if/rdy]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
-set_property port_width 1 [get_debug_ports u_ila_0/probe30]
-connect_debug_port u_ila_0/probe30 [get_nets [list zcash_fpga_top/control_top/debug_if2/sop]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-set_property port_width 1 [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list uart_wrapper/txuart_debug_if/sop]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
-set_property port_width 1 [get_debug_ports u_ila_0/probe32]
-connect_debug_port u_ila_0/probe32 [get_nets [list uart_wrapper/rxuart_debug_if/sop]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
-set_property port_width 1 [get_debug_ports u_ila_0/probe33]
-connect_debug_port u_ila_0/probe33 [get_nets [list uart_wrapper/uart_axi_arready]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
-set_property port_width 1 [get_debug_ports u_ila_0/probe34]
-connect_debug_port u_ila_0/probe34 [get_nets [list uart_wrapper/uart_axi_arvalid]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
-set_property port_width 1 [get_debug_ports u_ila_0/probe35]
-connect_debug_port u_ila_0/probe35 [get_nets [list uart_wrapper/uart_axi_awready]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
-set_property port_width 1 [get_debug_ports u_ila_0/probe36]
-connect_debug_port u_ila_0/probe36 [get_nets [list uart_wrapper/uart_axi_awvalid]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
-set_property port_width 1 [get_debug_ports u_ila_0/probe37]
-connect_debug_port u_ila_0/probe37 [get_nets [list uart_wrapper/uart_axi_rvalid]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
-set_property port_width 1 [get_debug_ports u_ila_0/probe38]
-connect_debug_port u_ila_0/probe38 [get_nets [list uart_wrapper/uart_axi_wready]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
-set_property port_width 1 [get_debug_ports u_ila_0/probe39]
-connect_debug_port u_ila_0/probe39 [get_nets [list uart_wrapper/txuart_debug_if/val]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
-set_property port_width 1 [get_debug_ports u_ila_0/probe40]
-connect_debug_port u_ila_0/probe40 [get_nets [list zcash_fpga_top/control_top/debug_if2/val]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
-set_property port_width 1 [get_debug_ports u_ila_0/probe41]
-connect_debug_port u_ila_0/probe41 [get_nets [list uart_wrapper/rxuart_debug_if/val]]
 create_debug_core u_ila_1 ila
 set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
 set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
@@ -320,67 +305,137 @@ set_property port_width 1 [get_debug_ports u_ila_1/clk]
 connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_mmcm/inst/clk_200]]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
 set_property port_width 3 [get_debug_ports u_ila_1/probe0]
-connect_debug_port u_ila_1/probe0 [get_nets [list {zcash_fpga_top/control_top/debug_if0/mod[0]} {zcash_fpga_top/control_top/debug_if0/mod[1]} {zcash_fpga_top/control_top/debug_if0/mod[2]}]]
+connect_debug_port u_ila_1/probe0 [get_nets [list {zcash_fpga_top/secp256k1_top/debug_if_rx/mod[0]} {zcash_fpga_top/secp256k1_top/debug_if_rx/mod[1]} {zcash_fpga_top/secp256k1_top/debug_if_rx/mod[2]}]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
 set_property port_width 64 [get_debug_ports u_ila_1/probe1]
-connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/control_top/debug_if1/dat[0]} {zcash_fpga_top/control_top/debug_if1/dat[1]} {zcash_fpga_top/control_top/debug_if1/dat[2]} {zcash_fpga_top/control_top/debug_if1/dat[3]} {zcash_fpga_top/control_top/debug_if1/dat[4]} {zcash_fpga_top/control_top/debug_if1/dat[5]} {zcash_fpga_top/control_top/debug_if1/dat[6]} {zcash_fpga_top/control_top/debug_if1/dat[7]} {zcash_fpga_top/control_top/debug_if1/dat[8]} {zcash_fpga_top/control_top/debug_if1/dat[9]} {zcash_fpga_top/control_top/debug_if1/dat[10]} {zcash_fpga_top/control_top/debug_if1/dat[11]} {zcash_fpga_top/control_top/debug_if1/dat[12]} {zcash_fpga_top/control_top/debug_if1/dat[13]} {zcash_fpga_top/control_top/debug_if1/dat[14]} {zcash_fpga_top/control_top/debug_if1/dat[15]} {zcash_fpga_top/control_top/debug_if1/dat[16]} {zcash_fpga_top/control_top/debug_if1/dat[17]} {zcash_fpga_top/control_top/debug_if1/dat[18]} {zcash_fpga_top/control_top/debug_if1/dat[19]} {zcash_fpga_top/control_top/debug_if1/dat[20]} {zcash_fpga_top/control_top/debug_if1/dat[21]} {zcash_fpga_top/control_top/debug_if1/dat[22]} {zcash_fpga_top/control_top/debug_if1/dat[23]} {zcash_fpga_top/control_top/debug_if1/dat[24]} {zcash_fpga_top/control_top/debug_if1/dat[25]} {zcash_fpga_top/control_top/debug_if1/dat[26]} {zcash_fpga_top/control_top/debug_if1/dat[27]} {zcash_fpga_top/control_top/debug_if1/dat[28]} {zcash_fpga_top/control_top/debug_if1/dat[29]} {zcash_fpga_top/control_top/debug_if1/dat[30]} {zcash_fpga_top/control_top/debug_if1/dat[31]} {zcash_fpga_top/control_top/debug_if1/dat[32]} {zcash_fpga_top/control_top/debug_if1/dat[33]} {zcash_fpga_top/control_top/debug_if1/dat[34]} {zcash_fpga_top/control_top/debug_if1/dat[35]} {zcash_fpga_top/control_top/debug_if1/dat[36]} {zcash_fpga_top/control_top/debug_if1/dat[37]} {zcash_fpga_top/control_top/debug_if1/dat[38]} {zcash_fpga_top/control_top/debug_if1/dat[39]} {zcash_fpga_top/control_top/debug_if1/dat[40]} {zcash_fpga_top/control_top/debug_if1/dat[41]} {zcash_fpga_top/control_top/debug_if1/dat[42]} {zcash_fpga_top/control_top/debug_if1/dat[43]} {zcash_fpga_top/control_top/debug_if1/dat[44]} {zcash_fpga_top/control_top/debug_if1/dat[45]} {zcash_fpga_top/control_top/debug_if1/dat[46]} {zcash_fpga_top/control_top/debug_if1/dat[47]} {zcash_fpga_top/control_top/debug_if1/dat[48]} {zcash_fpga_top/control_top/debug_if1/dat[49]} {zcash_fpga_top/control_top/debug_if1/dat[50]} {zcash_fpga_top/control_top/debug_if1/dat[51]} {zcash_fpga_top/control_top/debug_if1/dat[52]} {zcash_fpga_top/control_top/debug_if1/dat[53]} {zcash_fpga_top/control_top/debug_if1/dat[54]} {zcash_fpga_top/control_top/debug_if1/dat[55]} {zcash_fpga_top/control_top/debug_if1/dat[56]} {zcash_fpga_top/control_top/debug_if1/dat[57]} {zcash_fpga_top/control_top/debug_if1/dat[58]} {zcash_fpga_top/control_top/debug_if1/dat[59]} {zcash_fpga_top/control_top/debug_if1/dat[60]} {zcash_fpga_top/control_top/debug_if1/dat[61]} {zcash_fpga_top/control_top/debug_if1/dat[62]} {zcash_fpga_top/control_top/debug_if1/dat[63]}]]
+connect_debug_port u_ila_1/probe1 [get_nets [list {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[0]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[1]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[2]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[3]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[4]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[5]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[6]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[7]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[8]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[9]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[10]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[11]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[12]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[13]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[14]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[15]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[16]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[17]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[18]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[19]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[20]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[21]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[22]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[23]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[24]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[25]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[26]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[27]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[28]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[29]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[30]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[31]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[32]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[33]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[34]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[35]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[36]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[37]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[38]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[39]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[40]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[41]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[42]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[43]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[44]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[45]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[46]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[47]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[48]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[49]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[50]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[51]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[52]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[53]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[54]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[55]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[56]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[57]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[58]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[59]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[60]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[61]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[62]} {zcash_fpga_top/secp256k1_top/debug_if_tx/dat[63]}]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
 set_property port_width 3 [get_debug_ports u_ila_1/probe2]
-connect_debug_port u_ila_1/probe2 [get_nets [list {zcash_fpga_top/control_top/debug_if1/mod[0]} {zcash_fpga_top/control_top/debug_if1/mod[1]} {zcash_fpga_top/control_top/debug_if1/mod[2]}]]
+connect_debug_port u_ila_1/probe2 [get_nets [list {zcash_fpga_top/secp256k1_top/debug_if_tx/mod[0]} {zcash_fpga_top/secp256k1_top/debug_if_tx/mod[1]} {zcash_fpga_top/secp256k1_top/debug_if_tx/mod[2]}]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
 set_property port_width 64 [get_debug_ports u_ila_1/probe3]
-connect_debug_port u_ila_1/probe3 [get_nets [list {zcash_fpga_top/control_top/debug_if0/dat[0]} {zcash_fpga_top/control_top/debug_if0/dat[1]} {zcash_fpga_top/control_top/debug_if0/dat[2]} {zcash_fpga_top/control_top/debug_if0/dat[3]} {zcash_fpga_top/control_top/debug_if0/dat[4]} {zcash_fpga_top/control_top/debug_if0/dat[5]} {zcash_fpga_top/control_top/debug_if0/dat[6]} {zcash_fpga_top/control_top/debug_if0/dat[7]} {zcash_fpga_top/control_top/debug_if0/dat[8]} {zcash_fpga_top/control_top/debug_if0/dat[9]} {zcash_fpga_top/control_top/debug_if0/dat[10]} {zcash_fpga_top/control_top/debug_if0/dat[11]} {zcash_fpga_top/control_top/debug_if0/dat[12]} {zcash_fpga_top/control_top/debug_if0/dat[13]} {zcash_fpga_top/control_top/debug_if0/dat[14]} {zcash_fpga_top/control_top/debug_if0/dat[15]} {zcash_fpga_top/control_top/debug_if0/dat[16]} {zcash_fpga_top/control_top/debug_if0/dat[17]} {zcash_fpga_top/control_top/debug_if0/dat[18]} {zcash_fpga_top/control_top/debug_if0/dat[19]} {zcash_fpga_top/control_top/debug_if0/dat[20]} {zcash_fpga_top/control_top/debug_if0/dat[21]} {zcash_fpga_top/control_top/debug_if0/dat[22]} {zcash_fpga_top/control_top/debug_if0/dat[23]} {zcash_fpga_top/control_top/debug_if0/dat[24]} {zcash_fpga_top/control_top/debug_if0/dat[25]} {zcash_fpga_top/control_top/debug_if0/dat[26]} {zcash_fpga_top/control_top/debug_if0/dat[27]} {zcash_fpga_top/control_top/debug_if0/dat[28]} {zcash_fpga_top/control_top/debug_if0/dat[29]} {zcash_fpga_top/control_top/debug_if0/dat[30]} {zcash_fpga_top/control_top/debug_if0/dat[31]} {zcash_fpga_top/control_top/debug_if0/dat[32]} {zcash_fpga_top/control_top/debug_if0/dat[33]} {zcash_fpga_top/control_top/debug_if0/dat[34]} {zcash_fpga_top/control_top/debug_if0/dat[35]} {zcash_fpga_top/control_top/debug_if0/dat[36]} {zcash_fpga_top/control_top/debug_if0/dat[37]} {zcash_fpga_top/control_top/debug_if0/dat[38]} {zcash_fpga_top/control_top/debug_if0/dat[39]} {zcash_fpga_top/control_top/debug_if0/dat[40]} {zcash_fpga_top/control_top/debug_if0/dat[41]} {zcash_fpga_top/control_top/debug_if0/dat[42]} {zcash_fpga_top/control_top/debug_if0/dat[43]} {zcash_fpga_top/control_top/debug_if0/dat[44]} {zcash_fpga_top/control_top/debug_if0/dat[45]} {zcash_fpga_top/control_top/debug_if0/dat[46]} {zcash_fpga_top/control_top/debug_if0/dat[47]} {zcash_fpga_top/control_top/debug_if0/dat[48]} {zcash_fpga_top/control_top/debug_if0/dat[49]} {zcash_fpga_top/control_top/debug_if0/dat[50]} {zcash_fpga_top/control_top/debug_if0/dat[51]} {zcash_fpga_top/control_top/debug_if0/dat[52]} {zcash_fpga_top/control_top/debug_if0/dat[53]} {zcash_fpga_top/control_top/debug_if0/dat[54]} {zcash_fpga_top/control_top/debug_if0/dat[55]} {zcash_fpga_top/control_top/debug_if0/dat[56]} {zcash_fpga_top/control_top/debug_if0/dat[57]} {zcash_fpga_top/control_top/debug_if0/dat[58]} {zcash_fpga_top/control_top/debug_if0/dat[59]} {zcash_fpga_top/control_top/debug_if0/dat[60]} {zcash_fpga_top/control_top/debug_if0/dat[61]} {zcash_fpga_top/control_top/debug_if0/dat[62]} {zcash_fpga_top/control_top/debug_if0/dat[63]}]]
+connect_debug_port u_ila_1/probe3 [get_nets [list {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[0]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[1]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[2]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[3]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[4]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[5]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[6]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[7]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[8]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[9]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[10]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[11]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[12]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[13]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[14]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[15]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[16]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[17]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[18]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[19]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[20]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[21]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[22]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[23]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[24]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[25]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[26]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[27]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[28]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[29]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[30]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[31]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[32]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[33]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[34]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[35]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[36]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[37]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[38]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[39]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[40]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[41]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[42]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[43]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[44]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[45]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[46]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[47]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[48]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[49]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[50]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[51]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[52]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[53]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[54]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[55]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[56]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[57]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[58]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[59]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[60]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[61]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[62]} {zcash_fpga_top/secp256k1_top/debug_if_rx/dat[63]}]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
-set_property port_width 1 [get_debug_ports u_ila_1/probe4]
+set_property port_width 64 [get_debug_ports u_ila_1/probe4]
-connect_debug_port u_ila_1/probe4 [get_nets [list zcash_fpga_top/control_top/debug_if0/ctl]]
+connect_debug_port u_ila_1/probe4 [get_nets [list {zcash_fpga_top/control_top/debug_if_tx/dat[0]} {zcash_fpga_top/control_top/debug_if_tx/dat[1]} {zcash_fpga_top/control_top/debug_if_tx/dat[2]} {zcash_fpga_top/control_top/debug_if_tx/dat[3]} {zcash_fpga_top/control_top/debug_if_tx/dat[4]} {zcash_fpga_top/control_top/debug_if_tx/dat[5]} {zcash_fpga_top/control_top/debug_if_tx/dat[6]} {zcash_fpga_top/control_top/debug_if_tx/dat[7]} {zcash_fpga_top/control_top/debug_if_tx/dat[8]} {zcash_fpga_top/control_top/debug_if_tx/dat[9]} {zcash_fpga_top/control_top/debug_if_tx/dat[10]} {zcash_fpga_top/control_top/debug_if_tx/dat[11]} {zcash_fpga_top/control_top/debug_if_tx/dat[12]} {zcash_fpga_top/control_top/debug_if_tx/dat[13]} {zcash_fpga_top/control_top/debug_if_tx/dat[14]} {zcash_fpga_top/control_top/debug_if_tx/dat[15]} {zcash_fpga_top/control_top/debug_if_tx/dat[16]} {zcash_fpga_top/control_top/debug_if_tx/dat[17]} {zcash_fpga_top/control_top/debug_if_tx/dat[18]} {zcash_fpga_top/control_top/debug_if_tx/dat[19]} {zcash_fpga_top/control_top/debug_if_tx/dat[20]} {zcash_fpga_top/control_top/debug_if_tx/dat[21]} {zcash_fpga_top/control_top/debug_if_tx/dat[22]} {zcash_fpga_top/control_top/debug_if_tx/dat[23]} {zcash_fpga_top/control_top/debug_if_tx/dat[24]} {zcash_fpga_top/control_top/debug_if_tx/dat[25]} {zcash_fpga_top/control_top/debug_if_tx/dat[26]} {zcash_fpga_top/control_top/debug_if_tx/dat[27]} {zcash_fpga_top/control_top/debug_if_tx/dat[28]} {zcash_fpga_top/control_top/debug_if_tx/dat[29]} {zcash_fpga_top/control_top/debug_if_tx/dat[30]} {zcash_fpga_top/control_top/debug_if_tx/dat[31]} {zcash_fpga_top/control_top/debug_if_tx/dat[32]} {zcash_fpga_top/control_top/debug_if_tx/dat[33]} {zcash_fpga_top/control_top/debug_if_tx/dat[34]} {zcash_fpga_top/control_top/debug_if_tx/dat[35]} {zcash_fpga_top/control_top/debug_if_tx/dat[36]} {zcash_fpga_top/control_top/debug_if_tx/dat[37]} {zcash_fpga_top/control_top/debug_if_tx/dat[38]} {zcash_fpga_top/control_top/debug_if_tx/dat[39]} {zcash_fpga_top/control_top/debug_if_tx/dat[40]} {zcash_fpga_top/control_top/debug_if_tx/dat[41]} {zcash_fpga_top/control_top/debug_if_tx/dat[42]} {zcash_fpga_top/control_top/debug_if_tx/dat[43]} {zcash_fpga_top/control_top/debug_if_tx/dat[44]} {zcash_fpga_top/control_top/debug_if_tx/dat[45]} {zcash_fpga_top/control_top/debug_if_tx/dat[46]} {zcash_fpga_top/control_top/debug_if_tx/dat[47]} {zcash_fpga_top/control_top/debug_if_tx/dat[48]} {zcash_fpga_top/control_top/debug_if_tx/dat[49]} {zcash_fpga_top/control_top/debug_if_tx/dat[50]} {zcash_fpga_top/control_top/debug_if_tx/dat[51]} {zcash_fpga_top/control_top/debug_if_tx/dat[52]} {zcash_fpga_top/control_top/debug_if_tx/dat[53]} {zcash_fpga_top/control_top/debug_if_tx/dat[54]} {zcash_fpga_top/control_top/debug_if_tx/dat[55]} {zcash_fpga_top/control_top/debug_if_tx/dat[56]} {zcash_fpga_top/control_top/debug_if_tx/dat[57]} {zcash_fpga_top/control_top/debug_if_tx/dat[58]} {zcash_fpga_top/control_top/debug_if_tx/dat[59]} {zcash_fpga_top/control_top/debug_if_tx/dat[60]} {zcash_fpga_top/control_top/debug_if_tx/dat[61]} {zcash_fpga_top/control_top/debug_if_tx/dat[62]} {zcash_fpga_top/control_top/debug_if_tx/dat[63]}]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
-set_property port_width 1 [get_debug_ports u_ila_1/probe5]
+set_property port_width 3 [get_debug_ports u_ila_1/probe5]
-connect_debug_port u_ila_1/probe5 [get_nets [list zcash_fpga_top/control_top/debug_if1/ctl]]
+connect_debug_port u_ila_1/probe5 [get_nets [list {zcash_fpga_top/control_top/debug_if_tx/mod[0]} {zcash_fpga_top/control_top/debug_if_tx/mod[1]} {zcash_fpga_top/control_top/debug_if_tx/mod[2]}]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
-set_property port_width 1 [get_debug_ports u_ila_1/probe6]
+set_property port_width 3 [get_debug_ports u_ila_1/probe6]
-connect_debug_port u_ila_1/probe6 [get_nets [list zcash_fpga_top/control_top/debug_if1/eop]]
+connect_debug_port u_ila_1/probe6 [get_nets [list {zcash_fpga_top/control_top/debug_if_rx/mod[0]} {zcash_fpga_top/control_top/debug_if_rx/mod[1]} {zcash_fpga_top/control_top/debug_if_rx/mod[2]}]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
-set_property port_width 1 [get_debug_ports u_ila_1/probe7]
+set_property port_width 64 [get_debug_ports u_ila_1/probe7]
-connect_debug_port u_ila_1/probe7 [get_nets [list zcash_fpga_top/control_top/debug_if0/eop]]
+connect_debug_port u_ila_1/probe7 [get_nets [list {zcash_fpga_top/control_top/debug_if_rx/dat[0]} {zcash_fpga_top/control_top/debug_if_rx/dat[1]} {zcash_fpga_top/control_top/debug_if_rx/dat[2]} {zcash_fpga_top/control_top/debug_if_rx/dat[3]} {zcash_fpga_top/control_top/debug_if_rx/dat[4]} {zcash_fpga_top/control_top/debug_if_rx/dat[5]} {zcash_fpga_top/control_top/debug_if_rx/dat[6]} {zcash_fpga_top/control_top/debug_if_rx/dat[7]} {zcash_fpga_top/control_top/debug_if_rx/dat[8]} {zcash_fpga_top/control_top/debug_if_rx/dat[9]} {zcash_fpga_top/control_top/debug_if_rx/dat[10]} {zcash_fpga_top/control_top/debug_if_rx/dat[11]} {zcash_fpga_top/control_top/debug_if_rx/dat[12]} {zcash_fpga_top/control_top/debug_if_rx/dat[13]} {zcash_fpga_top/control_top/debug_if_rx/dat[14]} {zcash_fpga_top/control_top/debug_if_rx/dat[15]} {zcash_fpga_top/control_top/debug_if_rx/dat[16]} {zcash_fpga_top/control_top/debug_if_rx/dat[17]} {zcash_fpga_top/control_top/debug_if_rx/dat[18]} {zcash_fpga_top/control_top/debug_if_rx/dat[19]} {zcash_fpga_top/control_top/debug_if_rx/dat[20]} {zcash_fpga_top/control_top/debug_if_rx/dat[21]} {zcash_fpga_top/control_top/debug_if_rx/dat[22]} {zcash_fpga_top/control_top/debug_if_rx/dat[23]} {zcash_fpga_top/control_top/debug_if_rx/dat[24]} {zcash_fpga_top/control_top/debug_if_rx/dat[25]} {zcash_fpga_top/control_top/debug_if_rx/dat[26]} {zcash_fpga_top/control_top/debug_if_rx/dat[27]} {zcash_fpga_top/control_top/debug_if_rx/dat[28]} {zcash_fpga_top/control_top/debug_if_rx/dat[29]} {zcash_fpga_top/control_top/debug_if_rx/dat[30]} {zcash_fpga_top/control_top/debug_if_rx/dat[31]} {zcash_fpga_top/control_top/debug_if_rx/dat[32]} {zcash_fpga_top/control_top/debug_if_rx/dat[33]} {zcash_fpga_top/control_top/debug_if_rx/dat[34]} {zcash_fpga_top/control_top/debug_if_rx/dat[35]} {zcash_fpga_top/control_top/debug_if_rx/dat[36]} {zcash_fpga_top/control_top/debug_if_rx/dat[37]} {zcash_fpga_top/control_top/debug_if_rx/dat[38]} {zcash_fpga_top/control_top/debug_if_rx/dat[39]} {zcash_fpga_top/control_top/debug_if_rx/dat[40]} {zcash_fpga_top/control_top/debug_if_rx/dat[41]} {zcash_fpga_top/control_top/debug_if_rx/dat[42]} {zcash_fpga_top/control_top/debug_if_rx/dat[43]} {zcash_fpga_top/control_top/debug_if_rx/dat[44]} {zcash_fpga_top/control_top/debug_if_rx/dat[45]} {zcash_fpga_top/control_top/debug_if_rx/dat[46]} {zcash_fpga_top/control_top/debug_if_rx/dat[47]} {zcash_fpga_top/control_top/debug_if_rx/dat[48]} {zcash_fpga_top/control_top/debug_if_rx/dat[49]} {zcash_fpga_top/control_top/debug_if_rx/dat[50]} {zcash_fpga_top/control_top/debug_if_rx/dat[51]} {zcash_fpga_top/control_top/debug_if_rx/dat[52]} {zcash_fpga_top/control_top/debug_if_rx/dat[53]} {zcash_fpga_top/control_top/debug_if_rx/dat[54]} {zcash_fpga_top/control_top/debug_if_rx/dat[55]} {zcash_fpga_top/control_top/debug_if_rx/dat[56]} {zcash_fpga_top/control_top/debug_if_rx/dat[57]} {zcash_fpga_top/control_top/debug_if_rx/dat[58]} {zcash_fpga_top/control_top/debug_if_rx/dat[59]} {zcash_fpga_top/control_top/debug_if_rx/dat[60]} {zcash_fpga_top/control_top/debug_if_rx/dat[61]} {zcash_fpga_top/control_top/debug_if_rx/dat[62]} {zcash_fpga_top/control_top/debug_if_rx/dat[63]}]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
-set_property port_width 1 [get_debug_ports u_ila_1/probe8]
+set_property port_width 32 [get_debug_ports u_ila_1/probe8]
-connect_debug_port u_ila_1/probe8 [get_nets [list zcash_fpga_top/control_top/debug_if0/err]]
+connect_debug_port u_ila_1/probe8 [get_nets [list {zcash_fpga_top/secp256k1_top/secp256k1_state[0]} {zcash_fpga_top/secp256k1_top/secp256k1_state[1]} {zcash_fpga_top/secp256k1_top/secp256k1_state[2]} {zcash_fpga_top/secp256k1_top/secp256k1_state[3]} {zcash_fpga_top/secp256k1_top/secp256k1_state[4]} {zcash_fpga_top/secp256k1_top/secp256k1_state[5]} {zcash_fpga_top/secp256k1_top/secp256k1_state[6]} {zcash_fpga_top/secp256k1_top/secp256k1_state[7]} {zcash_fpga_top/secp256k1_top/secp256k1_state[8]} {zcash_fpga_top/secp256k1_top/secp256k1_state[9]} {zcash_fpga_top/secp256k1_top/secp256k1_state[10]} {zcash_fpga_top/secp256k1_top/secp256k1_state[11]} {zcash_fpga_top/secp256k1_top/secp256k1_state[12]} {zcash_fpga_top/secp256k1_top/secp256k1_state[13]} {zcash_fpga_top/secp256k1_top/secp256k1_state[14]} {zcash_fpga_top/secp256k1_top/secp256k1_state[15]} {zcash_fpga_top/secp256k1_top/secp256k1_state[16]} {zcash_fpga_top/secp256k1_top/secp256k1_state[17]} {zcash_fpga_top/secp256k1_top/secp256k1_state[18]} {zcash_fpga_top/secp256k1_top/secp256k1_state[19]} {zcash_fpga_top/secp256k1_top/secp256k1_state[20]} {zcash_fpga_top/secp256k1_top/secp256k1_state[21]} {zcash_fpga_top/secp256k1_top/secp256k1_state[22]} {zcash_fpga_top/secp256k1_top/secp256k1_state[23]} {zcash_fpga_top/secp256k1_top/secp256k1_state[24]} {zcash_fpga_top/secp256k1_top/secp256k1_state[25]} {zcash_fpga_top/secp256k1_top/secp256k1_state[26]} {zcash_fpga_top/secp256k1_top/secp256k1_state[27]} {zcash_fpga_top/secp256k1_top/secp256k1_state[28]} {zcash_fpga_top/secp256k1_top/secp256k1_state[29]} {zcash_fpga_top/secp256k1_top/secp256k1_state[30]} {zcash_fpga_top/secp256k1_top/secp256k1_state[31]}]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
 set_property port_width 1 [get_debug_ports u_ila_1/probe9]
-connect_debug_port u_ila_1/probe9 [get_nets [list zcash_fpga_top/control_top/debug_if1/err]]
+connect_debug_port u_ila_1/probe9 [get_nets [list zcash_fpga_top/control_top/debug_if_rx/ctl]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
 set_property port_width 1 [get_debug_ports u_ila_1/probe10]
-connect_debug_port u_ila_1/probe10 [get_nets [list zcash_fpga_top/control_top/debug_if0/rdy]]
+connect_debug_port u_ila_1/probe10 [get_nets [list zcash_fpga_top/control_top/debug_if_tx/ctl]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
 set_property port_width 1 [get_debug_ports u_ila_1/probe11]
-connect_debug_port u_ila_1/probe11 [get_nets [list zcash_fpga_top/control_top/debug_if1/rdy]]
+connect_debug_port u_ila_1/probe11 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/ctl]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12]
 set_property port_width 1 [get_debug_ports u_ila_1/probe12]
-connect_debug_port u_ila_1/probe12 [get_nets [list zcash_fpga_top/control_top/debug_if1/sop]]
+connect_debug_port u_ila_1/probe12 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/ctl]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13]
 set_property port_width 1 [get_debug_ports u_ila_1/probe13]
-connect_debug_port u_ila_1/probe13 [get_nets [list zcash_fpga_top/control_top/debug_if0/sop]]
+connect_debug_port u_ila_1/probe13 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/eop]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe14]
 set_property port_width 1 [get_debug_ports u_ila_1/probe14]
-connect_debug_port u_ila_1/probe14 [get_nets [list zcash_fpga_top/control_top/debug_if0/val]]
+connect_debug_port u_ila_1/probe14 [get_nets [list zcash_fpga_top/control_top/debug_if_tx/eop]]
 create_debug_port u_ila_1 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe15]
 set_property port_width 1 [get_debug_ports u_ila_1/probe15]
-connect_debug_port u_ila_1/probe15 [get_nets [list zcash_fpga_top/control_top/debug_if1/val]]
+connect_debug_port u_ila_1/probe15 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/eop]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe16]
+set_property port_width 1 [get_debug_ports u_ila_1/probe16]
+connect_debug_port u_ila_1/probe16 [get_nets [list zcash_fpga_top/control_top/debug_if_rx/eop]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe17]
+set_property port_width 1 [get_debug_ports u_ila_1/probe17]
+connect_debug_port u_ila_1/probe17 [get_nets [list zcash_fpga_top/control_top/debug_if_tx/err]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe18]
+set_property port_width 1 [get_debug_ports u_ila_1/probe18]
+connect_debug_port u_ila_1/probe18 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/err]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe19]
+set_property port_width 1 [get_debug_ports u_ila_1/probe19]
+connect_debug_port u_ila_1/probe19 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/err]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe20]
+set_property port_width 1 [get_debug_ports u_ila_1/probe20]
+connect_debug_port u_ila_1/probe20 [get_nets [list zcash_fpga_top/control_top/debug_if_rx/err]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe21]
+set_property port_width 1 [get_debug_ports u_ila_1/probe21]
+connect_debug_port u_ila_1/probe21 [get_nets [list zcash_fpga_top/control_top/debug_if_tx/rdy]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe22]
+set_property port_width 1 [get_debug_ports u_ila_1/probe22]
+connect_debug_port u_ila_1/probe22 [get_nets [list zcash_fpga_top/control_top/debug_if_rx/rdy]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe23]
+set_property port_width 1 [get_debug_ports u_ila_1/probe23]
+connect_debug_port u_ila_1/probe23 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/rdy]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe24]
+set_property port_width 1 [get_debug_ports u_ila_1/probe24]
+connect_debug_port u_ila_1/probe24 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/rdy]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe25]
+set_property port_width 1 [get_debug_ports u_ila_1/probe25]
+connect_debug_port u_ila_1/probe25 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/sop]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe26]
+set_property port_width 1 [get_debug_ports u_ila_1/probe26]
+connect_debug_port u_ila_1/probe26 [get_nets [list zcash_fpga_top/control_top/debug_if_tx/sop]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe27]
+set_property port_width 1 [get_debug_ports u_ila_1/probe27]
+connect_debug_port u_ila_1/probe27 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/sop]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe28]
+set_property port_width 1 [get_debug_ports u_ila_1/probe28]
+connect_debug_port u_ila_1/probe28 [get_nets [list zcash_fpga_top/control_top/debug_if_rx/sop]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe29]
+set_property port_width 1 [get_debug_ports u_ila_1/probe29]
+connect_debug_port u_ila_1/probe29 [get_nets [list zcash_fpga_top/control_top/debug_if_rx/val]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe30]
+set_property port_width 1 [get_debug_ports u_ila_1/probe30]
+connect_debug_port u_ila_1/probe30 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_tx/val]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe31]
+set_property port_width 1 [get_debug_ports u_ila_1/probe31]
+connect_debug_port u_ila_1/probe31 [get_nets [list zcash_fpga_top/secp256k1_top/debug_if_rx/val]]
+create_debug_port u_ila_1 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe32]
+set_property port_width 1 [get_debug_ports u_ila_1/probe32]
+connect_debug_port u_ila_1/probe32 [get_nets [list zcash_fpga_top/control_top/debug_if_tx/val]]
+set_false_path -from [get_pins {zcash_fpga_top/core_rst1_sync/dat_reg[0][0]/C}] -to [get_pins {zcash_fpga_top/core_rst1_sync/dat_reg[2][0]_srl2/D}]
+set_false_path -from [get_pins {zcash_fpga_top/if_rst_sync/dat_reg[0][0]/C}] -to [get_pins {zcash_fpga_top/if_rst_sync/dat_reg[2][0]_srl2/D}]
 set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
 set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
 set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]

zcash_fpga/src/rtl/top/zcash_fpga_top.sv

@@ -36,7 +36,7 @@ module zcash_fpga_top
   if_axi_stream.source tx_if
 );
 
-logic rst_core0, rst_core1, rst_if, usr_rst, usr_rst_r;
+logic rst_core0, usr_rst_core1, rst_core1, rst_if, usr_rst_if, usr_rst, usr_rst_r;
 
 if_axi_stream #(.DAT_BYTS(CORE_DAT_BYTS)) equihash_axi(i_clk_core0);
 
@@ -53,30 +53,24 @@ always_ff @ (posedge i_clk_core0) begin
 end
 
 // Synchronize resets
-(* DONT_TOUCH = "yes" *)
+synchronizer  #(.DAT_BITS ( 1 ), .NUM_CLKS ( 3 )) core_rst1_sync (
-synchronizer  #(
-  .DAT_BITS ( 1 ),
-  .NUM_CLKS ( 3 )
-)
-core_rst1_sync (
   .i_clk_a ( i_clk_core0 ),
   .i_clk_b ( i_clk_core1 ),
-  .i_dat_a ( usr_rst_r || i_rst_core1 ),
+  .i_dat_a ( usr_rst_r   ),
-  .o_dat_b ( rst_core1 )
+  .o_dat_b ( usr_rst_core1 )
 );
 
-(* DONT_TOUCH = "yes" *)
+always_ff @ (posedge i_clk_core1) rst_core1 <= i_rst_core1 || usr_rst_core1;
-synchronizer  #(
+
-  .DAT_BITS ( 1 ),
+synchronizer  #(.DAT_BITS ( 1 ), .NUM_CLKS ( 3 )) if_rst_sync (
-  .NUM_CLKS ( 3 )
-)
-if_rst_sync (
   .i_clk_a ( i_clk_core0 ),
   .i_clk_b ( i_clk_if   ),
-  .i_dat_a ( usr_rst_r || i_rst_if ),
+  .i_dat_a ( usr_rst_r  ),
-  .o_dat_b ( rst_if )
+  .o_dat_b ( usr_rst_if )
 );
 
+always_ff @ (posedge i_clk_if) rst_if <= i_rst_if || usr_rst_if;
+
 // This block takes in the interface signals and interfaces with other blocks
 control_top #(
   .CORE_DAT_BYTS ( CORE_DAT_BYTS ),
@@ -100,48 +94,31 @@ control_top (
 
 
 // This block is used to verify a equihash solution
-generate if (ENB_VERIFY_EQUIHASH == 1) begin
+equihash_verif_top #(
-  equihash_verif_top #(
+  .DAT_BYTS( CORE_DAT_BYTS )
-    .DAT_BYTS( CORE_DAT_BYTS )
+)
-  )
+equihash_verif_top (
-  equihash_verif_top (
+  .i_clk ( i_clk_core0 ),
-    .i_clk ( i_clk_core0 ),
+  .i_rst ( rst_core0 || ENB_VERIFY_EQUIHASH == 0 ),
-    .i_rst ( rst_core0   ),
+  .i_clk_300 ( i_clk_core1 ), // Faster clock
-    .i_clk_300 ( i_clk_core1 ), // Faster clock
+  .i_rst_300 ( rst_core1 || ENB_VERIFY_EQUIHASH == 0 ), 
-    .i_rst_300 ( rst_core1   ), 
+  .i_axi      ( equihash_axi      ),
-    .i_axi      ( equihash_axi      ),
+  .o_mask     ( equihash_mask     ),
-    .o_mask     ( equihash_mask     ),
+  .o_mask_val ( equihash_mask_val )
-    .o_mask_val ( equihash_mask_val )
+);
-  );
+
-end else begin
-  always_comb begin
-    equihash_mask = 0;
-    equihash_mask_val = 0;
-    equihash_axi.rdy = 1;
-  end
-end
-endgenerate
 
 // This block is the ECCDSA block for curve secp256k1
-generate if (ENB_VERIFY_SECP256K1_SIG == 1) begin
+always_comb begin
-  always_comb begin
+ secp256k1_mm_if.reset_source();
-   secp256k1_mm_if.reset_source();
-  end
-  secp256k1_top secp256k1_top (
-    .i_clk      ( i_clk_core0 ),
-    .i_rst      ( rst_core0   ),
-    .if_cmd_rx  ( secp256k1_out_if ),
-    .if_cmd_tx  ( secp256k1_in_if  ),
-    .if_axi_mm  ( secp256k1_mm_if  )
-  );
-end else begin
-  always_comb begin
-    secp256k1_out_if.rdy = 1;
-    secp256k1_in_if.reset_source();
-    secp256k1_mm_if.reset_sink();
-  end
 end
-endgenerate
+secp256k1_top secp256k1_top (
+  .i_clk      ( i_clk_core0 ),
+  .i_rst      ( rst_core0 || ENB_VERIFY_SECP256K1_SIG == 0 ),
+  .if_cmd_rx  ( secp256k1_out_if ),
+  .if_cmd_tx  ( secp256k1_in_if  ),
+  .if_axi_mm  ( secp256k1_mm_if  )
+);
 
 
 endmodule