Update bls12_381 to use atomic writes, and have programmable reset
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4b772fed16
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fcdc3c4975
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@ -27,7 +27,9 @@ module bls12_381_axi_bridge (
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input [31:0] i_curr_inst_pt,
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input [31:0] i_last_inst_cnt,
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output logic [31:0] o_new_inst_pt,
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output logic o_new_inst_pt_val
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output logic o_new_inst_pt_val,
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output logic o_reset_inst_ram,
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output logic o_reset_data_ram
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);
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import bls12_381_pkg::*;
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@ -57,8 +59,12 @@ always_ff @ (posedge i_clk) begin
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wr_addr <= 0;
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o_new_inst_pt_val <= 0;
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o_new_inst_pt <= 0;
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o_reset_inst_ram <= 0;
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o_reset_data_ram <= 0;
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end else begin
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o_reset_inst_ram <= 0;
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o_reset_data_ram <= 0;
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o_new_inst_pt_val <= 0;
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data_ram_read <= data_ram_read << 1;
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@ -138,21 +144,24 @@ always_ff @ (posedge i_clk) begin
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o_new_inst_pt_val <= 1;
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o_new_inst_pt <= axi_lite_if.wdata;
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end
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32'h0: begin
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o_reset_inst_ram <= axi_lite_if.wdata[0]; // This will reset the instruction ram
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o_reset_data_ram <= axi_lite_if.wdata[1]; // This will reset the data ram
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end
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endcase
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end else
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// TODO change this to be atomic writes
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if (wr_addr < DATA_AXIL_START) begin
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// Instruction memory
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inst_ram_if.we <= 0;
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inst_ram_if.d <= axi_lite_if.wdata << (((wr_addr - INST_AXIL_START) % INST_RAM_ALIGN_BYTE)/INST_RAM_USR_WIDTH)*32;
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inst_ram_if.we[4*((wr_addr - INST_AXIL_START) % INST_RAM_ALIGN_BYTE)/INST_RAM_USR_WIDTH +: 4] <= {4{1'd1}};
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inst_ram_if.d[(((wr_addr - INST_AXIL_START) % INST_RAM_ALIGN_BYTE)/INST_RAM_USR_WIDTH)*32 +: 32] <= axi_lite_if.wdata;
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inst_ram_if.a <= (wr_addr - INST_AXIL_START) / INST_RAM_ALIGN_BYTE;
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// Only write on the last work to make this atomic
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if ((wr_addr - INST_AXIL_START) % 8 == 4) inst_ram_if.we <= 1;
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end else begin
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// Data memory
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data_ram_if.we <= 0;
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data_ram_if.d <= axi_lite_if.wdata << (((wr_addr - DATA_AXIL_START) % DATA_RAM_ALIGN_BYTE)/DATA_RAM_USR_WIDTH)*32;
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data_ram_if.we[4*((wr_addr - DATA_AXIL_START) % DATA_RAM_ALIGN_BYTE)/DATA_RAM_USR_WIDTH +: 4] <= {4{1'd1}};
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data_ram_if.d[(((wr_addr - DATA_AXIL_START) % DATA_RAM_ALIGN_BYTE)/DATA_RAM_USR_WIDTH)*32 +: 32] <= axi_lite_if.wdata;
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data_ram_if.a <= (wr_addr - DATA_AXIL_START) / DATA_RAM_ALIGN_BYTE;
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// Only write on the last work to make this atomic
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if ((wr_addr - DATA_AXIL_START) % 64 == 44) data_ram_if.we <= 1;
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end
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end
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end
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@ -39,17 +39,18 @@ bls12_381_interrupt_rpl_t interrupt_rpl;
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enum {WAIT_FIFO, SEND_HDR, SEND_DATA} interrupt_state;
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logic [7:0] interrupt_hdr_byt;
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// Instruction RAM
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logic [READ_CYCLE:0] inst_ram_read;
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logic [READ_CYCLE:0] data_ram_read;
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if_ram #(.RAM_WIDTH(bls12_381_pkg::INST_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::INST_RAM_DEPTH), .BYT_EN(7)) inst_ram_sys_if(.i_clk(i_clk), .i_rst(i_rst));
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if_ram #(.RAM_WIDTH(bls12_381_pkg::INST_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::INST_RAM_DEPTH), .BYT_EN(7)) inst_ram_usr_if(.i_clk(i_clk), .i_rst(i_rst));
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logic [READ_CYCLE:0] inst_ram_read, data_ram_read;
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logic reset_inst_ram, reset_data_ram;
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// Instruction RAM
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if_ram #(.RAM_WIDTH(bls12_381_pkg::INST_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::INST_RAM_DEPTH)) inst_ram_sys_if(.i_clk(i_clk), .i_rst(i_rst || reset_inst_ram));
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if_ram #(.RAM_WIDTH(bls12_381_pkg::INST_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::INST_RAM_DEPTH)) inst_ram_usr_if(.i_clk(i_clk), .i_rst(i_rst || reset_inst_ram));
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inst_t curr_inst;
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// Data RAM
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if_ram #(.RAM_WIDTH(bls12_381_pkg::DATA_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::DATA_RAM_DEPTH), .BYT_EN(48)) data_ram_sys_if(.i_clk(i_clk), .i_rst(i_rst));
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if_ram #(.RAM_WIDTH(bls12_381_pkg::DATA_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::DATA_RAM_DEPTH), .BYT_EN(48)) data_ram_usr_if(.i_clk(i_clk), .i_rst(i_rst));
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if_ram #(.RAM_WIDTH(bls12_381_pkg::DATA_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::DATA_RAM_DEPTH)) data_ram_sys_if(.i_clk(i_clk), .i_rst(i_rst || reset_data_ram));
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if_ram #(.RAM_WIDTH(bls12_381_pkg::DATA_RAM_WIDTH), .RAM_DEPTH(bls12_381_pkg::DATA_RAM_DEPTH)) data_ram_usr_if(.i_clk(i_clk), .i_rst(i_rst || reset_data_ram));
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data_t curr_data, new_data;
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// Loading the fifo with slots and outputting an interrupt
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@ -191,7 +192,9 @@ bls12_381_axi_bridge bls12_381_axi_bridge (
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.i_curr_inst_pt ( curr_inst_pt ),
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.i_last_inst_cnt ( last_inst_cnt ),
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.o_new_inst_pt ( new_inst_pt ),
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.o_new_inst_pt_val ( new_inst_pt_val )
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.o_new_inst_pt_val ( new_inst_pt_val ),
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.o_reset_inst_ram ( reset_inst_ram ),
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.o_reset_data_ram ( reset_data_ram )
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);
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always_comb begin
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@ -410,7 +413,7 @@ task task_copy_reg();
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if (data_ram_read[READ_CYCLE]) begin
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data_ram_sys_if.a <= curr_inst.b;
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new_data <= curr_data;
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data_ram_sys_if.we <= -1;
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data_ram_sys_if.we <= 1;
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end
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endtask
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@ -434,7 +437,7 @@ task task_scalar_inv();
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data_ram_sys_if.a <= curr_inst.b;
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new_data.pt <= curr_data.pt;
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new_data.dat <= binv_o_if.dat;
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data_ram_sys_if.we <= -1;
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data_ram_sys_if.we <= 1;
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cnt <= cnt + 1;
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end
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end
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@ -481,7 +484,7 @@ task task_point_mult();
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if (fp2_pt_mult_out_if.val) begin
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new_data.pt <= FP_JB;
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new_data.dat <= fp2_pt_mult_out_if.dat >> ((cnt-2)*2*DAT_BITS);
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data_ram_sys_if.we <= -1;
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data_ram_sys_if.we <= 1;
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data_ram_sys_if.a <= data_ram_sys_if.a + 1;
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cnt <= cnt + 1;
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if (cnt == 4) begin
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@ -520,7 +523,7 @@ task task_fp_fpoint_mult();
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if (fp2_pt_mult_out_if.val) begin
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new_data.pt <= FP_JB;
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new_data.dat <= fp2_pt_mult_out_if.dat >> ((cnt-2)*2*DAT_BITS);
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data_ram_sys_if.we <= -1;
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data_ram_sys_if.we <= 1;
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if (cnt > 2) data_ram_sys_if.a <= data_ram_sys_if.a + 1;
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cnt <= cnt + 1;
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if (cnt == 4) begin
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@ -557,7 +560,7 @@ task task_fp2_fpoint_mult();
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if (fp2_pt_mult_out_if.val) begin
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new_data.pt <= FP2_JB;
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new_data.dat <= fp2_pt_mult_out_if.dat >> ((cnt-2)*DAT_BITS);
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data_ram_sys_if.we <= -1;
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data_ram_sys_if.we <= 1;
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if (cnt > 2) data_ram_sys_if.a <= data_ram_sys_if.a + 1;
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cnt <= cnt + 1;
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if (cnt == 7) begin
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@ -52,7 +52,7 @@ bls12_381_top bls12_381_top (
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);
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task test_fp_point_mult();
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task test_fp_fpoint_mult();
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begin
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integer signed get_len;
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logic [common_pkg::MAX_SIM_BYTS*8-1:0] get_dat;
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@ -67,7 +67,7 @@ begin
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failed = 0;
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in_k = 381'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa;
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exp_p = point_mult(in_k, g_point);
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$display("Running test_fp_point_mult...");
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$display("Running test_fp_fpoint_mult...");
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axi_lite_if.peek(.addr(0), .data(rdata));
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assert(rdata == INST_AXIL_START) else $fatal("ERROR: AXI lite register returned wrong value");
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@ -127,13 +127,13 @@ begin
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$display("INFO: Last cycle count was %d", rdata);
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if(failed)
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$fatal(1, "ERROR: test_fp_point_mult FAILED");
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$fatal(1, "ERROR: test_fp_fpoint_mult FAILED");
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else
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$display("INFO: test_fp_point_mult PASSED");
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$display("INFO: test_fp_fpoint_mult PASSED");
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end
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endtask;
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task test_fp2_point_mult();
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task test_fp2_fpoint_mult();
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begin
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integer signed get_len;
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logic [common_pkg::MAX_SIM_BYTS*8-1:0] get_dat;
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@ -148,7 +148,7 @@ begin
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failed = 0;
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in_k = 381'h33333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333;
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exp_p = fp2_point_mult(in_k, g2_point);
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$display("Running test_fp2_point_mult...");
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$display("Running test_fp2_fpoint_mult...");
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// See what current instruction pointer is
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axi_lite_if.peek(.addr(32'h10), .data(rdata));
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@ -200,21 +200,21 @@ begin
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// See what current instruction pointer is
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axi_lite_if.peek(.addr(32'h10), .data(rdata));
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$display("INFO: Current instruction pointer is 0x%x, setting to 0 and writing NULL instruction", rdata);
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inst = '{code:NOOP_WAIT, a:16'd0, b:16'h0, c:16'd0};
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axi_lite_if.put_data_multiple(.data(inst), .addr(INST_AXIL_START), .len(8));
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axi_lite_if.poke(.addr(32'h10), .data(32'd0));
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repeat(10) @(posedge clk);
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axi_lite_if.peek(.addr(32'h10), .data(rdata));
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assert(rdata == 32'd0) else $fatal(1, "ERROR: could not set instruction pointer");
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if(failed)
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$fatal(1, "ERROR: test_fp2_point_mult FAILED");
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$fatal(1, "ERROR: test_fp2_fpoint_mult FAILED");
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else
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$display("INFO: test_fp2_point_mult PASSED");
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$display("INFO: test_fp2_fpoint_mult PASSED");
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end
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endtask;
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@ -227,8 +227,9 @@ initial begin
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!bls12_381_top.data_uram_reset.reset_done)
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@(posedge clk);
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test_fp_point_mult();
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test_fp2_point_mult();
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test_fp_fpoint_mult();
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test_fp2_fpoint_mult();
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#1us $finish();
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end
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