68 lines
3.3 KiB
Markdown
68 lines
3.3 KiB
Markdown
The work in this repo is the result of a Zcash foundation grant to develop open-source FPGA code that can be used to accelerate various aspects of the network.
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**An Architecture document is [here](zcash_fpga_design_doc_v1.1.x.pdf)**.
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While mainly developed for Equihash and the secp256k1 and bls12-381 curves, the code used in this repo can also be applied with minimum modification to other curves.
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** Currently still a work in progress
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# Repo folder structure
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Each top level folder is explained below. Inside each folder is source code written in systemverilog, and most blocks have a standalone self-checking testbench.
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## aws
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This contains the top / project files for building on a AWS (Amazon FPGA VU9P w/ 64GB DDR4).
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* This contains the zcash_fpga library (aws/cl_zcash/software/runtime/zcash_fpga.hpp) that can be used to interface with the FPGA over PCIe.
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* Instructions on how to build are in the architecture document.
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## bittware_xupvvh
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This contains the top / project files for building on the Bittware VVH board (VU37P FPGA w/ 8GB HBM, 16GB DDR4).
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## ip_cores
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These contain shared IP cores used by the projects in this repo. These include many functions, such as:
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* Hashing
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- Blake2b - single pipe implementation of blake2b and a pipline-unrolled version for high performance (single clock hash @ 200MHz after initial 52 clock delay).
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- SHA256 and SHA256d
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* Packages and interfaces for common use, along with many tasks to simplify simulation
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- AXI4
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- AXI4-lite
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- Block RAM
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* Fifo implementations
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* Hash map implementation
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- Fully parameterized for bit widths and uses CRC as the hashing function
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* Blocks for parsing/processing streams
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* Karabutsa multiplier
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- Fully parameterized for number of levels
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* Barret reduction for modulo reduction when the modulus does not allow fast reduction
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- Both a fully pipelined high performance version and a slower but smaller resource utilization version
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* Addition and subtraction modules
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- Fully parameterized so that they can be used for large bit-width arithmetic
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* Extended Euclidean algorithm for calculating multiplicative inverses
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* Resource arbitrators
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* General purpose elliptical curve point and element modules
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- Point multiplication, doubling, adding up to Fp^12 (towered over Fp^6 and Fp^2)
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- Element inversion
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- Multiplication by non-residue for use in towering
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- Exponentiation of Fp^12 elements
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## zcash_fpga
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This is the top level for the Zcash FPGA. It contains source code and testbenches for the blocks used in the Zcash acceleration engine.
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It optionally contains the following top-level engines (you can include in a build via parameters in the top level package):
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* Equihash verification engine
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- Verifies the equihash solution and difficulty filters
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* Transparent Signature Verification Engine (secp256k1 ECDSA core)
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- Uses efficient endomorphism to reduce key bit size
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- Signature verification calculates multiple EC point operations in parallel, using a resource-shared single fully pipelined karabutsa multiplier and quick modulo reduction technique
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* BLS12-381 Coprocessor (zk-SNARK accelerator)
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- General arithmetic over bls12-381 curve
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- Dual Point multiplication in Fp and Fp^2 (G1 and G2)
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- Frobenius map operations
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- The ate pairing
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- Miller loop and final exponentiation stage
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