mirror of https://github.com/FOME-Tech/fome-fw.git
no qc
This commit is contained in:
Matthew Kennedy
parent
3fe5e8f3e3
commit
5d7a30ce2b
|
|
@ -20,9 +20,6 @@ jobs:
|
|||
# What boards should we build for? In the 'include' section below,
|
||||
# set up what each of these boards needs to build.
|
||||
#
|
||||
# see also gen_config where we have a similar list for all boards!
|
||||
# see also build-primary-bundle where default/primary bundle is build separately
|
||||
#
|
||||
# build-target: [
|
||||
# alphax-2chan,
|
||||
# alphax-4chan,
|
||||
|
|
@ -31,7 +28,6 @@ jobs:
|
|||
# hellen72,
|
||||
# hellen81,
|
||||
# hellen88bmw,
|
||||
# hellen88bmw_avr,
|
||||
# hellen-nb1,
|
||||
# hellen-gm-e67,
|
||||
# hellenNA8_96,
|
||||
|
|
@ -45,14 +41,11 @@ jobs:
|
|||
# mre_f4_no_openblt,
|
||||
# mre_f4_debug,
|
||||
# mre_f4_recovery,
|
||||
# mre_f4_hardware_QC_special_build,
|
||||
# mre_f7,
|
||||
# prometheus_405,
|
||||
# prometheus_469,
|
||||
# proteus_f4,
|
||||
# proteus_f4_hardware_QC_special_build,
|
||||
# proteus_f7,
|
||||
# proteus_f7_hardware_QC_special_build,
|
||||
# proteus_h7,
|
||||
# proteus_legacy,
|
||||
# stm32f429_nucleo,
|
||||
|
|
@ -97,10 +90,6 @@ jobs:
|
|||
# folder: config/boards/hellen/hellen88bmw
|
||||
# ini-file: fome_hellen88bmw.ini
|
||||
|
||||
# - build-target: hellen88bmw_avr
|
||||
# folder: config/boards/hellen/hellen88bmw
|
||||
# ini-file: fome_hellen88bmw.ini
|
||||
|
||||
- build-target: hellen-nb1
|
||||
folder: config/boards/hellen/hellen-nb1
|
||||
ini-file: fome_hellen-nb1.ini
|
||||
|
|
@ -157,10 +146,6 @@ jobs:
|
|||
# folder: config/boards/microrusefi
|
||||
# ini-file: fome_mre_f4.ini
|
||||
|
||||
# - build-target: mre_f4_hardware_QC_special_build
|
||||
# folder: config/boards/microrusefi
|
||||
# ini-file: fome_mre_f4.ini
|
||||
|
||||
# - build-target: mre_f7
|
||||
# folder: config/boards/microrusefi
|
||||
# ini-file: fome_mre_f7.ini
|
||||
|
|
@ -177,18 +162,10 @@ jobs:
|
|||
folder: config/boards/proteus
|
||||
ini-file: fome_proteus_f4.ini
|
||||
|
||||
# - build-target: proteus_f4_hardware_QC_special_build
|
||||
# folder: config/boards/proteus
|
||||
# ini-file: fome_proteus_f4.ini
|
||||
|
||||
- build-target: proteus_f7
|
||||
folder: config/boards/proteus
|
||||
ini-file: fome_proteus_f7.ini
|
||||
|
||||
# - build-target: proteus_f7_hardware_QC_special_build
|
||||
# folder: config/boards/proteus
|
||||
# ini-file: fome_proteus_f7.ini
|
||||
|
||||
# - build-target: proteus_h7
|
||||
# folder: config/boards/proteus
|
||||
# ini-file: fome_proteus_h7.ini
|
||||
|
|
|
|||
|
|
@ -1,422 +0,0 @@
|
|||
/**
|
||||
* @file boards/f429-208/board.c
|
||||
*
|
||||
* @date Oct 14, 2022
|
||||
* @author Andrey Gusakov, 2022
|
||||
*/
|
||||
|
||||
#include "hal.h"
|
||||
#include "hal_community.h"
|
||||
#include "hal_sdram_lld.h"
|
||||
/* for UNUSED() */
|
||||
#include "efilib.h"
|
||||
|
||||
#include "board.h"
|
||||
|
||||
/*
|
||||
* SDRAM driver configuration structure.
|
||||
*/
|
||||
static const SDRAMConfig sdram_cfg = {
|
||||
.sdcr = (uint32_t) (FMC_ColumnBits_Number_8b |
|
||||
FMC_RowBits_Number_12b |
|
||||
FMC_SDMemory_Width_16b |
|
||||
FMC_InternalBank_Number_4 |
|
||||
FMC_CAS_Latency_3 |
|
||||
FMC_Write_Protection_Disable |
|
||||
FMC_SDClock_Period_2 |
|
||||
FMC_Read_Burst_Disable |
|
||||
FMC_ReadPipe_Delay_1),
|
||||
|
||||
.sdtr = (uint32_t)( (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
|
||||
(7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns))
|
||||
(4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
|
||||
(7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns))
|
||||
(2 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns))
|
||||
(2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns)
|
||||
(2 << 24)), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
|
||||
|
||||
.sdcmr = (uint32_t)(((4 - 1) << 5) |
|
||||
((FMC_SDCMR_MRD_BURST_LENGTH_2 |
|
||||
FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
|
||||
FMC_SDCMR_MRD_CAS_LATENCY_3 |
|
||||
FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
|
||||
FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9)),
|
||||
|
||||
/* if (STM32_SYSCLK == 180000000) ->
|
||||
64ms / 4096 = 15.625us
|
||||
15.625us * 90MHz = 1406 - 20 = 1386 */
|
||||
//.sdrtr = (1386 << 1),
|
||||
.sdrtr = (uint32_t)(683 << 1),
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Type of STM32 GPIO port setup.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t moder;
|
||||
uint32_t otyper;
|
||||
uint32_t ospeedr;
|
||||
uint32_t pupdr;
|
||||
uint32_t odr;
|
||||
uint32_t afrl;
|
||||
uint32_t afrh;
|
||||
} gpio_setup_t;
|
||||
|
||||
/**
|
||||
* @brief Type of STM32 GPIO initialization data.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
gpio_setup_t PAData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
gpio_setup_t PBData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
gpio_setup_t PCData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
gpio_setup_t PDData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
gpio_setup_t PEData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
gpio_setup_t PFData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
gpio_setup_t PGData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
gpio_setup_t PHData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
gpio_setup_t PIData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
|
||||
gpio_setup_t PJData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
|
||||
gpio_setup_t PKData;
|
||||
#endif
|
||||
} gpio_config_t;
|
||||
|
||||
/**
|
||||
* @brief STM32 GPIO static initialization data.
|
||||
*/
|
||||
static const gpio_config_t gpio_default_config = {
|
||||
#if STM32_HAS_GPIOA
|
||||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
||||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
||||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
||||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
||||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
||||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
|
||||
#endif
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
||||
|
||||
gpiop->OTYPER = config->otyper;
|
||||
gpiop->OSPEEDR = config->ospeedr;
|
||||
gpiop->PUPDR = config->pupdr;
|
||||
gpiop->ODR = config->odr;
|
||||
gpiop->AFRL = config->afrl;
|
||||
gpiop->AFRH = config->afrh;
|
||||
gpiop->MODER = config->moder;
|
||||
}
|
||||
|
||||
static void stm32_gpio_init(void) {
|
||||
|
||||
/* Enabling GPIO-related clocks, the mask comes from the
|
||||
registry header file.*/
|
||||
rccResetAHB1(STM32_GPIO_EN_MASK);
|
||||
rccEnableAHB1(STM32_GPIO_EN_MASK, true);
|
||||
|
||||
/* Initializing all the defined GPIO ports.*/
|
||||
#if STM32_HAS_GPIOA
|
||||
gpio_init(GPIOA, &gpio_default_config.PAData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
gpio_init(GPIOB, &gpio_default_config.PBData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
gpio_init(GPIOC, &gpio_default_config.PCData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
gpio_init(GPIOD, &gpio_default_config.PDData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
gpio_init(GPIOE, &gpio_default_config.PEData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
gpio_init(GPIOF, &gpio_default_config.PFData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
gpio_init(GPIOG, &gpio_default_config.PGData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
gpio_init(GPIOH, &gpio_default_config.PHData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
gpio_init(GPIOI, &gpio_default_config.PIData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
gpio_init(GPIOJ, &gpio_default_config.PJData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
gpio_init(GPIOK, &gpio_default_config.PKData);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#define SDRAM ((FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE)
|
||||
|
||||
/**
|
||||
* FMC_Command_Mode
|
||||
*/
|
||||
#define FMCCM_NORMAL ((uint32_t)0x00000000)
|
||||
#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001)
|
||||
#define FMCCM_PALL ((uint32_t)0x00000002)
|
||||
#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003)
|
||||
#define FMCCM_LOAD_MODE ((uint32_t)0x00000004)
|
||||
#define FMCCM_SELFREFRESH ((uint32_t)0x00000005)
|
||||
#define FMCCM_POWER_DOWN ((uint32_t)0x00000006)
|
||||
|
||||
static void __early_sdram_wait_ready(void) {
|
||||
/* Wait until the SDRAM controller is ready */
|
||||
while (SDRAM->SDSR & FMC_SDSR_BUSY);
|
||||
}
|
||||
|
||||
static void __early_sdram_delay(void)
|
||||
{
|
||||
/* something > 100uS */
|
||||
volatile int tmp = 168 * 1000 * 100;
|
||||
|
||||
do {
|
||||
tmp--;
|
||||
} while(tmp);
|
||||
}
|
||||
|
||||
static void __early_sdram_init(const SDRAMConfig *config)
|
||||
{
|
||||
uint32_t command_target = 0;
|
||||
|
||||
#ifdef rccResetFSMC
|
||||
rccResetFSMC();
|
||||
#endif
|
||||
rccEnableFSMC(FALSE);
|
||||
|
||||
SDRAM->SDCR1 = config->sdcr;
|
||||
SDRAM->SDTR1 = config->sdtr;
|
||||
SDRAM->SDCR2 = config->sdcr;
|
||||
SDRAM->SDTR2 = config->sdtr;
|
||||
|
||||
#if STM32_SDRAM_USE_SDRAM1
|
||||
command_target |= FMC_SDCMR_CTB1;
|
||||
#endif
|
||||
#if STM32_SDRAM_USE_SDRAM2
|
||||
command_target |= FMC_SDCMR_CTB2;
|
||||
#endif
|
||||
|
||||
/* Step 3: Configure a clock configuration enable command.*/
|
||||
__early_sdram_wait_ready();
|
||||
SDRAM->SDCMR = FMCCM_CLK_ENABLED | command_target;
|
||||
|
||||
/* Step 4: Insert delay (tipically 100uS).*/
|
||||
__early_sdram_delay();
|
||||
|
||||
/* Step 5: Configure a PALL (precharge all) command.*/
|
||||
__early_sdram_wait_ready();
|
||||
SDRAM->SDCMR = FMCCM_PALL | command_target;
|
||||
|
||||
/* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
|
||||
__early_sdram_wait_ready();
|
||||
SDRAM->SDCMR = FMCCM_AUTO_REFRESH | command_target |
|
||||
(config->sdcmr & FMC_SDCMR_NRFS);
|
||||
|
||||
/* Step 6.2: Send the second command.*/
|
||||
__early_sdram_wait_ready();
|
||||
SDRAM->SDCMR = FMCCM_AUTO_REFRESH | command_target |
|
||||
(config->sdcmr & FMC_SDCMR_NRFS);
|
||||
|
||||
/* Step 7: Program the external memory mode register.*/
|
||||
__early_sdram_wait_ready();
|
||||
SDRAM->SDCMR = FMCCM_LOAD_MODE | command_target |
|
||||
(config->sdcmr & FMC_SDCMR_MRD);
|
||||
|
||||
/* Step 8: Set clock.*/
|
||||
__early_sdram_wait_ready();
|
||||
SDRAM->SDRTR = config->sdrtr & FMC_SDRTR_COUNT;
|
||||
|
||||
__early_sdram_wait_ready();
|
||||
}
|
||||
|
||||
static int __early_sdram_test(void *base, size_t size)
|
||||
{
|
||||
size_t i;
|
||||
uint32_t *ptr = base;
|
||||
|
||||
/* test 0 */
|
||||
for (i = 0; i < size / sizeof(uint32_t); i++) {
|
||||
ptr[i] = 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < size / sizeof(uint32_t); i++) {
|
||||
if (ptr[i] != 0)
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* test 1 */
|
||||
for (i = 0; i < size / sizeof(uint32_t); i++) {
|
||||
ptr[i] = 0xffffffff;
|
||||
}
|
||||
|
||||
for (i = 0; i < size / sizeof(uint32_t); i++) {
|
||||
if (ptr[i] != 0xffffffff)
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* test 2 */
|
||||
for (i = 0; i < size / sizeof(uint32_t); i++) {
|
||||
ptr[i] = i;
|
||||
}
|
||||
|
||||
for (i = 0; i < size / sizeof(uint32_t); i++) {
|
||||
if (ptr[i] != i)
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Early initialization code.
|
||||
* @details GPIO ports and system clocks are initialized before everything
|
||||
* else.
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
stm32_gpio_init();
|
||||
stm32_clock_init();
|
||||
|
||||
/*
|
||||
* Initialise FSMC for SDRAM.
|
||||
*/
|
||||
#if 0
|
||||
/* clear driver struct */
|
||||
memset(&SDRAMD1, 0 sizeof(SDRAMD1));
|
||||
sdramInit();
|
||||
sdramStart(&SDRAMD1, &sdram_cfg);
|
||||
#else
|
||||
__early_sdram_init(&sdram_cfg);
|
||||
#endif
|
||||
|
||||
if (1) {
|
||||
/* yes, hardcoded values */
|
||||
__early_sdram_test((void *) 0xD0000000, 8 * 1024 * 1024);
|
||||
}
|
||||
}
|
||||
|
||||
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief SDC card detection.
|
||||
*/
|
||||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp)
|
||||
{
|
||||
UNUSED(sdcp);
|
||||
/* TODO: Fill the implementation.*/
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDC card write protection detection.
|
||||
*/
|
||||
bool sdc_lld_is_write_protected(SDCDriver *sdcp)
|
||||
{
|
||||
UNUSED(sdcp);
|
||||
/* TODO: Fill the implementation.*/
|
||||
return false;
|
||||
}
|
||||
#endif /* HAL_USE_SDC */
|
||||
|
||||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief MMC_SPI card detection.
|
||||
*/
|
||||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp)
|
||||
{
|
||||
UNUSED(mmcp);
|
||||
/* TODO: Fill the implementation.*/
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MMC_SPI card write protection detection.
|
||||
*/
|
||||
bool mmc_lld_is_write_protected(MMCDriver *mmcp)
|
||||
{
|
||||
UNUSED(mmcp);
|
||||
/* TODO: Fill the implementation.*/
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,24 +0,0 @@
|
|||
HALCONFDIR = $(BOARD_DIR)
|
||||
|
||||
# List of all the board related files.
|
||||
BOARDCPPSRC = $(BOARD_DIR)/board_configuration.cpp
|
||||
|
||||
# Required include directories
|
||||
# STM32F429 has FSMC with SDRAM support
|
||||
DDEFS += -DFIRMWARE_ID=\"stm32f429\"
|
||||
IS_STM32F429 = yes
|
||||
EFI_HAS_EXT_SDRAM = yes
|
||||
|
||||
#LED
|
||||
DDEFS += -DLED_CRITICAL_ERROR_BRAIN_PIN=Gpio::B11
|
||||
|
||||
DDEFS += -DSTM32_FSMC_USE_FSMC1=TRUE -DSTM32_SDRAM_USE_SDRAM2=TRUE
|
||||
|
||||
DDEFS += -DHAL_USE_SDRAM=TRUE
|
||||
DDEFS += -DHAL_USE_FSMC=TRUE
|
||||
|
||||
# see signature_haba208.h
|
||||
DDEFS += -DSHORT_BOARD_NAME=haba208
|
||||
|
||||
# Shared variables
|
||||
ALLINC += $(BOARDINC)
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
#include "pch.h"
|
||||
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @todo Add your board-specific code, if any.
|
||||
*/
|
||||
void boardInit(void)
|
||||
{
|
||||
/* NOP */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Board-specific configuration defaults.
|
||||
* @todo Add your board-specific code, if any.
|
||||
*/
|
||||
void setBoardDefaultConfiguration() {
|
||||
engineConfiguration->communicationLedPin = Gpio::Unassigned;
|
||||
engineConfiguration->runningLedPin = Gpio::G13; /* LD3 - green */
|
||||
engineConfiguration->warningLedPin = Gpio::Unassigned;
|
||||
}
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
#-DDUMMY -DEFI_ENABLE_ASSERTS=FALSE -DCH_DBG_ENABLE_ASSERTS=FALSE -DCH_DBG_ENABLE_STACK_CHECK=FALSE -DCH_DBG_FILL_THREADS=FALSE -DCH_DBG_THREADS_PROFILING=FALSE"
|
||||
|
||||
bash ../common_make.sh f429-208 ARCH_STM32F4
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
cd ..
|
||||
|
||||
export EXTRA_PARAMS="-DDUMMY \
|
||||
-DEFI_SOFTWARE_KNOCK=FALSE \
|
||||
-DHAL_TRIGGER_USE_ADC=TRUE \
|
||||
-DSTM32_ADC_USE_ADC3=TRUE \
|
||||
"
|
||||
|
||||
|
||||
bash ../common_make.sh hellen/hellen88bmw ARCH_STM32F4
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
@echo off
|
||||
bash.exe compile_mre_f4_hardware_QC_special_build.sh
|
||||
|
|
@ -130,11 +130,6 @@ static void setupDefaultSensorInputs() {
|
|||
|
||||
setCommonNTCSensor(&engineConfiguration->auxTempSensor1, 2700);
|
||||
setCommonNTCSensor(&engineConfiguration->auxTempSensor2, 2700);
|
||||
|
||||
#if HW_CHECK_MODE
|
||||
engineConfiguration->auxTempSensor1.adcChannel = EFI_ADC_2;
|
||||
engineConfiguration->auxTempSensor2.adcChannel = EFI_ADC_3;
|
||||
#endif // HW_CHECK_MODE
|
||||
}
|
||||
|
||||
void setBoardConfigOverrides() {
|
||||
|
|
|
|||
|
|
@ -1,26 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
export EXTRA_PARAMS="-DDUMMY \
|
||||
-DHW_CHECK_MODE=TRUE \
|
||||
-DANALOG_HW_CHECK_MODE=TRUE \
|
||||
-DEFI_HPFP=FALSE \
|
||||
-DEFI_ALTERNATOR_CONTROL=FALSE \
|
||||
-DEFI_LOGIC_ANALYZER=FALSE \
|
||||
-DEFI_TOOTH_LOGGER=FALSE \
|
||||
-DEFI_LUA=FALSE \
|
||||
-DEFI_MALFUNCTION_INDICATOR=FALSE \
|
||||
-DEFI_AUX_PID=FALSE \
|
||||
-DEFI_MAX_31855=FALSE \
|
||||
-DEFI_ENGINE_SNIFFER=FALSE \
|
||||
-DEFI_STORAGE_INT_FLASH=FALSE \
|
||||
-DEFI_LAUNCH_CONTROL=FALSE \
|
||||
-DEFI_LAUNCH_CONTROL=FALSE \
|
||||
-DHW_CHECK_ALWAYS_STIMULATE=TRUE \
|
||||
-DRAMDISK_INVALID"
|
||||
|
||||
export VAR_DEF_ENGINE_TYPE=-DDEFAULT_ENGINE_TYPE=MRE_BOARD_NEW_TEST
|
||||
|
||||
# this QC configuration is used to assert our status with debug info
|
||||
export DEBUG_LEVEL_OPT="-O0 -ggdb -g"
|
||||
|
||||
bash ../common_make.sh microrusefi ARCH_STM32F4
|
||||
|
|
@ -102,18 +102,8 @@ static void setupEtb() {
|
|||
|
||||
static void setupDefaultSensorInputs() {
|
||||
// trigger inputs
|
||||
#if VR_HW_CHECK_MODE
|
||||
// set_trigger_input_pin 0 PE7
|
||||
engineConfiguration->triggerInputPins[0] = PROTEUS_VR_1;
|
||||
engineConfiguration->camInputs[0] = PROTEUS_VR_2;
|
||||
#else
|
||||
// Digital channel 1 as default - others not set
|
||||
engineConfiguration->triggerInputPins[0] = PROTEUS_DIGITAL_1;
|
||||
engineConfiguration->camInputs[0] = Gpio::Unassigned;
|
||||
#endif
|
||||
|
||||
engineConfiguration->triggerInputPins[1] = Gpio::Unassigned;
|
||||
|
||||
|
||||
engineConfiguration->clt.adcChannel = PROTEUS_IN_CLT;
|
||||
engineConfiguration->iat.adcChannel = PROTEUS_IN_IAT;
|
||||
|
|
|
|||
|
|
@ -1,9 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
export EXTRA_PARAMS="-DVR_HW_CHECK_MODE=TRUE -DHW_CHECK_MODE=TRUE -DHW_CHECK_SD=TRUE -DHW_CHECK_ALWAYS_STIMULATE=TRUE"
|
||||
|
||||
export VAR_DEF_ENGINE_TYPE=-DDEFAULT_ENGINE_TYPE=PROTEUS_QC_TEST_BOARD
|
||||
|
||||
# export DEBUG_LEVEL_OPT="-O0 -ggdb -g"
|
||||
|
||||
bash ../common_make.sh proteus ARCH_STM32F4
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
export EXTRA_PARAMS="-DVR_HW_CHECK_MODE=TRUE -DHW_CHECK_MODE=TRUE -DHW_CHECK_SD=TRUE -DHW_CHECK_ALWAYS_STIMULATE=TRUE"
|
||||
|
||||
export VAR_DEF_ENGINE_TYPE=-DDEFAULT_ENGINE_TYPE=PROTEUS_QC_TEST_BOARD
|
||||
|
||||
# export DEBUG_LEVEL_OPT="-O0 -ggdb -g"
|
||||
|
||||
bash ../common_make.sh proteus ARCH_STM32F7
|
||||
|
|
@ -4,10 +4,6 @@ rusEFI supports quite a wide array of hardware - we support stm32f4 and we suppo
|
|||
|
||||
For best user experience we have more than a dozen of different _binaries_ which are all compiled from same _firmware_ files with different configuration. This folder is all about that process.
|
||||
|
||||
|
||||
See [misc/jenkins/compile_other_versions/run.bat](misc/jenkins/compile_other_versions/run.bat) which is executed by build server.
|
||||
|
||||
|
||||
See https://rusefi.com/build_server/
|
||||
|
||||
By definition, BOARD_NAME is a folder in firmware\config\boards
|
||||
|
|
|
|||
|
|
@ -826,12 +826,6 @@ int TunerStudio::handleCrcCommand(TsChannelBase* tsChannel, char *data, int inco
|
|||
#endif /* ENABLE_PERF_TRACE */
|
||||
case TS_GET_CONFIG_ERROR: {
|
||||
const char* configError = getCriticalErrorMessage();
|
||||
#if HW_CHECK_MODE
|
||||
// analog input errors are returned as firmware error in QC mode
|
||||
if (!hasFirmwareError()) {
|
||||
strcpy((char*)configError, "FACTORY_MODE_PLEASE_CONTACT_SUPPORT");
|
||||
}
|
||||
#endif // HW_CHECK_MODE
|
||||
tsChannel->sendResponse(TS_CRC, reinterpret_cast<const uint8_t*>(configError), strlen(configError), true);
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -313,18 +313,7 @@ class CommunicationBlinkingTask : public PeriodicTimerController {
|
|||
setAllLeds(0);
|
||||
} else if (counter % 2 == 0) {
|
||||
enginePins.communicationLedPin.setValue(0);
|
||||
#if HW_CHECK_SD
|
||||
extern int totalLoggedBytes;
|
||||
if (totalLoggedBytes > 2000) {
|
||||
enginePins.communicationLedPin.setValue(1);
|
||||
}
|
||||
#endif // HW_CHECK_SD
|
||||
|
||||
//#if HW_CHECK_MODE
|
||||
// // we have to do anything possible to help users notice FACTORY MODE
|
||||
// enginePins.errorLedPin.setValue(1);
|
||||
// enginePins.runningLedPin.setValue(1);
|
||||
//#endif // HW_CHECK_MODE
|
||||
if (!lowVBatt) {
|
||||
enginePins.warningLedPin.setValue(0);
|
||||
}
|
||||
|
|
@ -354,11 +343,6 @@ extern int totalLoggedBytes;
|
|||
}
|
||||
|
||||
enginePins.communicationLedPin.setValue(1);
|
||||
//#if HW_CHECK_MODE
|
||||
// // we have to do anything possible to help users notice FACTORY MODE
|
||||
// enginePins.errorLedPin.setValue(0);
|
||||
// enginePins.runningLedPin.setValue(0);
|
||||
//#endif // HW_CHECK_MODE
|
||||
|
||||
#if EFI_ENGINE_CONTROL
|
||||
if (lowVBatt || isTriggerErrorNow() || isIgnitionTimingError()) {
|
||||
|
|
@ -696,11 +680,7 @@ DcHardware *getdcHardware();
|
|||
extern FrequencySensor vehicleSpeedSensor;
|
||||
tsOutputChannels->vssEdgeCounter = vehicleSpeedSensor.eventCounter;
|
||||
|
||||
#if HW_CHECK_MODE
|
||||
tsOutputChannels->hasCriticalError = 1;
|
||||
#else
|
||||
tsOutputChannels->hasCriticalError = hasFirmwareError();
|
||||
#endif // HW_CHECK_MODE
|
||||
|
||||
tsOutputChannels->isWarnNow = engine->engineState.warnings.isWarningNow();
|
||||
|
||||
|
|
|
|||
|
|
@ -121,14 +121,6 @@ void Engine::updateTriggerWaveform() {
|
|||
#endif /* EFI_ENGINE_CONTROL && EFI_SHAFT_POSITION_INPUT */
|
||||
}
|
||||
|
||||
#if ANALOG_HW_CHECK_MODE
|
||||
static void assertCloseTo(const char* msg, float actual, float expected) {
|
||||
if (actual < 0.95f * expected || actual > 1.05f * expected) {
|
||||
firmwareError(OBD_PCM_Processor_Fault, "%s validation failed actual=%f vs expected=%f", msg, actual, expected);
|
||||
}
|
||||
}
|
||||
#endif // ANALOG_HW_CHECK_MODE
|
||||
|
||||
void Engine::periodicSlowCallback() {
|
||||
ScopePerf perf(PE::EnginePeriodicSlowCallback);
|
||||
|
||||
|
|
@ -175,32 +167,6 @@ void Engine::periodicSlowCallback() {
|
|||
void baroLps25Update();
|
||||
baroLps25Update();
|
||||
#endif // EFI_PROD_CODE
|
||||
|
||||
#if ANALOG_HW_CHECK_MODE
|
||||
efiAssertVoid(OBD_PCM_Processor_Fault, isAdcChannelValid(engineConfiguration->clt.adcChannel), "No CLT setting");
|
||||
efitimesec_t secondsNow = getTimeNowS();
|
||||
|
||||
#if ! HW_CHECK_ALWAYS_STIMULATE
|
||||
fail("HW_CHECK_ALWAYS_STIMULATE required to have self-stimulation")
|
||||
#endif
|
||||
|
||||
int hwCheckRpm = 204;
|
||||
if (secondsNow > 2 && secondsNow < 180) {
|
||||
assertCloseTo("RPM", Sensor::get(SensorType::Rpm).Value, hwCheckRpm);
|
||||
} else if (!hasFirmwareError() && secondsNow > 180) {
|
||||
static bool isHappyTest = false;
|
||||
if (!isHappyTest) {
|
||||
setTriggerEmulatorRPM(5 * hwCheckRpm);
|
||||
efiPrintf("TEST PASSED");
|
||||
isHappyTest = true;
|
||||
}
|
||||
}
|
||||
|
||||
assertCloseTo("clt", Sensor::getRaw(SensorType::Clt), 1.351f);
|
||||
assertCloseTo("iat", Sensor::getRaw(SensorType::Iat), 2.245f);
|
||||
assertCloseTo("aut1", Sensor::getRaw(SensorType::AuxTemp1), 2.750f);
|
||||
assertCloseTo("aut2", Sensor::getRaw(SensorType::AuxTemp2), 3.176f);
|
||||
#endif // ANALOG_HW_CHECK_MODE
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -238,7 +238,6 @@ static void handleFuel(int rpm, efitick_t nowNt, float currentPhase, float nextP
|
|||
void mainTriggerCallback(uint32_t trgEventIndex, efitick_t edgeTimestamp, angle_t currentPhase, angle_t nextPhase) {
|
||||
ScopePerf perf(PE::MainTriggerCallback);
|
||||
|
||||
#if ! HW_CHECK_MODE
|
||||
if (hasFirmwareError()) {
|
||||
/**
|
||||
* In case on a major error we should not process any more events.
|
||||
|
|
@ -246,7 +245,6 @@ void mainTriggerCallback(uint32_t trgEventIndex, efitick_t edgeTimestamp, angle_
|
|||
*/
|
||||
return;
|
||||
}
|
||||
#endif // HW_CHECK_MODE
|
||||
|
||||
int rpm = engine->rpmCalculator.getCachedRpm();
|
||||
if (rpm == 0) {
|
||||
|
|
|
|||
|
|
@ -294,21 +294,7 @@ static FlashState readConfiguration() {
|
|||
}
|
||||
|
||||
void readFromFlash() {
|
||||
#if HW_CHECK_MODE
|
||||
/*
|
||||
* getFlashAddr does device validation, we want validation to be invoked even while we are
|
||||
* HW_CHECK_MODE mode where we would not need actual address
|
||||
* todo: rename method to emphasis the fact of validation check?
|
||||
*/
|
||||
getFlashAddrFirstCopy();
|
||||
getFlashAddrSecondCopy();
|
||||
|
||||
resetConfigurationExt(DEFAULT_ENGINE_TYPE);
|
||||
|
||||
FlashState result = FlashState::Ok;
|
||||
#else
|
||||
FlashState result = readConfiguration();
|
||||
#endif
|
||||
|
||||
switch (result) {
|
||||
case FlashState::CrcFailed:
|
||||
|
|
|
|||
|
|
@ -260,20 +260,6 @@ void hwHandleVvtCamSignal(TriggerValue front, efitick_t nowNt, int index) {
|
|||
warning(CUSTOM_VVT_MODE_NOT_SELECTED, "VVT: event on %d but no mode", camIndex);
|
||||
}
|
||||
|
||||
#if VR_HW_CHECK_MODE
|
||||
// some boards do not have hardware VR input LEDs which makes such boards harder to validate
|
||||
// from experience we know that assembly mistakes happen and quality control is required
|
||||
extern ioportid_t criticalErrorLedPort;
|
||||
extern ioportmask_t criticalErrorLedPin;
|
||||
|
||||
for (int i = 0 ; i < 100 ; i++) {
|
||||
// turning pin ON and busy-waiting a bit
|
||||
palWritePad(criticalErrorLedPort, criticalErrorLedPin, 1);
|
||||
}
|
||||
|
||||
palWritePad(criticalErrorLedPort, criticalErrorLedPin, 0);
|
||||
#endif // VR_HW_CHECK_MODE
|
||||
|
||||
const auto& vvtShape = tc->vvtShape[camIndex];
|
||||
|
||||
bool isVvtWithRealDecoder = vvtWithRealDecoder(engineConfiguration->vvtMode[camIndex]);
|
||||
|
|
@ -404,24 +390,6 @@ uint32_t triggerMaxDuration = 0;
|
|||
void hwHandleShaftSignal(int signalIndex, bool isRising, efitick_t timestamp) {
|
||||
TriggerCentral *tc = getTriggerCentral();
|
||||
ScopePerf perf(PE::HandleShaftSignal);
|
||||
#if VR_HW_CHECK_MODE
|
||||
// some boards do not have hardware VR input LEDs which makes such boards harder to validate
|
||||
// from experience we know that assembly mistakes happen and quality control is required
|
||||
extern ioportid_t criticalErrorLedPort;
|
||||
extern ioportmask_t criticalErrorLedPin;
|
||||
|
||||
#if HW_CHECK_ALWAYS_STIMULATE
|
||||
disableTriggerStimulator();
|
||||
#endif // HW_CHECK_ALWAYS_STIMULATE
|
||||
|
||||
|
||||
for (int i = 0 ; i < 100 ; i++) {
|
||||
// turning pin ON and busy-waiting a bit
|
||||
palWritePad(criticalErrorLedPort, criticalErrorLedPin, 1);
|
||||
}
|
||||
|
||||
palWritePad(criticalErrorLedPort, criticalErrorLedPin, 0);
|
||||
#endif // VR_HW_CHECK_MODE
|
||||
|
||||
if (tc->directSelfStimulation || !tc->hwTriggerInputEnabled) {
|
||||
// sensor noise + self-stim = loss of trigger sync
|
||||
|
|
|
|||
|
|
@ -268,12 +268,6 @@ void runRusEfiWithConfig() {
|
|||
startCanConsole();
|
||||
#endif /* EFI_CAN_SERIAL */
|
||||
|
||||
#if HW_CHECK_ALWAYS_STIMULATE
|
||||
// we need a special binary for final assembly check. We cannot afford to require too much software or too many steps
|
||||
// to be executed at the place of assembly
|
||||
enableTriggerStimulator();
|
||||
#endif // HW_CHECK_ALWAYS_STIMULATE
|
||||
|
||||
#if EFI_LUA
|
||||
startLua();
|
||||
#endif // EFI_LUA
|
||||
|
|
|
|||
|
|
@ -1,3 +0,0 @@
|
|||
@echo off
|
||||
bash.exe misc\jenkins\compile_other_versions\compile.sh %1 %2 %3 %4
|
||||
bash.exe misc\jenkins\compile_other_versions\prepare_bundle.sh %1 %2 %3 %4
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
set script_name=run.bat
|
||||
echo Entering %script_name%
|
||||
echo "RUSEFI_BUILD_FTP_USER=%RUSEFI_BUILD_FTP_USER%"
|
||||
|
||||
pwd
|
||||
|
||||
call misc\jenkins\build_java_console.bat
|
||||
if not exist java_console_binary/rusefi_console.jar exit -1
|
||||
|
||||
call misc\jenkins\build_simulator.bat
|
||||
if not exist simulator/build/rusefi_simulator.exe exit -1
|
||||
|
||||
rem #
|
||||
rem # see gen_config.sh where short<>long name dictionary is hard-coded
|
||||
rem #
|
||||
|
||||
call misc\jenkins\compile_other_versions\compile_and_upload.bat frankenso frankenso_na6
|
||||
IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
pwd
|
||||
|
||||
call misc\jenkins\compile_other_versions\compile_and_upload.bat kinetis kinetis
|
||||
IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
|
||||
call misc\jenkins\compile_other_versions\compile_and_upload.bat microrusefi mre_f4 rusefi_mre_f4.ini
|
||||
IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
pwd
|
||||
|
||||
rem call misc\jenkins\compile_other_versions\compile_and_upload.bat microrusefi mre_f4_slave rusefi_mre_f7.ini
|
||||
rem IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
rem IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
rem pwd
|
||||
|
||||
call misc\jenkins\compile_other_versions\compile_and_upload.bat microrusefi mre_f4_hardware_QC_special_build rusefi_microrusefi.ini
|
||||
IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
pwd
|
||||
|
||||
set f7_console_setting=firmware\config\boards\nucleo_f767\rusefi_console_properties.xml
|
||||
|
||||
rem folter_name configuration_name [optional .ini file name]
|
||||
|
||||
call misc\jenkins\compile_other_versions\compile_and_upload.bat microrusefi mre_f7 rusefi_microrusefi.ini %f7_console_setting%
|
||||
IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
pwd
|
||||
|
||||
rem call misc\jenkins\compile_other_versions\compile_and_upload.bat microrusefi mre_f7_test rusefi_microrusefi.ini %f7_console_setting%
|
||||
rem IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
rem IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
rem pwd
|
||||
|
||||
call misc\jenkins\compile_other_versions\compile_and_upload.bat prometheus prometheus_405 prometheus_405.ini
|
||||
IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
pwd
|
||||
|
||||
|
||||
call misc\jenkins\compile_other_versions\compile_and_upload.bat prometheus prometheus_469 prometheus_469.ini
|
||||
IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
pwd
|
||||
|
||||
call misc\jenkins\compile_other_versions\compile_and_upload.bat proteus proteus_f4 rusefi_proteus_f4.ini
|
||||
IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
pwd
|
||||
|
||||
call misc\jenkins\compile_other_versions\compile_and_upload.bat proteus proteus_f7 rusefi_proteus_f7.ini
|
||||
IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
pwd
|
||||
|
||||
|
||||
call misc\jenkins\compile_other_versions\compile_and_upload.bat nucleo_f767 stm32f767_nucleo no %f7_console_setting%
|
||||
IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
pwd
|
||||
|
||||
|
||||
rem call misc\jenkins\compile_other_versions\compile_and_upload.bat nucleo_f767 stm32f767_osc no %f7_console_setting%
|
||||
rem IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
rem IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
rem pwd
|
||||
|
||||
call misc\jenkins\compile_other_versions\compile_and_upload.bat prometheus prometheus_405 rusefi_prometheus_405.ini
|
||||
IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
pwd
|
||||
|
||||
|
||||
call misc\jenkins\compile_other_versions\compile_and_upload.bat prometheus prometheus_469 rusefi_prometheus_469.ini
|
||||
IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat
|
||||
IF %ERRORLEVEL% NEQ 0 EXIT /B 1
|
||||
pwd
|
||||
|
|
@ -24,8 +24,6 @@
|
|||
#define EFI_ENABLE_CRITICAL_ENGINE_STOP TRUE
|
||||
#define EFI_ENABLE_ENGINE_WARNING TRUE
|
||||
|
||||
#define HW_CHECK_MODE FALSE
|
||||
|
||||
#define SC_BUFFER_SIZE 4000
|
||||
|
||||
#define EFI_ACTIVE_CONFIGURATION_IN_FLASH FALSE
|
||||
|
|
|
|||
Loading…
Reference in New Issue