mirror of https://github.com/PentHertz/srsLTE.git
sched, fix - avoid tpc commands when target pusch and pucch snr are not specified
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@ -110,14 +110,14 @@ public:
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* @remark See TS 36.213 Section 5.1.1
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* @return accumulated TPC value {-1, 0, 1, 3}
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*/
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uint8_t encode_pusch_tpc() { return enconde_tpc(PUSCH_CODE); }
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uint8_t encode_pusch_tpc() { return encode_tpc(PUSCH_CODE); }
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/**
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* Called during DCI format1/2A/A encoding to set PUCCH TPC command
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* @remark See TS 36.213 Section 5.1.2
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* @return accumulated TPC value {-1, 0, 1, 3}
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*/
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uint8_t encode_pucch_tpc() { return enconde_tpc(PUCCH_CODE); }
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uint8_t encode_pucch_tpc() { return encode_tpc(PUCCH_CODE); }
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uint32_t max_ul_prbs() const { return max_prbs_cached; }
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@ -138,18 +138,14 @@ private:
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return 1;
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}
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}
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uint8_t enconde_tpc(uint32_t cc)
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uint8_t encode_tpc(uint32_t cc)
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{
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float target_snr_dB = cc == PUSCH_CODE ? target_pusch_snr_dB : target_pucch_snr_dB;
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auto& ch_snr = snr_estim_list[cc];
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assert(ch_snr.pending_delta == 0); // ensure called once per {cc,tti}
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if (target_snr_dB < 0) {
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// undefined target SINR case. Increase Tx power once per PHR, considering the number of allocable PRBs remains
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// unchanged
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if (not ch_snr.phr_flag) {
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ch_snr.pending_delta = (max_prbs_cached == nof_prb) ? 1 : (last_phr < 0 ? -1 : 0);
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ch_snr.phr_flag = true;
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}
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// undefined target sinr case.
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ch_snr.pending_delta = 0;
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} else {
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// target SINR is finite and there is power headroom
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float diff = target_snr_dB - ch_snr.snr_avg.value();
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@ -100,7 +100,7 @@ int test_undefined_target_snr()
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TESTASSERT(sum_pusch == 0);
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TESTASSERT(sum_pucch == 0);
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// TEST: If the PHR allows full utilization of available PRBs, the TPC slightly increments UL Tx power
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// TEST: Check that high PHR allows full utilization of available PRBs, TPC remains at zero (no target SINR)
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int phr = 30;
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tpcfsm.set_phr(phr);
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TESTASSERT(tpcfsm.max_ul_prbs() == 50);
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@ -111,8 +111,7 @@ int test_undefined_target_snr()
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sum_pusch += decode_tpc(tpcfsm.encode_pusch_tpc());
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sum_pucch += decode_tpc(tpcfsm.encode_pucch_tpc());
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}
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TESTASSERT(sum_pusch > 0 and sum_pusch <= 3);
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TESTASSERT(sum_pucch > 0 and sum_pucch <= 3);
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TESTASSERT(sum_pusch == 0 and sum_pucch == 0);
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// TEST: PHR is too low to allow all PRBs to be allocated. This event should not affect TPC commands
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phr = 5;
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@ -135,8 +134,8 @@ int test_undefined_target_snr()
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sum_pusch += decode_tpc(tpcfsm.encode_pusch_tpc());
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sum_pucch += decode_tpc(tpcfsm.encode_pucch_tpc());
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}
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TESTASSERT(sum_pusch <= 0 and sum_pusch >= -1);
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TESTASSERT(sum_pucch <= 0 and sum_pucch >= -1);
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TESTASSERT(sum_pusch == 0);
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TESTASSERT(sum_pucch == 0);
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return SRSRAN_SUCCESS;
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}
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