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ChibiOS
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Fixed bug #1124. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_20.3.x@13862 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-09-20 09:35:14 +00:00
parent 2c0ead7cbb
commit 033c92c92d
2 changed files with 26 additions and 15 deletions
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40
os/hal/ports/STM32/STM32F4xx/stm32_registry.h
View File

@ -291,7 +291,8 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX TRUE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 2)) STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000303 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@ -665,7 +666,8 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX FALSE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 2)) STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000303 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@ -675,7 +677,7 @@
#define STM32_HAS_SPI2 TRUE #define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE #define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX TRUE #define STM32_SPI2_I2S_FULLDUPLEX FALSE
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
#define STM32_SPI2_RX_DMA_CHN 0x00000000 #define STM32_SPI2_RX_DMA_CHN 0x00000000
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) #define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
@ -683,7 +685,7 @@
#define STM32_HAS_SPI3 TRUE #define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE #define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX TRUE #define STM32_SPI3_I2S_FULLDUPLEX FALSE
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ #define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
STM32_DMA_STREAM_ID_MSK(1, 2)) STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_SPI3_RX_DMA_CHN 0x00000000 #define STM32_SPI3_RX_DMA_CHN 0x00000000
@ -1389,7 +1391,7 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S TRUE #define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX FALSE #define STM32_SPI1_I2S_FULLDUPLEX TRUE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 2)) STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000303 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@ -1418,7 +1420,7 @@
#define STM32_HAS_SPI4 TRUE #define STM32_HAS_SPI4 TRUE
#define STM32_SPI4_SUPPORTS_I2S TRUE #define STM32_SPI4_SUPPORTS_I2S TRUE
#define STM32_SPI4_I2S_FULLDUPLEX FALSE #define STM32_SPI4_I2S_FULLDUPLEX TRUE
#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 3) |\
STM32_DMA_STREAM_ID_MSK(2, 4)) STM32_DMA_STREAM_ID_MSK(2, 4))
@ -1429,7 +1431,7 @@
#define STM32_HAS_SPI5 TRUE #define STM32_HAS_SPI5 TRUE
#define STM32_SPI5_SUPPORTS_I2S TRUE #define STM32_SPI5_SUPPORTS_I2S TRUE
#define STM32_SPI5_I2S_FULLDUPLEX FALSE #define STM32_SPI5_I2S_FULLDUPLEX TRUE
#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
STM32_DMA_STREAM_ID_MSK(2, 5)) STM32_DMA_STREAM_ID_MSK(2, 5))
#define STM32_SPI5_RX_DMA_CHN 0x00702000 #define STM32_SPI5_RX_DMA_CHN 0x00702000
@ -1761,7 +1763,8 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX TRUE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 2)) STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000303 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@ -1788,7 +1791,8 @@
#define STM32_SPI3_TX_DMA_CHN 0x00000000 #define STM32_SPI3_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI4 TRUE #define STM32_HAS_SPI4 TRUE
#define STM32_SPI4_SUPPORTS_I2S FALSE #define STM32_SPI4_SUPPORTS_I2S TRUE
#define STM32_SPI4_I2S_FULLDUPLEX TRUE
#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 3) |\ STM32_DMA_STREAM_ID_MSK(2, 3) |\
STM32_DMA_STREAM_ID_MSK(2, 4)) STM32_DMA_STREAM_ID_MSK(2, 4))
@ -1798,7 +1802,8 @@
#define STM32_SPI4_TX_DMA_CHN 0x00050040 #define STM32_SPI4_TX_DMA_CHN 0x00050040
#define STM32_HAS_SPI5 TRUE #define STM32_HAS_SPI5 TRUE
#define STM32_SPI5_SUPPORTS_I2S FALSE #define STM32_SPI5_SUPPORTS_I2S TRUE
#define STM32_SPI5_I2S_FULLDUPLEX TRUE
#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
STM32_DMA_STREAM_ID_MSK(2, 5)) STM32_DMA_STREAM_ID_MSK(2, 5))
#define STM32_SPI5_RX_DMA_CHN 0x00702000 #define STM32_SPI5_RX_DMA_CHN 0x00702000
@ -2087,7 +2092,8 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX TRUE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 2)) STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000303 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@ -2114,7 +2120,8 @@
#define STM32_SPI3_TX_DMA_CHN 0x00000000 #define STM32_SPI3_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI4 TRUE #define STM32_HAS_SPI4 TRUE
#define STM32_SPI4_SUPPORTS_I2S FALSE #define STM32_SPI4_SUPPORTS_I2S TRUE
#define STM32_SPI4_I2S_FULLDUPLEX TRUE
#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 3)) STM32_DMA_STREAM_ID_MSK(2, 3))
#define STM32_SPI4_RX_DMA_CHN 0x00005004 #define STM32_SPI4_RX_DMA_CHN 0x00005004
@ -2123,7 +2130,8 @@
#define STM32_SPI4_TX_DMA_CHN 0x00050040 #define STM32_SPI4_TX_DMA_CHN 0x00050040
#define STM32_HAS_SPI5 TRUE #define STM32_HAS_SPI5 TRUE
#define STM32_SPI5_SUPPORTS_I2S FALSE #define STM32_SPI5_SUPPORTS_I2S TRUE
#define STM32_SPI5_I2S_FULLDUPLEX TRUE
#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
STM32_DMA_STREAM_ID_MSK(2, 5)) STM32_DMA_STREAM_ID_MSK(2, 5))
#define STM32_SPI5_RX_DMA_CHN 0x00702000 #define STM32_SPI5_RX_DMA_CHN 0x00702000
@ -2372,7 +2380,7 @@
#define STM32_HAS_I2C3 FALSE #define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE #define STM32_HAS_I2C4 TRUE
#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) |\ #define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) |\
STM32_DMA_STREAM_ID_MSK(1, 3)) STM32_DMA_STREAM_ID_MSK(1, 3))
#define STM32_I2C4_RX_DMA_CHN 0x00002007 #define STM32_I2C4_RX_DMA_CHN 0x00002007
@ -2388,7 +2396,8 @@
/* SPI attributes.*/ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_SUPPORTS_I2S TRUE
#define STM32_SPI1_I2S_FULLDUPLEX TRUE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ #define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 2)) STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000303 #define STM32_SPI1_RX_DMA_CHN 0x00000303
@ -2406,6 +2415,7 @@
#define STM32_HAS_SPI5 TRUE #define STM32_HAS_SPI5 TRUE
#define STM32_SPI5_SUPPORTS_I2S TRUE #define STM32_SPI5_SUPPORTS_I2S TRUE
#define STM32_SPI5_I2S_FULLDUPLEX TRUE
#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
STM32_DMA_STREAM_ID_MSK(2, 5)) STM32_DMA_STREAM_ID_MSK(2, 5))
#define STM32_SPI5_RX_DMA_CHN 0x00702000 #define STM32_SPI5_RX_DMA_CHN 0x00702000

1
readme.txt
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@ -74,6 +74,7 @@
***************************************************************************** *****************************************************************************
*** 20.3.3 *** *** 20.3.3 ***
- FIX: Fixed I2S-related problems in STM32F4xx registry (bug #1124).
- FIX: Fixed incorrect STM32 iWDG initialization in windowed mode (bug #1122). - FIX: Fixed incorrect STM32 iWDG initialization in windowed mode (bug #1122).
- FIX: Fixed ignored HSIDIV setting on STM32G0xx (bug #1121) - FIX: Fixed ignored HSIDIV setting on STM32G0xx (bug #1121)