Renamed r13 context field in sp (ARM ports). Extended the priorities range from 127 to 255.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8921 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -247,7 +247,7 @@ struct port_intctx {
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* at context switch time.
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* at context switch time.
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*/
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*/
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struct port_context {
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struct port_context {
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struct port_intctx *r13;
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struct port_intctx *sp;
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};
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};
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/*===========================================================================*/
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/*===========================================================================*/
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@ -260,11 +260,11 @@ struct port_context {
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* by an @p port_intctx structure.
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* by an @p port_intctx structure.
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*/
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*/
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#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
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#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
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(tp)->ctx.r13 = (struct port_intctx *)((uint8_t *)(wtop) - \
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(tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \
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sizeof (struct port_intctx)); \
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sizeof (struct port_intctx)); \
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(tp)->ctx.r13->r4 = (regarm_t)(pf); \
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(tp)->ctx.sp->r4 = (regarm_t)(pf); \
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(tp)->ctx.r13->r5 = (regarm_t)(arg); \
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(tp)->ctx.sp->r5 = (regarm_t)(arg); \
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(tp)->ctx.r13->lr = (regarm_t)(_port_thread_start); \
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(tp)->ctx.sp->lr = (regarm_t)(_port_thread_start); \
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}
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}
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/**
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/**
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@ -135,7 +135,7 @@ struct port_intctx {};
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* at context switch time.
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* at context switch time.
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*/
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*/
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struct port_context {
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struct port_context {
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struct port_intctx *r13;
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struct port_intctx *sp;
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};
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};
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#endif /* !defined(_FROM_ASM_) */
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#endif /* !defined(_FROM_ASM_) */
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@ -207,11 +207,11 @@ struct port_intctx {
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* by an @p port_intctx structure.
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* by an @p port_intctx structure.
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*/
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*/
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#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
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#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
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(tp)->ctx.r13 = (struct port_intctx *)((uint8_t *)(wtop) - \
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(tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \
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sizeof (struct port_intctx)); \
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sizeof (struct port_intctx)); \
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(tp)->ctx.r13->r4 = (regarm_t)(pf); \
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(tp)->ctx.sp->r4 = (regarm_t)(pf); \
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(tp)->ctx.r13->r5 = (regarm_t)(arg); \
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(tp)->ctx.sp->r5 = (regarm_t)(arg); \
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(tp)->ctx.r13->lr = (regarm_t)_port_thread_start; \
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(tp)->ctx.sp->lr = (regarm_t)_port_thread_start; \
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}
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}
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/**
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/**
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@ -363,11 +363,11 @@ struct port_intctx {
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* by an @p port_intctx structure.
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* by an @p port_intctx structure.
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*/
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*/
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#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
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#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
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(tp)->ctx.r13 = (struct port_intctx *)((uint8_t *)(wtop) - \
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(tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \
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sizeof (struct port_intctx)); \
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sizeof (struct port_intctx)); \
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(tp)->ctx.r13->r4 = (regarm_t)(pf); \
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(tp)->ctx.sp->r4 = (regarm_t)(pf); \
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(tp)->ctx.r13->r5 = (regarm_t)(arg); \
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(tp)->ctx.sp->r5 = (regarm_t)(arg); \
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(tp)->ctx.r13->lr = (regarm_t)_port_thread_start; \
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(tp)->ctx.sp->lr = (regarm_t)_port_thread_start; \
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}
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}
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/**
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/**
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@ -51,9 +51,8 @@
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priority. */
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priority. */
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#define IDLEPRIO (tprio_t)1 /**< @brief Idle priority. */
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#define IDLEPRIO (tprio_t)1 /**< @brief Idle priority. */
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#define LOWPRIO (tprio_t)2 /**< @brief Lowest priority. */
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#define LOWPRIO (tprio_t)2 /**< @brief Lowest priority. */
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#define NORMALPRIO (tprio_t)64 /**< @brief Normal priority. */
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#define NORMALPRIO (tprio_t)128 /**< @brief Normal priority. */
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#define HIGHPRIO (tprio_t)127 /**< @brief Highest priority. */
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#define HIGHPRIO (tprio_t)255 /**< @brief Highest priority. */
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#define ABSPRIO (tprio_t)255 /**< @brief Greatest priority. */
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/** @} */
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/** @} */
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/**
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/**
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@ -148,7 +148,7 @@ static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) {
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tp = chRegFirstThread();
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tp = chRegFirstThread();
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do {
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do {
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chprintf(chp, "%08lx %08lx %08lx %4lu %9s %12s\r\n",
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chprintf(chp, "%08lx %08lx %08lx %4lu %9s %12s\r\n",
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(uint32_t)tp->stklimit, (uint32_t)tp->ctx.r13, (uint32_t)tp,
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(uint32_t)tp->stklimit, (uint32_t)tp->ctx.sp, (uint32_t)tp,
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(uint32_t)tp->prio, states[tp->state],
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(uint32_t)tp->prio, states[tp->state],
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tp->name == NULL ? "" : tp->name);
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tp->name == NULL ? "" : tp->name);
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tp = chRegNextThread(tp);
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tp = chRegNextThread(tp);
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@ -1,90 +0,0 @@
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******************************************************************************
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*** ChibiOS 16.1.0 Release Notes. ***
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******************************************************************************
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ChibiOS 16.1.0 is composed of several independent but inter-operable
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sub-projects: RT, NIL, HAL.
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*** ChibiOS 16.1.0 highlighs ****
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This release has been developed with focus mainly on the HAL subsystem and
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general STM32 support. RT and NIL received minor bug fixes that have also
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been back-ported to previous stable branches.
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*** ChibiOS 16.1.0 general improvements ***
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- ChibiOS release version number redefined as <year>.<month>.<patch> in order
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to not confuse release version numbers with products version numbers.
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- Improved ARMCMx GCC rules.ld supporting multiple RAM regions. It is now
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possible to assign stacks, data, bss, etc ot any of the defined RAM regions.
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- Added capability to allocate initialized, zeroed and not initialized data
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to any of the defined RAM regions.
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*** What's new in RT 3.1.0 ***
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- Support for Cortex-M7.
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- Added new function chVTGetTimersStateI() returning the state of the
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timers list. This is useful to assess if it is convenient to transition
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to lower power modes.
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- Added CodeWarrior compiler support to the e200 port.
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- Minor bugs fixed.
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*** What's new in HAL 4.0.0 ***
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- New watchdog (WDG) driver.
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- Added support for STM32L0xx, STM32L4xx, STM32F7xx, STM32F446, STM32F030xC,
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STM32F070x6, STM32F070xB, STM32F091xC, STM32F098xx devices.
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- Improved USB driver.
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- Modified the driver to have a separate USB_SUSPENDED state, this
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allows the application to detect if the USB is communicating or if
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it is disconnected or powered down.
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- Added synchronous API.
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- Removed queued API.
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- Improved USB support for STM32 USBv1, OTGv1.
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- Isochronous support for STM32 USBv1, OTGv1.
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- STM32 USBv1/OTGv1 buffers and queues do not more require to be aligned in
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position and size.
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- Improved Serial-USB driver.
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- New buffers queue object.
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- Modified the driver to reject write/read attempts if the
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underlying USB is not in active state. In case of disconnection the
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SDU driver broadcasts a CHN_DISCONNECTED event.
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- Improved CAN driver.
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- Better errors reporting for STM32 CANv1.
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- Improved UART driver.
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- Added synchronous API.
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- Improved PAL driver.
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- Added "lines" handling to PAL driver, lines are identifiers of both
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ports and pins encoded in a single value. Added a set of macros
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operating on lines.
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- Added GPIOv3 driver for STM32L4xx.
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- I2S support added for STM32 SPIv2 peripheral.
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- Board files an demos for STM32 Nucleo32 boards.
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- Added latest CMSIS headers for all STM32 families.
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- STM32 DMA drivers have been unified and consolidated in DMAv1 and DMAv2.
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- DMA channels selection now supported on all devices with the new mux
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mechanism.
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- Added serial driver support for USART 3..6 on STM32F030xC devices.
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- Added support for differential mode to the STM32F3xx ADC driver.
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- STM32 GPT, ICU and PWM driver enhancements. Now it is possible to
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suppress default ISRs by defining STM32_TIMx_SUPPRESS_ISR.
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The application is now able to define custom handlers if required
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or simply save space if the driver callbacks are not used.
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Now the functions xxx_lld_serve_interrupts() have global scope, this
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way custom ISRs can call them from outside the driver module.
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- Added TIM units use cross-check in STM32 GPT, ICU, PWM and ST drivers,
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now use collisions are explicitly reported.
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- Added support for I2C3 and I2C4 to the STM32 I2Cv2 I2C driver.
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- Added support for SPI4...SPI6 to the STM32 SPIv2 SPI driver.
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- Added support for UART4...UART8 to the STM32 UARTv2 UART driver.
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- Added support for UART7 and UART8,LPUART1 to the STM32 UARTv2 serial
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driver.
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- New STM32 ADCv3 driver supporting middle STM32 devices (F3, L4).
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- New STM32 ADCv2 driver supporting large STM32 devices (F2, F4, F7).
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- New STM32 ADCv1 driver supporting small STM32 devices (F0, L0).
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- Introduced support for TIM21 and TIM22 in STM32 ST driver.
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*** What's new in NIL 1.1.0 ***
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- Support for Cortex-M7.
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- Minor bugs fixed.
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@ -0,0 +1,44 @@
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******************************************************************************
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*** ChibiOS next Release Notes. ***
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******************************************************************************
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ChibiOS next is composed of several independent but inter-operable
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sub-projects: RT, NIL, HAL.
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*** ChibiOS next highlights ****
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This release is focused on RTOS general improvements, both RT and NIL received
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a series of important new features.
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*** ChibiOS next general improvements ***
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- Rationalized source tree to reduce code duplication.
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- Shared RTOS components, now allocators, mailboxes and binary semaphores
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are usable by both RT and NIL.
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- Shared ports architecture. Now RTOS ports work for both RT and NIL, no
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more duplication.
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- Enhanced shell.
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*** What's new in RT 4.0.0 ***
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- Common ports architecture.
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- Ability to use the new shared RTOS components.
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- Enhanced trace buffer, it is able to store events regarding not just threads
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but also IRQs, halts and user events.
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- Simplified the dynamic threading model, now it is the thread creator
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responsible for memory release, the references counter has been removed
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and the code is much simpler.
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- New threading API, now creating static threads is even faster.
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- Saved space in thread_t structure.
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- Extended priority range to 1..255.
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- Experimental NASA OSAL implementation.
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*** What's new in HAL 4.1.0 ***
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*** What's new in NIL 2.0.0 ***
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- Common ports architecture.
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- Ability to use the new shared RTOS components.
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- State checker.
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- Parameter checks.
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