git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13474 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
efa898eddf
commit
04ae78bb85
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file RCCv1/stm32_ahb.inc
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* @brief Shared AHB clock handler.
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*
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* @addtogroup STM32_AHB_HANDLER
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* @{
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*/
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @name HPRE field bits definitions
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* @{
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*/
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#define STM32_HPRE_MASK (15 << 4) /**< HPRE field mask. */
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#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
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#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
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#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
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#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
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#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
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#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
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#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
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#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
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#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* Registry checks for robustness.*/
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/* Checks on configurations.*/
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#if !defined(STM32_HPRE)
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#error "STM32_HPRE not defined in mcuconf.h"
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#endif
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/* Check on limits.*/
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#if !defined(STM32_SYSCLK_MAX)
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#error "STM32_SYSCLK_MAX not defined in hal_lld.h"
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#endif
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/* Input checks.*/
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#if !defined(STM32_SYSCLK)
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#error "STM32_SYSCLK not defined in hal_lld.h"
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#endif
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/**
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* @brief AHB frequency.
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*/
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#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
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#define STM32_HCLK (STM32_SYSCLK / 1)
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#elif STM32_HPRE == STM32_HPRE_DIV2
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#define STM32_HCLK (STM32_SYSCLK / 2)
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#elif STM32_HPRE == STM32_HPRE_DIV4
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#define STM32_HCLK (STM32_SYSCLK / 4)
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#elif STM32_HPRE == STM32_HPRE_DIV8
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#define STM32_HCLK (STM32_SYSCLK / 8)
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#elif STM32_HPRE == STM32_HPRE_DIV16
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#define STM32_HCLK (STM32_SYSCLK / 16)
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#elif STM32_HPRE == STM32_HPRE_DIV64
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#define STM32_HCLK (STM32_SYSCLK / 64)
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#elif STM32_HPRE == STM32_HPRE_DIV128
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#define STM32_HCLK (STM32_SYSCLK / 128)
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#elif STM32_HPRE == STM32_HPRE_DIV256
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#define STM32_HCLK (STM32_SYSCLK / 256)
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#elif STM32_HPRE == STM32_HPRE_DIV512
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#define STM32_HCLK (STM32_SYSCLK / 512)
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#else
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#error "invalid STM32_HPRE value specified"
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#endif
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/*
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* SYSCLK frequency check.
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*/
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#if STM32_SYSCLK > STM32_SYSCLK_MAX
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#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
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#endif
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/*
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* HCLK frequency check.
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*/
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#if STM32_HCLK > STM32_SYSCLK_MAX
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#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/** @} */
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@ -0,0 +1,111 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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||||||
|
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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||||||
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file RCCv1/stm32_apb1.inc
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* @brief Shared APB1 clock handler.
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*
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* @addtogroup STM32_APB1_HANDLER
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* @{
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*/
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @name PPRE1 field bits definitions
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* @{
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*/
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#define STM32_PPRE1_MASK (7 << 8) /**< PPRE1 field mask. */
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#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
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#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
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#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
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#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
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#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* Registry checks for robustness.*/
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/* Checks on configurations.*/
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#if !defined(STM32_PPRE1)
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#error "STM32_PPRE1 not defined in mcuconf.h"
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#endif
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/* Check on limits.*/
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#if !defined(STM32_PCLK1_MAX)
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#error "STM32_PCLK1_MAX not defined in hal_lld.h"
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#endif
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/* Input checks.*/
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#if !defined(STM32_HCLK)
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#error "STM32_HCLK not defined in hal_lld.h"
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#endif
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/**
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* @brief APB1 frequency.
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*/
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#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
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#define STM32_PCLK1 (STM32_HCLK / 1)
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#elif STM32_PPRE1 == STM32_PPRE1_DIV2
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#define STM32_PCLK1 (STM32_HCLK / 2)
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#elif STM32_PPRE1 == STM32_PPRE1_DIV4
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#define STM32_PCLK1 (STM32_HCLK / 4)
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#elif STM32_PPRE1 == STM32_PPRE1_DIV8
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#define STM32_PCLK1 (STM32_HCLK / 8)
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#elif STM32_PPRE1 == STM32_PPRE1_DIV16
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#define STM32_PCLK1 (STM32_HCLK / 16)
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#else
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#error "invalid STM32_PPRE1 value specified"
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#endif
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/*
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* APB1 frequency check.
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*/
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#if STM32_PCLK1 > STM32_PCLK1_MAX
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#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/** @} */
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@ -0,0 +1,111 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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||||||
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file RCCv1/stm32_apb2.inc
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* @brief Shared APB2 clock handler.
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*
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* @addtogroup STM32_APB2_HANDLER
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* @{
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*/
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @name PPRE1 field bits definitions
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* @{
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*/
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#define STM32_PPRE2_MASK (7 << 11) /**< PPRE2 field mask. */
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#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
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#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
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#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
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#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
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#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* Registry checks for robustness.*/
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/* Checks on configurations.*/
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#if !defined(STM32_PPRE1)
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#error "STM32_PPRE1 not defined in mcuconf.h"
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#endif
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/* Check on limits.*/
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#if !defined(STM32_PCLK1_MAX)
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#error "STM32_PCLK1_MAX not defined in hal_lld.h"
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#endif
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/* Input checks.*/
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#if !defined(STM32_HCLK)
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#error "STM32_HCLK not defined in hal_lld.h"
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#endif
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/**
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* @brief APB2 frequency.
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*/
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#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
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#define STM32_PCLK2 (STM32_HCLK / 1)
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#elif STM32_PPRE2 == STM32_PPRE2_DIV2
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#define STM32_PCLK2 (STM32_HCLK / 2)
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#elif STM32_PPRE2 == STM32_PPRE2_DIV4
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#define STM32_PCLK2 (STM32_HCLK / 4)
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#elif STM32_PPRE2 == STM32_PPRE2_DIV8
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#define STM32_PCLK2 (STM32_HCLK / 8)
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#elif STM32_PPRE2 == STM32_PPRE2_DIV16
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#define STM32_PCLK2 (STM32_HCLK / 16)
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#else
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#error "invalid STM32_PPRE2 value specified"
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#endif
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/*
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* APB2 frequency check.
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*/
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#if STM32_PCLK2 > STM32_PCLK2_MAX
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#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/** @} */
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@ -26,6 +26,11 @@
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/* Driver local definitions. */
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/**
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* @brief HSI16 clock frequency.
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*/
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#define STM32_HSI16CLK 16000000
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -26,6 +26,11 @@
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/* Driver local definitions. */
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/**
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* @brief HSI48 clock frequency.
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*/
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#define STM32_HSI48CLK 48000000
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -26,6 +26,11 @@
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/* Driver local definitions. */
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/**
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* @brief LSI clock frequency.
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*/
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#define STM32_LSICLK 32000
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/* Derived constants and error checks. */
|
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/*===========================================================================*/
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/*===========================================================================*/
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@ -45,6 +45,17 @@
|
||||||
#define STM32_MSIRANGE_48M (11 << 4) /**< 48MHz nominal. */
|
#define STM32_MSIRANGE_48M (11 << 4) /**< 48MHz nominal. */
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name RCC_CSR register bits definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define STM32_MSISRANGE_MASK (15 << 8) /**< MSISRANGE field mask. */
|
||||||
|
#define STM32_MSISRANGE_1M (4 << 8) /**< 1MHz nominal. */
|
||||||
|
#define STM32_MSISRANGE_2M (5 << 8) /**< 2MHz nominal. */
|
||||||
|
#define STM32_MSISRANGE_4M (6 << 8) /**< 4MHz nominal. */
|
||||||
|
#define STM32_MSISRANGE_8M (7 << 8) /**< 8MHz nominal. */
|
||||||
|
/** @} */
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Derived constants and error checks. */
|
/* Derived constants and error checks. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
|
||||||
|
|
@ -151,8 +151,7 @@ void stm32_clock_init(void) {
|
||||||
flash_ws_init(STM32_MSI_FLASHBITS);
|
flash_ws_init(STM32_MSI_FLASHBITS);
|
||||||
|
|
||||||
/* Clocks setup.*/
|
/* Clocks setup.*/
|
||||||
lse_init(); /* LSE before MSI because MSIPLL
|
lse_init(); /* LSE first because MSIPLL. */
|
||||||
uses LSE.*/
|
|
||||||
msi_init();
|
msi_init();
|
||||||
lsi_init();
|
lsi_init();
|
||||||
hsi16_init();
|
hsi16_init();
|
||||||
|
|
|
||||||
|
|
@ -65,15 +65,6 @@
|
||||||
#endif
|
#endif
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
/**
|
|
||||||
* @name Internal clock sources
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define STM32_HSI16CLK 16000000 /**< 16MHz internal clock. */
|
|
||||||
#define STM32_HSI48CLK 48000000 /**< 48MHz internal clock. */
|
|
||||||
#define STM32_LSICLK 32000 /**< Low speed internal clock. */
|
|
||||||
/** @} */
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @name PWR_CR1 register bits definitions
|
* @name PWR_CR1 register bits definitions
|
||||||
* @{
|
* @{
|
||||||
|
|
@ -94,31 +85,6 @@
|
||||||
#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
|
#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
|
||||||
#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */
|
#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */
|
||||||
|
|
||||||
#define STM32_HPRE_MASK (15 << 4) /**< HPRE field mask. */
|
|
||||||
#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
|
|
||||||
#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
|
|
||||||
#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
|
|
||||||
#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
|
|
||||||
#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
|
|
||||||
#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
|
|
||||||
#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
|
|
||||||
#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
|
|
||||||
#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
|
|
||||||
|
|
||||||
#define STM32_PPRE1_MASK (7 << 8) /**< PPRE1 field mask. */
|
|
||||||
#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
|
|
||||||
#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
|
|
||||||
#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
|
|
||||||
#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
|
|
||||||
#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
|
|
||||||
|
|
||||||
#define STM32_PPRE2_MASK (7 << 11) /**< PPRE2 field mask. */
|
|
||||||
#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
|
|
||||||
#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
|
|
||||||
#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
|
|
||||||
#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
|
|
||||||
#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
|
|
||||||
|
|
||||||
#define STM32_STOPWUCK_MASK (1 << 15) /**< STOPWUCK field mask. */
|
#define STM32_STOPWUCK_MASK (1 << 15) /**< STOPWUCK field mask. */
|
||||||
#define STM32_STOPWUCK_MSI (0 << 15) /**< Wakeup clock is MSI. */
|
#define STM32_STOPWUCK_MSI (0 << 15) /**< Wakeup clock is MSI. */
|
||||||
#define STM32_STOPWUCK_HSI16 (1 << 15) /**< Wakeup clock is HSI16. */
|
#define STM32_STOPWUCK_HSI16 (1 << 15) /**< Wakeup clock is HSI16. */
|
||||||
|
|
@ -326,17 +292,6 @@
|
||||||
#define STM32_LSCOSEL_LSE (3 << 24) /**< LSE on LSCO pin. */
|
#define STM32_LSCOSEL_LSE (3 << 24) /**< LSE on LSCO pin. */
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
/**
|
|
||||||
* @name RCC_CSR register bits definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define STM32_MSISRANGE_MASK (15 << 8) /**< MSISRANGE field mask. */
|
|
||||||
#define STM32_MSISRANGE_1M (4 << 8) /**< 1MHz nominal. */
|
|
||||||
#define STM32_MSISRANGE_2M (5 << 8) /**< 2MHz nominal. */
|
|
||||||
#define STM32_MSISRANGE_4M (6 << 8) /**< 4MHz nominal. */
|
|
||||||
#define STM32_MSISRANGE_8M (7 << 8) /**< 8MHz nominal. */
|
|
||||||
/** @} */
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver pre-compile time settings. */
|
/* Driver pre-compile time settings. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
@ -419,29 +374,6 @@
|
||||||
#define STM32_PLLSAI2SRC STM32_PLLSAI2SRC_MSI
|
#define STM32_PLLSAI2SRC STM32_PLLSAI2SRC_MSI
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AHB prescaler value.
|
|
||||||
* @note The default value is calculated for a 120MHz system clock from
|
|
||||||
* the internal 4MHz MSI clock.
|
|
||||||
*/
|
|
||||||
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
|
|
||||||
#define STM32_HPRE STM32_HPRE_DIV1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief APB1 prescaler value.
|
|
||||||
*/
|
|
||||||
#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
|
|
||||||
#define STM32_PPRE1 STM32_PPRE1_DIV1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief APB2 prescaler value.
|
|
||||||
*/
|
|
||||||
#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
|
|
||||||
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief STOPWUCK clock setting.
|
* @brief STOPWUCK clock setting.
|
||||||
*/
|
*/
|
||||||
|
|
@ -872,10 +804,9 @@
|
||||||
#include "stm32_hse.inc"
|
#include "stm32_hse.inc"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* HSI16 related checks.
|
* Platform HSI16-related checks.
|
||||||
*/
|
*/
|
||||||
#if STM32_HSI16_ENABLED
|
#if !STM32_HSI16_ENABLED
|
||||||
#else /* !STM32_HSI16_ENABLED */
|
|
||||||
|
|
||||||
#if STM32_SW == STM32_SW_HSI16
|
#if STM32_SW == STM32_SW_HSI16
|
||||||
#error "HSI16 not enabled, required by STM32_SW"
|
#error "HSI16 not enabled, required by STM32_SW"
|
||||||
|
|
@ -997,10 +928,9 @@
|
||||||
#endif /* !STM32_HSI48_ENABLED */
|
#endif /* !STM32_HSI48_ENABLED */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* HSE related checks.
|
* Platform HSE-related checks.
|
||||||
*/
|
*/
|
||||||
#if STM32_HSE_ENABLED
|
#if !STM32_HSE_ENABLED
|
||||||
#else /* !STM32_HSE_ENABLED */
|
|
||||||
|
|
||||||
#if STM32_SW == STM32_SW_HSE
|
#if STM32_SW == STM32_SW_HSE
|
||||||
#error "HSE not enabled, required by STM32_SW"
|
#error "HSE not enabled, required by STM32_SW"
|
||||||
|
|
@ -1057,10 +987,9 @@
|
||||||
#endif /* !STM32_HSE_ENABLED */
|
#endif /* !STM32_HSE_ENABLED */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* LSI related checks.
|
* Platform LSI-related checks.
|
||||||
*/
|
*/
|
||||||
#if STM32_LSI_ENABLED
|
#if !STM32_LSI_ENABLED
|
||||||
#else /* !STM32_LSI_ENABLED */
|
|
||||||
|
|
||||||
#if STM32_RTCSEL == STM32_RTCSEL_LSI
|
#if STM32_RTCSEL == STM32_RTCSEL_LSI
|
||||||
#error "LSI not enabled, required by STM32_RTCSEL"
|
#error "LSI not enabled, required by STM32_RTCSEL"
|
||||||
|
|
@ -1077,7 +1006,7 @@
|
||||||
#endif /* !STM32_LSI_ENABLED */
|
#endif /* !STM32_LSI_ENABLED */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* LSE related checks.
|
* Platform LSE-related checks.
|
||||||
*/
|
*/
|
||||||
#if !STM32_LSE_ENABLED
|
#if !STM32_LSE_ENABLED
|
||||||
#if STM32_RTCSEL == STM32_RTCSEL_LSE
|
#if STM32_RTCSEL == STM32_RTCSEL_LSE
|
||||||
|
|
@ -1312,109 +1241,10 @@
|
||||||
#error "invalid STM32_SW value specified"
|
#error "invalid STM32_SW value specified"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Check on the system clock.*/
|
/* Bus handlers.*/
|
||||||
#if STM32_SYSCLK > STM32_SYSCLK_MAX
|
#include "stm32_ahb.inc"
|
||||||
#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
|
#include "stm32_apb1.inc"
|
||||||
#endif
|
#include "stm32_apb2.inc"
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AHB frequency.
|
|
||||||
*/
|
|
||||||
#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
|
|
||||||
#define STM32_HCLK (STM32_SYSCLK / 1)
|
|
||||||
|
|
||||||
#elif STM32_HPRE == STM32_HPRE_DIV2
|
|
||||||
#define STM32_HCLK (STM32_SYSCLK / 2)
|
|
||||||
|
|
||||||
#elif STM32_HPRE == STM32_HPRE_DIV4
|
|
||||||
#define STM32_HCLK (STM32_SYSCLK / 4)
|
|
||||||
|
|
||||||
#elif STM32_HPRE == STM32_HPRE_DIV8
|
|
||||||
#define STM32_HCLK (STM32_SYSCLK / 8)
|
|
||||||
|
|
||||||
#elif STM32_HPRE == STM32_HPRE_DIV16
|
|
||||||
#define STM32_HCLK (STM32_SYSCLK / 16)
|
|
||||||
|
|
||||||
#elif STM32_HPRE == STM32_HPRE_DIV64
|
|
||||||
#define STM32_HCLK (STM32_SYSCLK / 64)
|
|
||||||
|
|
||||||
#elif STM32_HPRE == STM32_HPRE_DIV128
|
|
||||||
#define STM32_HCLK (STM32_SYSCLK / 128)
|
|
||||||
|
|
||||||
#elif STM32_HPRE == STM32_HPRE_DIV256
|
|
||||||
#define STM32_HCLK (STM32_SYSCLK / 256)
|
|
||||||
|
|
||||||
#elif STM32_HPRE == STM32_HPRE_DIV512
|
|
||||||
#define STM32_HCLK (STM32_SYSCLK / 512)
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error "invalid STM32_HPRE value specified"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* AHB frequency check.
|
|
||||||
*/
|
|
||||||
#if STM32_HCLK > STM32_SYSCLK_MAX
|
|
||||||
#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief APB1 frequency.
|
|
||||||
*/
|
|
||||||
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
|
|
||||||
#define STM32_PCLK1 (STM32_HCLK / 1)
|
|
||||||
|
|
||||||
#elif STM32_PPRE1 == STM32_PPRE1_DIV2
|
|
||||||
#define STM32_PCLK1 (STM32_HCLK / 2)
|
|
||||||
|
|
||||||
#elif STM32_PPRE1 == STM32_PPRE1_DIV4
|
|
||||||
#define STM32_PCLK1 (STM32_HCLK / 4)
|
|
||||||
|
|
||||||
#elif STM32_PPRE1 == STM32_PPRE1_DIV8
|
|
||||||
#define STM32_PCLK1 (STM32_HCLK / 8)
|
|
||||||
|
|
||||||
#elif STM32_PPRE1 == STM32_PPRE1_DIV16
|
|
||||||
#define STM32_PCLK1 (STM32_HCLK / 16)
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error "invalid STM32_PPRE1 value specified"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* APB1 frequency check.
|
|
||||||
*/
|
|
||||||
#if STM32_PCLK1 > STM32_PCLK1_MAX
|
|
||||||
#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief APB2 frequency.
|
|
||||||
*/
|
|
||||||
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
|
||||||
#define STM32_PCLK2 (STM32_HCLK / 1)
|
|
||||||
|
|
||||||
#elif STM32_PPRE2 == STM32_PPRE2_DIV2
|
|
||||||
#define STM32_PCLK2 (STM32_HCLK / 2)
|
|
||||||
|
|
||||||
#elif STM32_PPRE2 == STM32_PPRE2_DIV4
|
|
||||||
#define STM32_PCLK2 (STM32_HCLK / 4)
|
|
||||||
|
|
||||||
#elif STM32_PPRE2 == STM32_PPRE2_DIV8
|
|
||||||
#define STM32_PCLK2 (STM32_HCLK / 8)
|
|
||||||
|
|
||||||
#elif STM32_PPRE2 == STM32_PPRE2_DIV16
|
|
||||||
#define STM32_PCLK2 (STM32_HCLK / 16)
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error "invalid STM32_PPRE2 value specified"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* APB2 frequency check.
|
|
||||||
*/
|
|
||||||
#if STM32_PCLK2 > STM32_PCLK2_MAX
|
|
||||||
#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief MCO divider clock frequency.
|
* @brief MCO divider clock frequency.
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue