Fixed RTC on newer STM32F7 devices.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9888 35acf78f-673a-0410-8e92-d51de3d6d3f4

os/hal/ports/STM32/STM32F4xx/stm32_rcc.h

@@ -469,7 +469,6 @@
 #define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
 /** @} */
 
-
 /**
  * @name    CAN peripherals specific RCC operations
  * @{

os/hal/ports/STM32/STM32F7xx/hal_lld.c

@@ -120,9 +120,6 @@ void hal_lld_init(void) {
   rccResetAPB1(~RCC_APB1RSTR_PWRRST);
   rccResetAPB2(~0);
 
-  /* PWR clock enabled.*/
-  rccEnablePWRInterface(FALSE);
-
   /* Initializes the backup domain.*/
   hal_lld_backup_domain_init();
 
@@ -162,8 +159,15 @@ void hal_lld_init(void) {
 void stm32_clock_init(void) {
 
 #if !STM32_NO_INIT
-  /* PWR clock enable.*/
+  /* PWR clock enabled.*/
+#if defined(HAL_USE_RTC) &&                                                 \
+    (defined(STM32F765xx) || defined(STM32F767xx) ||                        \
+     defined(STM32F769xx) || defined(STM32F777xx) ||                        \
+     defined (STM32F779xx))
+  RCC->APB1ENR = RCC_APB1ENR_PWREN | RCC_APB1ENR_RTCEN;
+#else
   RCC->APB1ENR = RCC_APB1ENR_PWREN;
+#endif
 
   /* PWR initialization.*/
   PWR->CR1 = STM32_VOS;

os/hal/ports/STM32/STM32F7xx/stm32_rcc.h

@@ -469,7 +469,6 @@
 #define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
 /** @} */
 
-
 /**
  * @name    CAN peripherals specific RCC operations
  * @{

os/hal/ports/STM32/STM32L4xx/stm32_rcc.h

@@ -413,7 +413,6 @@
 #define rccResetPWRInterface() rccResetAPB1R1(RCC_APB1RSTR1_PWRRST)
 /** @} */
 
-
 /**
  * @name    CAN peripherals specific RCC operations
  * @{