Adding hal_ldd files from master
This commit is contained in:
Fabien Poussin
parent
5114f073b6
commit
0f416078cc
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@ -1,5 +1,5 @@
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -114,9 +114,12 @@ static void hal_lld_backup_domain_init(void) {
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void hal_lld_init(void) {
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/* Reset of all peripherals. AHB3 is not reseted because it could have
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been initialized in the board initialization file (board.c).*/
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been initialized in the board initialization file (board.c) and AHB2 is not
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present in STM32F410. */
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rccResetAHB1(~0);
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#if !defined(STM32F410xx)
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rccResetAHB2(~0);
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#endif
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rccResetAPB1(~RCC_APB1RSTR_PWRRST);
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rccResetAPB2(~0);
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@ -147,7 +150,11 @@ void stm32_clock_init(void) {
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#if !STM32_NO_INIT
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/* PWR clock enable.*/
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#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR_RTCAPBEN)
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RCC->APB1ENR = RCC_APB1ENR_PWREN | RCC_APB1ENR_RTCAPBEN;
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#else
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RCC->APB1ENR = RCC_APB1ENR_PWREN;
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#endif
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/* PWR initialization.*/
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#if defined(STM32F4XX) || defined(__DOXYGEN__)
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@ -173,7 +180,7 @@ void stm32_clock_init(void) {
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/* Registers finally cleared to reset values.*/
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RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
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RCC->CFGR = 0; /* CFGR reset value. */
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#if STM32_HSE_ENABLED
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/* HSE activation.*/
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#if defined(STM32_HSE_BYPASS)
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@ -220,35 +227,73 @@ void stm32_clock_init(void) {
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/* Waiting for PLL lock.*/
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while (!(RCC->CR & RCC_CR_PLLRDY))
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;
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#endif /* STM32_OVERDRIVE_REQUIRED */
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#endif /* STM32_ACTIVATE_PLL */
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#if STM32_ACTIVATE_PLLI2S
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/* PLLI2S activation.*/
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RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;
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RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN | STM32_PLLI2SP |
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STM32_PLLI2SQ | STM32_PLLI2SM;
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RCC->CR |= RCC_CR_PLLI2SON;
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/* Waiting for PLL lock.*/
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while (!(RCC->CR & RCC_CR_PLLI2SRDY))
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;
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#endif
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#endif /* STM32_ACTIVATE_PLLI2S */
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#if STM32_ACTIVATE_PLLSAI
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/* PLLSAI activation.*/
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RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ;
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RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIN | STM32_PLLSAIP |
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STM32_PLLSAIQ | STM32_PLLSAIM;
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RCC->CR |= RCC_CR_PLLSAION;
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/* Waiting for PLL lock.*/
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while (!(RCC->CR & RCC_CR_PLLSAIRDY))
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;
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#endif
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#endif /* STM32_ACTIVATE_PLLSAI */
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/* Other clock-related settings (dividers, MCO etc).*/
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RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
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STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
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STM32_HPRE;
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#if defined(STM32F446xx)
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/* DCKCFGR register initialization, note, must take care of the _OFF
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pseudo settings.*/
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{
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uint32_t dckcfgr = 0;
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#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
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dckcfgr |= STM32_SAI2SEL;
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#endif
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#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
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dckcfgr |= STM32_SAI1SEL;
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#endif
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#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
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dckcfgr |= STM32_PLLSAIDIVR;
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#endif
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RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ;
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}
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RCC->DCKCFGR2 = STM32_CK48MSEL;
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#elif defined(STM32F469xx) || defined(STM32F479xx)
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/* DCKCFGR register initialization, note, must take care of the _OFF
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pseudo settings.*/
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{
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uint32_t dckcfgr = 0;
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#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
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dckcfgr |= STM32_SAI2SEL;
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#endif
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#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
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dckcfgr |= STM32_SAI1SEL;
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#endif
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#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
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dckcfgr |= STM32_PLLSAIDIVR;
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#endif
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RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ |
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STM32_CK48MSEL;
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}
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#endif
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/* Flash setup.*/
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#if defined(STM32_USE_REVISION_A_FIX)
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#if !defined(STM32_REMOVE_REVISION_A_FIX)
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/* Some old revisions of F4x MCUs randomly crashes with compiler
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optimizations enabled AND flash caches enabled. */
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if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241))
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@ -1,5 +1,5 @@
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -26,22 +26,22 @@
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* - STM32_VDD (as hundredths of Volt).
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* .
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* One of the following macros must also be defined:
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* - STM32F2XX for High-performance STM32 F-2 devices.
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* - STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx for
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* High-performance STM32 F-4 devices.
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* - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx for
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* High-performance STM32 F-4 devices.
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* - STM32F401xC, STM32F401xE for High-performance STM32 F-4 devices.
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* - STM32F411xE for High-performance STM32 F-4 devices.
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* - STM32F446xx for High-performance STM32 F-4 devices.
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* - STM32F2XX for High-performance STM32F2 devices.
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* - STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx,
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* STM32F446xx for High-performance STM32F4 devices of
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* Foundation line.
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* - STM32F401xC, STM32F401xE, STM32F410Cx, STM32F410Rx, STM32F411xE
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* for High-performance STM32F4 devices of Access line.
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* - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx, STM32F469xx,
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* STM32F479xx for High-performance STM32F4 devices of Advanced line.
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* .
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#ifndef HAL_LLD_H
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#define HAL_LLD_H
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#include "stm32_registry.h"
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@ -52,17 +52,50 @@
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS TRUE
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#define HAL_IMPLEMENTS_COUNTERS TRUE
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/**
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* @name Platform identification macros
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* @{
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*/
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#if defined(STM32F439xx) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32F439 High Performance with DSP and FPU"
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#if defined(STM32F205xx) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32F205 High Performance"
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#elif defined(STM32F446xx)
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#define PLATFORM_NAME "STM32F446 High Performance with DSP and FPU"
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#elif defined(STM32F207xx)
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#define PLATFORM_NAME "STM32F207 High Performance"
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#elif defined(STM32F215xx)
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#define PLATFORM_NAME "STM32F215 High Performance"
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#elif defined(STM32F217xx)
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#define PLATFORM_NAME "STM32F217 High Performance"
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#elif defined(STM32F401xx)
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#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU"
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#elif defined(STM32F405xx)
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#define PLATFORM_NAME "STM32F405 High Performance with DSP and FPU"
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#elif defined(STM32F407xx)
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#define PLATFORM_NAME "STM32F407 High Performance with DSP and FPU"
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#elif defined(STM32F410xx)
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#define PLATFORM_NAME "STM32F410 High Performance with DSP and FPU"
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#elif defined(STM32F411xx)
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#define PLATFORM_NAME "STM32F411 High Performance with DSP and FPU"
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#elif defined(STM32F412xx)
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#define PLATFORM_NAME "STM32F412 High Performance with DSP and FPU"
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#elif defined(STM32F415xx)
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#define PLATFORM_NAME "STM32F415 High Performance with DSP and FPU"
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#elif defined(STM32F417xx)
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#define PLATFORM_NAME "STM32F417 High Performance with DSP and FPU"
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#elif defined(STM32F427xx)
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#define PLATFORM_NAME "STM32F427 High Performance with DSP and FPU"
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#elif defined(STM32F429xx)
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#define PLATFORM_NAME "STM32F429 High Performance with DSP and FPU"
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@ -70,41 +103,17 @@
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#elif defined(STM32F437xx)
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#define PLATFORM_NAME "STM32F437 High Performance with DSP and FPU"
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#elif defined(STM32F427xx)
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#define PLATFORM_NAME "STM32F427 High Performance with DSP and FPU"
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#elif defined(STM32F439xx)
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#define PLATFORM_NAME "STM32F439 High Performance with DSP and FPU"
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#elif defined(STM32F405xx)
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#define PLATFORM_NAME "STM32F405 High Performance with DSP and FPU"
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#elif defined(STM32F446xx)
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#define PLATFORM_NAME "STM32F446 High Performance with DSP and FPU"
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#elif defined(STM32F415xx)
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#define PLATFORM_NAME "STM32F415 High Performance with DSP and FPU"
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#elif defined(STM32F469xx)
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#define PLATFORM_NAME "STM32F469 High Performance with DSP and FPU"
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#elif defined(STM32F407xx)
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#define PLATFORM_NAME "STM32F407 High Performance with DSP and FPU"
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#elif defined(STM32F417xx)
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#define PLATFORM_NAME "STM32F417 High Performance with DSP and FPU"
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#elif defined(STM32F401xC)
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#define PLATFORM_NAME "STM32F401xC High Performance with DSP and FPU"
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#elif defined(STM32F401xE)
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#define PLATFORM_NAME "STM32F401xE High Performance with DSP and FPU"
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#elif defined(STM32F411xE)
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#define PLATFORM_NAME "STM32F411xE High Performance with DSP and FPU"
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#elif defined(STM32F205xx)
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#define PLATFORM_NAME "STM32F205 High Performance"
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#elif defined(STM32F215xx)
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#define PLATFORM_NAME "STM32F215 High Performance"
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#elif defined(STM32F207xx)
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#define PLATFORM_NAME "STM32F207 High Performance"
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#elif defined(STM32F217xx)
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#define PLATFORM_NAME "STM32F217 High Performance"
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#elif defined(STM32F479xx)
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#define PLATFORM_NAME "STM32F479 High Performance with DSP and FPU"
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#else
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#error "STM32F2xx/F4xx device not specified"
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@ -117,7 +126,7 @@
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*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || \
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defined(STM32F429xx) || defined(STM32F439xx) || \
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defined(STM32F446xx) || defined(__DOXYGEN__)
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defined(STM32F469xx) || defined(STM32F479xx) || defined(__DOXYGEN__)
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/**
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* @brief Absolute maximum system clock.
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*/
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@ -188,10 +197,20 @@
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*/
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#define STM32_PLLOUT_MIN 24000000
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/**
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* @brief Maximum PLLI2S output clock frequency.
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*/
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#define STM32_PLLI2SOUT_MAX 216000000
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/**
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* @brief Maximum PLLSAI output clock frequency.
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*/
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#define STM32_PLLSAIOUT_MAX 216000000
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/**
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* @brief Maximum APB1 clock frequency.
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*/
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#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX /4)
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#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4)
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/**
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* @brief Maximum APB2 clock frequency.
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@ -204,7 +223,7 @@
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#define STM32_SPII2S_MAX 45000000
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#endif
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#if defined(STM32F40_41xxx) || defined(__DOXYGEN__)
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#if defined(STM32F40_41xxx)
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#define STM32_SYSCLK_MAX 168000000
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#define STM32_HSECLK_MAX 26000000
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#define STM32_HSECLK_BYP_MAX 50000000
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@ -224,7 +243,7 @@
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#define STM32_SPII2S_MAX 42000000
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#endif
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#if defined(STM32F401xx) || defined(__DOXYGEN__)
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#if defined(STM32F401xx)
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#define STM32_SYSCLK_MAX 84000000
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#define STM32_HSECLK_MAX 26000000
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#define STM32_HSECLK_BYP_MAX 50000000
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@ -244,7 +263,8 @@
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#define STM32_SPII2S_MAX 42000000
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#endif
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#if defined(STM32F411xx)
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#if defined(STM32F410xx) || defined(STM32F411xx) || \
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defined(STM32F412xx)
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#define STM32_SYSCLK_MAX 100000000
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#define STM32_HSECLK_MAX 26000000
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#define STM32_HSECLK_BYP_MAX 50000000
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@ -264,6 +284,28 @@
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#define STM32_SPII2S_MAX 50000000
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#endif
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#if defined(STM32F446xx)
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#define STM32_SYSCLK_MAX 180000000
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#define STM32_HSECLK_MAX 26000000
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#define STM32_HSECLK_BYP_MAX 50000000
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#define STM32_HSECLK_MIN 4000000
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#define STM32_HSECLK_BYP_MIN 1000000
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#define STM32_LSECLK_MAX 32768
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#define STM32_LSECLK_BYP_MAX 1000000
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#define STM32_LSECLK_MIN 32768
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#define STM32_PLLIN_MAX 2100000
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#define STM32_PLLIN_MIN 950000
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#define STM32_PLLVCO_MAX 432000000
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#define STM32_PLLVCO_MIN 100000000
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#define STM32_PLLOUT_MAX 180000000
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#define STM32_PLLOUT_MIN 12500000
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#define STM32_PLLI2SOUT_MAX 216000000
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#define STM32_PLLSAIOUT_MAX 216000000
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#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4)
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#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2)
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#define STM32_SPII2S_MAX 45000000
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#endif
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#if defined(STM32F2XX)
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#define STM32_SYSCLK_MAX 120000000
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#define STM32_HSECLK_MAX 26000000
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@ -395,10 +437,32 @@
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* @name RCC_PLLI2SCFGR register bits definitions
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* @{
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*/
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#define STM32_PLLI2SM_MASK (31 << 0) /**< PLLI2SM mask. */
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#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */
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#define STM32_PLLI2SP_MASK (3 << 16) /**< PLLI2SP mask. */
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#define STM32_PLLI2SP_DIV2 (0 << 16) /**< PLLI2S clock divided by 2. */
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#define STM32_PLLI2SP_DIV4 (1 << 16) /**< PLLI2S clock divided by 4. */
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#define STM32_PLLI2SP_DIV6 (2 << 16) /**< PLLI2S clock divided by 6. */
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#define STM32_PLLI2SP_DIV8 (3 << 16) /**< PLLI2S clock divided by 8. */
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#define STM32_PLLI2SQ_MASK (15 << 24) /**< PLLI2SQ mask. */
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#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
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/** @} */
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/**
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* @name RCC_PLLSAICFGR register bits definitions
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* @{
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*/
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#define STM32_PLLSAIM_MASK (31 << 0) /**< PLLSAIM mask. */
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#define STM32_PLLSAIN_MASK (511 << 6) /**< PLLSAIN mask. */
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#define STM32_PLLSAIP_MASK (3 << 16) /**< PLLSAIP mask. */
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#define STM32_PLLSAIP_DIV2 (0 << 16) /**< PLLSAI clock divided by 2. */
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#define STM32_PLLSAIP_DIV4 (1 << 16) /**< PLLSAI clock divided by 4. */
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#define STM32_PLLSAIP_DIV6 (2 << 16) /**< PLLSAI clock divided by 6. */
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#define STM32_PLLSAIP_DIV8 (3 << 16) /**< PLLSAI clock divided by 8. */
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#define STM32_PLLSAIQ_MASK (15 << 24) /**< PLLSAIQ mask. */
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#define STM32_PLLSAIR_MASK (7 << 28) /**< PLLSAIR mask. */
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/** @} */
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/**
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* @name RCC_BDCR register bits definitions
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* @{
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@ -410,6 +474,80 @@
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#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
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/** @} */
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/**
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* @name RCC_DCKCFGR register bits definitions
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* @{
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*/
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#define STM32_PLLI2SDIVQ_MASK (31 << 0) /**< PLLI2SDIVQ mask. */
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#define STM32_PLLSAIDIVQ_MASK (31 << 8) /**< PLLSAIDIVQ mask. */
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#define STM32_PLLSAIDIVR_MASK (3 << 16) /**< PLLSAIDIVR mask. */
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#define STM32_PLLSAIDIVR_DIV2 (0 << 16) /**< LCD_CLK is R divided by 2. */
|
||||
#define STM32_PLLSAIDIVR_DIV4 (1 << 16) /**< LCD_CLK is R divided by 4. */
|
||||
#define STM32_PLLSAIDIVR_DIV8 (2 << 16) /**< LCD_CLK is R divided by 8. */
|
||||
#define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/
|
||||
#define STM32_PLLSAIDIVR_OFF 0xFFFFFFFFU /**< LCD CLK is not required. */
|
||||
|
||||
#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */
|
||||
#define STM32_SAI1SEL_PLLSAI (0 << 20) /**< SAI1 source is PLLSAI. */
|
||||
#define STM32_SAI1SEL_PLLI2S (1 << 20) /**< SAI1 source is PLLI2S. */
|
||||
#define STM32_SAI1SEL_PLLR (2 << 20) /**< SAI1 source is PLLR. */
|
||||
#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
|
||||
|
||||
#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */
|
||||
#define STM32_SAI2SEL_PLLSAI (0 << 22) /**< SAI2 source is PLLSAI. */
|
||||
#define STM32_SAI2SEL_PLLI2S (1 << 22) /**< SAI2 source is PLLI2S. */
|
||||
#define STM32_SAI2SEL_PLLR (2 << 22) /**< SAI2 source is PLLR. */
|
||||
#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
|
||||
|
||||
#define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */
|
||||
#define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */
|
||||
#define STM32_TIMPRE_HCLK (1 << 24) /**< TIM clocks from HCLK. */
|
||||
|
||||
#define STM32_I2S1SEL_MASK (3 << 25) /**< I2S1SEL mask. */
|
||||
#define STM32_I2S1SEL_PLLR (0 << 25) /**< I2S1 source is PLLR. */
|
||||
#define STM32_I2S1SEL_AFIN (1 << 25) /**< I2S1 source is AF Input. */
|
||||
#define STM32_I2S1SEL_MCO1 (2 << 25) /**< I2S1 source is MCO1. */
|
||||
#define STM32_I2S1SEL_OFF 0xFFFFFFFFU /**< I2S1 clock is not required.*/
|
||||
|
||||
#define STM32_I2S2SEL_MASK (3 << 27) /**< I2S2SEL mask. */
|
||||
#define STM32_I2S2SEL_PLLR (0 << 27) /**< I2S2 source is PLLR. */
|
||||
#define STM32_I2S2SEL_AFIN (1 << 27) /**< I2S2 source is AF Input. */
|
||||
#define STM32_I2S2SEL_MCO1 (2 << 27) /**< I2S2 source is MCO1. */
|
||||
#define STM32_I2S2SEL_OFF 0xFFFFFFFFU /**< I2S2 clock is not required.*/
|
||||
|
||||
#define STM32_DSISEL_MASK (1 << 28) /**< DSISEL mask. */
|
||||
#define STM32_DSISEL_PHY (0 << 28) /**< DSI source is DSI-PSY. */
|
||||
#define STM32_DSISEL_PLLR (1 << 28) /**< DSI source is PLLR. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RCC_DCKCFGR2 register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_I2C1SEL_MASK (3 << 22) /**< I2C1SEL mask. */
|
||||
#define STM32_I2C1SEL_PCLK1 (0 << 22) /**< I2C1 source is PCLK1. */
|
||||
#define STM32_I2C1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */
|
||||
#define STM32_I2C1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */
|
||||
|
||||
#define STM32_CECSEL_MASK (1 << 26) /**< CECSEL mask. */
|
||||
#define STM32_CECSEL_LSE (0 << 26) /**< CEC source is LSE. */
|
||||
#define STM32_CECSEL_HSIDIV488 (1 << 26) /**< CEC source is HSI/488. */
|
||||
|
||||
#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
|
||||
#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
|
||||
#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */
|
||||
|
||||
#define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */
|
||||
#define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */
|
||||
#define STM32_SDMMCSEL_SYSCLK (1 << 28) /**< SDMMC source is SYSCLK. */
|
||||
|
||||
#define STM32_SPDIFSEL_MASK (1 << 29) /**< SPDIFSEL mask. */
|
||||
#define STM32_SPDIFSEL_PLLI2S (0 << 29) /**< SPDIF source is PLLI2S. */
|
||||
#define STM32_SPDIFSEL_PLL (1 << 29) /**< SPDIF source is PLL. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -597,6 +735,156 @@
|
|||
#endif
|
||||
#endif /* !defined(STM32F4XX) */
|
||||
|
||||
/**
|
||||
* @brief I2S clock source.
|
||||
*/
|
||||
#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
|
||||
#define STM32_I2SSRC STM32_I2SSRC_CKIN
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLI2SN multiplier value.
|
||||
* @note The allowed values are 192..432, except for
|
||||
* STM32F446 where values are 50...432.
|
||||
* @note The default value is calculated for a 96MHz I2S clock
|
||||
* output from an external 8MHz HSE clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SN_VALUE 192
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLI2SM divider value.
|
||||
* @note The allowed values are 2..63.
|
||||
* @note The default value is calculated for a 96MHz I2S clock
|
||||
* output from an external 8MHz HSE clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SM_VALUE 4
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLI2SR divider value.
|
||||
* @note The allowed values are 2..7.
|
||||
* @note The default value is calculated for a 96MHz I2S clock
|
||||
* output from an external 8MHz HSE clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SR_VALUE 4
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLI2SP divider value.
|
||||
* @note The allowed values are 2, 4, 6 and 8.
|
||||
*/
|
||||
#if !defined(STM32_PLLI2SP_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SP_VALUE 4
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLI2SQ divider value.
|
||||
* @note The allowed values are 2..15.
|
||||
*/
|
||||
#if !defined(STM32_PLLI2SQ_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SQ_VALUE 4
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLI2SDIVQ divider value (SAI clock divider).
|
||||
*/
|
||||
#if !defined(STM32_PLLI2SDIVQ) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SDIVQ 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLSAIM value.
|
||||
* @note The allowed values are 2..63.
|
||||
* @note The default value is calculated for a 96MHz SAI clock
|
||||
* output from an external 8MHz HSE clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIM_VALUE 4
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLSAIN value.
|
||||
* @note The allowed values are 50..432.
|
||||
* @note The default value is calculated for a 96MHz SAI clock
|
||||
* output from an external 8MHz HSE clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLSAIN_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIN_VALUE 192
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLSAIM value.
|
||||
* @note The allowed values are 2..63.
|
||||
* @note The default value is calculated for a 96MHz SAI clock
|
||||
* output from an external 8MHz HSE clock.
|
||||
*/
|
||||
#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIM_VALUE 4
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLSAIR value.
|
||||
* @note The allowed values are 2..7.
|
||||
*/
|
||||
#if !defined(STM32_PLLSAIR_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIR_VALUE 4
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLSAIP divider value.
|
||||
* @note The allowed values are 2, 4, 6 and 8.
|
||||
*/
|
||||
#if !defined(STM32_PLLSAIP_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIP_VALUE 8
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLSAIQ value.
|
||||
* @note The allowed values are 2..15.
|
||||
*/
|
||||
#if !defined(STM32_PLLSAIQ_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIQ_VALUE 4
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLSAIDIVR divider value (SAI clock divider).
|
||||
*/
|
||||
#if !defined(STM32_PLLSAIDIVR) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLSAIDIVR divider value (LCD clock divider).
|
||||
*/
|
||||
#if !defined(STM32_PLLSAIDIVQ) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIDIVQ 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SAI1SEL value (SAI1 clock source).
|
||||
*/
|
||||
#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
|
||||
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SAI2SEL value (SAI2 clock source).
|
||||
*/
|
||||
#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)
|
||||
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL48CLK clock source.
|
||||
*/
|
||||
#if !defined(STM32_CK48MSEL) || defined(__DOXYGEN__)
|
||||
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief AHB prescaler value.
|
||||
*/
|
||||
|
|
@ -663,53 +951,6 @@
|
|||
#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
|
||||
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief I2S clock source.
|
||||
*/
|
||||
#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
|
||||
#define STM32_I2SSRC STM32_I2SSRC_CKIN
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLI2SN multiplier value.
|
||||
* @note The allowed values are 192..432.
|
||||
*/
|
||||
#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SN_VALUE 192
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLI2SR multiplier value.
|
||||
* @note The allowed values are 2..7.
|
||||
*/
|
||||
#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SR_VALUE 5
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLSAIQ value.
|
||||
* @note The allowed values are 2..15.
|
||||
*/
|
||||
#if !defined(STM32_PLLSAIQ_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIQ_VALUE 8
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLSAIQ value.
|
||||
* @note The allowed values are 49..432.
|
||||
*/
|
||||
#if !defined(STM32_PLLSAIN_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIN_VALUE 120
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLSAIQ value.
|
||||
* @note The allowed values are 2..7.
|
||||
*/
|
||||
#if !defined(STM32_PLLSAIR_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIR_VALUE 4
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -739,7 +980,7 @@
|
|||
*/
|
||||
#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
|
||||
defined(STM32F40_41xxx) || defined(STM32F446xx) || \
|
||||
defined(__DOXYGEN__)
|
||||
defined(STM32F469_479xx) || defined(__DOXYGEN__)
|
||||
#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)
|
||||
#define STM32_0WS_THRESHOLD 30000000
|
||||
#define STM32_1WS_THRESHOLD 60000000
|
||||
|
|
@ -829,7 +1070,7 @@
|
|||
#error "invalid VDD voltage specified"
|
||||
#endif
|
||||
|
||||
#elif defined(STM32F411xx)
|
||||
#elif defined(STM32F410xx) || defined(STM32F411xx)
|
||||
#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
|
||||
#define STM32_0WS_THRESHOLD 30000000
|
||||
#define STM32_1WS_THRESHOLD 64000000
|
||||
|
|
@ -945,6 +1186,17 @@
|
|||
#error "HSI not enabled, required by STM32_I2SSRC"
|
||||
#endif
|
||||
|
||||
#if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
|
||||
(STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S)) && \
|
||||
(STM32_PLLSRC == STM32_PLLSRC_HSI)
|
||||
#error "HSI not enabled, required by STM32_SAI1SEL"
|
||||
#endif
|
||||
|
||||
#if ((STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI) || \
|
||||
(STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S)) && \
|
||||
(STM32_PLLSRC == STM32_PLLSRC_HSI)
|
||||
#error "HSI not enabled, required by STM32_SAI2SEL"
|
||||
#endif
|
||||
#endif /* !STM32_HSI_ENABLED */
|
||||
|
||||
/*
|
||||
|
|
@ -954,10 +1206,17 @@
|
|||
|
||||
#if STM32_HSECLK == 0
|
||||
#error "HSE frequency not defined"
|
||||
#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
|
||||
#else /* STM32_HSECLK != 0 */
|
||||
#if defined(STM32_HSE_BYPASS)
|
||||
#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
|
||||
#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_BYP_MAX)"
|
||||
#endif
|
||||
#else /* !defined(STM32_HSE_BYPASS) */
|
||||
#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
|
||||
#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
|
||||
#endif
|
||||
|
||||
#endif /* !defined(STM32_HSE_BYPASS) */
|
||||
#endif /* STM32_HSECLK != 0 */
|
||||
#else /* !STM32_HSE_ENABLED */
|
||||
|
||||
#if STM32_SW == STM32_SW_HSE
|
||||
|
|
@ -1035,7 +1294,7 @@
|
|||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLs input clock frequency.
|
||||
* @brief PLL input clock frequency.
|
||||
*/
|
||||
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
|
||||
|
|
@ -1082,13 +1341,13 @@
|
|||
* @brief STM32_PLLP field.
|
||||
*/
|
||||
#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLP (0 << 16)
|
||||
#define STM32_PLLP STM32_PLLP_DIV2
|
||||
#elif STM32_PLLP_VALUE == 4
|
||||
#define STM32_PLLP (1 << 16)
|
||||
#define STM32_PLLP STM32_PLLP_DIV4
|
||||
#elif STM32_PLLP_VALUE == 6
|
||||
#define STM32_PLLP (2 << 16)
|
||||
#define STM32_PLLP STM32_PLLP_DIV6
|
||||
#elif STM32_PLLP_VALUE == 8
|
||||
#define STM32_PLLP (3 << 16)
|
||||
#define STM32_PLLP STM32_PLLP_DIV8
|
||||
#else
|
||||
#error "invalid STM32_PLLP_VALUE value specified"
|
||||
#endif
|
||||
|
|
@ -1149,7 +1408,8 @@
|
|||
|
||||
/* Calculating VOS settings, it is different for each sub-platform.*/
|
||||
#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
|
||||
defined(STM32F446xx) || defined(__DOXYGEN__)
|
||||
defined(STM32F446xx) || defined(STM32F469_479xx) || \
|
||||
defined(__DOXYGEN__)
|
||||
#if STM32_SYSCLK <= 120000000
|
||||
#define STM32_VOS STM32_VOS_SCALE3
|
||||
#define STM32_OVERDRIVE_REQUIRED FALSE
|
||||
|
|
@ -1180,7 +1440,7 @@
|
|||
#endif
|
||||
#define STM32_OVERDRIVE_REQUIRED FALSE
|
||||
|
||||
#elif defined(STM32F411xx)
|
||||
#elif defined(STM32F410xx) || defined(STM32F411xx) || defined(STM32F412xx)
|
||||
#if STM32_SYSCLK <= 64000000
|
||||
#define STM32_VOS STM32_VOS_SCALE3
|
||||
#elif STM32_SYSCLK <= 84000000
|
||||
|
|
@ -1277,7 +1537,10 @@
|
|||
/*
|
||||
* PLLI2S enable check.
|
||||
*/
|
||||
#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || defined(__DOXYGEN__)
|
||||
#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
|
||||
(STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) || \
|
||||
(STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S) || \
|
||||
defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PLLI2S activation flag.
|
||||
*/
|
||||
|
|
@ -1286,15 +1549,59 @@
|
|||
#define STM32_ACTIVATE_PLLI2S FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLI2SM field.
|
||||
*/
|
||||
#if ((STM32_PLLI2SM_VALUE >= 2) && (STM32_PLLI2SM_VALUE <= 63)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SM (STM32_PLLI2SM_VALUE << 0)
|
||||
#else
|
||||
#error "invalid STM32_PLLI2SM_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLI2SN field.
|
||||
*/
|
||||
#if defined (STM32F446xx) || defined(__DOXYGEN__)
|
||||
#if ((STM32_PLLI2SN_VALUE >= 50) && (STM32_PLLI2SN_VALUE <= 432)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6)
|
||||
#else
|
||||
#error "invalid STM32_PLLI2SN_VALUE value specified"
|
||||
#endif
|
||||
#else /* !defined(STM32F446xx) */
|
||||
#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6)
|
||||
#else
|
||||
#error "invalid STM32_PLLI2SN_VALUE value specified"
|
||||
#endif
|
||||
#endif /* defined(STM32F446xx) */
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLI2SP field.
|
||||
*/
|
||||
#if (STM32_PLLI2SP_VALUE == 2) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SP STM32_PLLI2SP_DIV2
|
||||
#elif STM32_PLLI2SP_VALUE == 4
|
||||
#define STM32_PLLI2SP STM32_PLLI2SP_DIV4
|
||||
#elif STM32_PLLI2SP_VALUE == 6
|
||||
#define STM32_PLLI2SP STM32_PLLI2SP_DIV6
|
||||
#elif STM32_PLLI2SP_VALUE == 8
|
||||
#define STM32_PLLI2SP STM32_PLLI2SP_DIV8
|
||||
#else
|
||||
#error "invalid STM32_PLLI2SP_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLI2SQ field.
|
||||
*/
|
||||
#if ((STM32_PLLI2SQ_VALUE >= 2) && (STM32_PLLI2SQ_VALUE <= 15)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SQ (STM32_PLLI2SQ_VALUE << 24)
|
||||
#else
|
||||
#error "invalid STM32_PLLI2SQ_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLI2SR field.
|
||||
|
|
@ -1306,10 +1613,80 @@
|
|||
#error "invalid STM32_PLLI2SR_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLI2S input clock frequency.
|
||||
*/
|
||||
#if defined(STM32F446xx)
|
||||
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SCLKIN (STM32_HSECLK / STM32_PLLI2SM_VALUE)
|
||||
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
|
||||
#define STM32_PLLI2SCLKIN (STM32_HSICLK / STM32_PLLI2SM_VALUE)
|
||||
#else
|
||||
#error "invalid STM32_PLLSRC value specified"
|
||||
#endif
|
||||
#else /* !defined(STM32F446xx) */
|
||||
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLI2SCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
|
||||
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
|
||||
#define STM32_PLLI2SCLKIN (STM32_HSICLK / STM32_PLLM_VALUE)
|
||||
#else
|
||||
#error "invalid STM32_PLLSRC value specified"
|
||||
#endif
|
||||
#endif /* defined(STM32F446xx) */
|
||||
|
||||
/**
|
||||
* @brief PLLI2S VCO frequency.
|
||||
*/
|
||||
#define STM32_PLLI2SVCO (STM32_PLLI2SCLKIN * STM32_PLLI2SN_VALUE)
|
||||
|
||||
/*
|
||||
* PLLI2S VCO frequency range check.
|
||||
*/
|
||||
#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \
|
||||
(STM32_PLLI2SVCO > STM32_PLLVCO_MAX)
|
||||
#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLI2S P output clock frequency.
|
||||
*/
|
||||
#define STM32_PLLI2S_P_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SP_VALUE)
|
||||
|
||||
/**
|
||||
* @brief PLLI2S Q output clock frequency.
|
||||
*/
|
||||
#define STM32_PLLI2S_Q_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SQ_VALUE)
|
||||
|
||||
/**
|
||||
* @brief PLLI2S R output clock frequency.
|
||||
*/
|
||||
#define STM32_PLLI2S_R_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)
|
||||
|
||||
/*
|
||||
* PLLSAI enable check.
|
||||
*/
|
||||
#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI)) | \
|
||||
(STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) || \
|
||||
(STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
|
||||
(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI) || \
|
||||
defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PLLSAI activation flag.
|
||||
*/
|
||||
#define STM32_ACTIVATE_PLLSAI TRUE
|
||||
#else
|
||||
#define STM32_ACTIVATE_PLLSAI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLSAIM field.
|
||||
*/
|
||||
#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIM (STM32_PLLSAIM_VALUE << 0)
|
||||
#else
|
||||
#error "invalid STM32_PLLSAIM_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLSAIN field.
|
||||
|
|
@ -1328,7 +1705,7 @@
|
|||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIQ (STM32_PLLSAIQ_VALUE << 24)
|
||||
#else
|
||||
#error "invalid STM32_PLLSAIR_VALUE value specified"
|
||||
#error "invalid STM32_PLLSAIQ_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -1342,34 +1719,89 @@
|
|||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL VCO frequency.
|
||||
* @brief STM32_PLLSAIP field.
|
||||
*/
|
||||
#define STM32_PLLI2SVCO (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE)
|
||||
|
||||
/*
|
||||
* PLLI2S VCO frequency range check.
|
||||
*/
|
||||
#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \
|
||||
(STM32_PLLI2SVCO > STM32_PLLVCO_MAX)
|
||||
#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
|
||||
#if (STM32_PLLSAIP_VALUE == 2) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAIP STM32_PLLSAIP_DIV2
|
||||
|
||||
#elif STM32_PLLSAIP_VALUE == 4
|
||||
#define STM32_PLLSAIP STM32_PLLSAIP_DIV4
|
||||
|
||||
#elif STM32_PLLSAIP_VALUE == 6
|
||||
#define STM32_PLLSAIP STM32_PLLSAIP_DIV6
|
||||
|
||||
#elif STM32_PLLSAIP_VALUE == 8
|
||||
#define STM32_PLLSAIP STM32_PLLSAIP_DIV8
|
||||
|
||||
#else
|
||||
#error "invalid STM32_PLLSAIP_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLI2S output clock frequency.
|
||||
* @brief PLLSAI input clock frequency.
|
||||
*/
|
||||
#define STM32_PLLI2SCLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)
|
||||
#if defined(STM32F446xx)
|
||||
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAICLKIN (STM32_HSECLK / STM32_PLLSAIM_VALUE)
|
||||
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
|
||||
#define STM32_PLLSAICLKIN (STM32_HSICLK / STM32_PLLSAIM_VALUE)
|
||||
#else
|
||||
#error "invalid STM32_PLLSRC value specified"
|
||||
#endif
|
||||
#else /* !defined(STM32F446xx) */
|
||||
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSAICLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
|
||||
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
|
||||
#define STM32_PLLSAICLKIN (STM32_HSICLK / STM32_PLLM_VALUE)
|
||||
#else
|
||||
#error "invalid STM32_PLLSRC value specified"
|
||||
#endif
|
||||
#endif /* defined(STM32F446xx) */
|
||||
|
||||
/**
|
||||
* @brief PLLSAI VCO frequency.
|
||||
*/
|
||||
#define STM32_PLLSAIVCO (STM32_PLLSAICLKIN * STM32_PLLSAIN_VALUE)
|
||||
|
||||
/*
|
||||
* PLLSAI VCO frequency range check.
|
||||
*/
|
||||
#if (STM32_PLLSAIVCO < STM32_PLLVCO_MIN) || \
|
||||
(STM32_PLLSAIVCO > STM32_PLLVCO_MAX)
|
||||
#error "STM32_PLLSAIVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLSAI P output clock frequency.
|
||||
*/
|
||||
#define STM32_PLLSAI_P_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
|
||||
|
||||
/**
|
||||
* @brief PLLSAI Q output clock frequency.
|
||||
*/
|
||||
#define STM32_PLLSAI_Q_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE)
|
||||
|
||||
/**
|
||||
* @brief PLLSAI R output clock frequency.
|
||||
*/
|
||||
#define STM32_PLLSAI_R_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE)
|
||||
|
||||
/**
|
||||
* @brief MCO1 divider clock.
|
||||
*/
|
||||
#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
|
||||
#define STM32_MCO1DIVCLK STM32_HSICLK
|
||||
|
||||
#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
|
||||
#define STM32_MCO1DIVCLK STM32_LSECLK
|
||||
|
||||
#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
|
||||
#define STM32_MCO1DIVCLK STM32_HSECLK
|
||||
|
||||
#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
|
||||
#define STM32_MCO1DIVCLK STM32_PLLCLKOUT
|
||||
|
||||
#else
|
||||
#error "invalid STM32_MCO1SEL value specified"
|
||||
#endif
|
||||
|
|
@ -1379,14 +1811,19 @@
|
|||
*/
|
||||
#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_MCO1CLK STM32_MCO1DIVCLK
|
||||
|
||||
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
|
||||
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
|
||||
|
||||
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
|
||||
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
|
||||
|
||||
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
|
||||
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
|
||||
|
||||
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
|
||||
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
|
||||
|
||||
#else
|
||||
#error "invalid STM32_MCO1PRE value specified"
|
||||
#endif
|
||||
|
|
@ -1396,12 +1833,16 @@
|
|||
*/
|
||||
#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
|
||||
#define STM32_MCO2DIVCLK STM32_HSECLK
|
||||
|
||||
#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
|
||||
#define STM32_MCO2DIVCLK STM32_PLLCLKOUT
|
||||
|
||||
#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
|
||||
#define STM32_MCO2DIVCLK STM32_SYSCLK
|
||||
|
||||
#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
|
||||
#define STM32_MCO2DIVCLK STM32_PLLI2S
|
||||
|
||||
#else
|
||||
#error "invalid STM32_MCO2SEL value specified"
|
||||
#endif
|
||||
|
|
@ -1411,14 +1852,19 @@
|
|||
*/
|
||||
#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_MCO2CLK STM32_MCO2DIVCLK
|
||||
|
||||
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
|
||||
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
|
||||
|
||||
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
|
||||
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
|
||||
|
||||
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
|
||||
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
|
||||
|
||||
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
|
||||
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
|
||||
|
||||
#else
|
||||
#error "invalid STM32_MCO2PRE value specified"
|
||||
#endif
|
||||
|
|
@ -1448,12 +1894,16 @@
|
|||
*/
|
||||
#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
|
||||
#define STM32_RTCCLK 0
|
||||
|
||||
#elif STM32_RTCSEL == STM32_RTCSEL_LSE
|
||||
#define STM32_RTCCLK STM32_LSECLK
|
||||
|
||||
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
|
||||
#define STM32_RTCCLK STM32_LSICLK
|
||||
|
||||
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
|
||||
#define STM32_RTCCLK STM32_HSEDIVCLK
|
||||
|
||||
#else
|
||||
#error "invalid STM32_RTCSEL value specified"
|
||||
#endif
|
||||
|
|
@ -1462,10 +1912,16 @@
|
|||
* @brief 48MHz frequency.
|
||||
*/
|
||||
#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
|
||||
#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
|
||||
#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
|
||||
#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI
|
||||
#define STM32_PLL48CLK (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
|
||||
#else
|
||||
#define STM32_PLL48CLK 0
|
||||
#error "invalid source selected for PLL48CLK clock"
|
||||
#endif
|
||||
#else /* !STM32_CLOCK48_REQUIRED */
|
||||
#define STM32_PLL48CLK 0
|
||||
#endif /* !STM32_CLOCK48_REQUIRED */
|
||||
|
||||
/**
|
||||
* @brief Clock of timers connected to APB1
|
||||
|
|
@ -1547,6 +2003,6 @@ extern "C" {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_LLD_H_ */
|
||||
#endif /* HAL_LLD_H */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
File diff suppressed because it is too large
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Reference in New Issue