git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7807 35acf78f-673a-0410-8e92-d51de3d6d3f4
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file DMAv1/stm32_dma.c
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* @brief DMA helper driver code.
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*
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* @addtogroup STM32_DMA_V1
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* @details DMA sharing helper driver. In the STM32 the DMA streams are a
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* shared resource, this driver allows to allocate and free DMA
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* streams at runtime in order to allow all the other device
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* drivers to coordinate the access to the resource.
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* @note The DMA ISR handlers are all declared into this module because
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* sharing, the various device drivers can associate a callback to
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* ISRs when allocating streams.
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* @{
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*/
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#include "hal.h"
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/* The following macro is only defined if some driver requiring DMA services
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has been enabled.*/
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#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @brief Mask of the DMA1 streams in @p dma_streams_mask.
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*/
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#define STM32_DMA1_STREAMS_MASK 0x0000007FU
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/**
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* @brief Mask of the DMA2 streams in @p dma_streams_mask.
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*/
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#define STM32_DMA2_STREAMS_MASK 0x00000F80U
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/**
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* @brief Post-reset value of the stream CCR register.
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*/
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#define STM32_DMA_CCR_RESET_VALUE 0x00000000U
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief DMA streams descriptors.
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* @details This table keeps the association between an unique stream
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* identifier and the involved physical registers.
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* @note Don't use this array directly, use the appropriate wrapper macros
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* instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
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*/
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const stm32_dma_stream_t __stm32_dma_streams[STM32_DMA_STREAMS] = {
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{DMA1_Channel1, &DMA1->IFCR, 0, 0, STM32_DMA1_STREAM1_EVENT_NUMBER},
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{DMA1_Channel2, &DMA1->IFCR, 4, 1, STM32_DMA1_STREAM2_EVENT_NUMBER},
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{DMA1_Channel3, &DMA1->IFCR, 8, 2, STM32_DMA1_STREAM3_EVENT_NUMBER},
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{DMA1_Channel4, &DMA1->IFCR, 12, 3, STM32_DMA1_STREAM4_EVENT_NUMBER},
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{DMA1_Channel5, &DMA1->IFCR, 16, 4, STM32_DMA1_STREAM5_EVENT_NUMBER},
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#if STM32_DMA_STREAMS > 5
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{DMA1_Channel6, &DMA1->IFCR, 20, 5, STM32_DMA1_STREAM6_EVENT_NUMBER},
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{DMA1_Channel7, &DMA1->IFCR, 24, 6, STM32_DMA1_STREAM7_EVENT_NUMBER},
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#endif
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#if STM32_DMA_STREAMS > 7
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{DMA2_Channel1, &DMA2->IFCR, 0, 7, STM32_DMA2_STREAM1_EVENT_NUMBER},
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{DMA2_Channel2, &DMA2->IFCR, 4, 8, STM32_DMA2_STREAM2_EVENT_NUMBER},
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{DMA2_Channel3, &DMA2->IFCR, 8, 9, STM32_DMA2_STREAM3_EVENT_NUMBER},
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{DMA2_Channel4, &DMA2->IFCR, 12, 10, STM32_DMA2_STREAM4_EVENT_NUMBER},
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{DMA2_Channel5, &DMA2->IFCR, 16, 11, STM32_DMA2_STREAM5_EVENT_NUMBER},
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#endif
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};
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/**
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* @brief DMA ISR redirector type.
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*/
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typedef struct {
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stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
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void *dma_param; /**< @brief DMA callback parameter. */
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} dma_isr_redir_t;
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/**
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* @brief Mask of the allocated streams.
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*/
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static uint32_t dma_streams_mask;
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/**
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* @brief DMA IRQ redirectors.
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*/
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static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if defined(STM32_DMA1_STREAM1_EVENT_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA1 stream 1 shared interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_DMA1_STREAM1_EVENT_HANDLER) {
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uint32_t flags;
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OSAL_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = flags << 0;
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if (dma_isr_redir[0].dma_func)
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dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(STM32_DMA1_STREAM2_EVENT_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA1 stream 2 shared interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_DMA1_STREAM2_EVENT_HANDLER) {
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uint32_t flags;
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OSAL_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = flags << 4;
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if (dma_isr_redir[1].dma_func)
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dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(STM32_DMA1_STREAM3_EVENT_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA1 stream 3 shared interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_DMA1_STREAM3_EVENT_HANDLER) {
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uint32_t flags;
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OSAL_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = flags << 8;
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if (dma_isr_redir[2].dma_func)
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dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(STM32_DMA1_STREAM4_EVENT_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA1 stream 4 shared interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_DMA1_STREAM4_EVENT_HANDLER) {
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uint32_t flags;
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OSAL_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = flags << 12;
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if (dma_isr_redir[3].dma_func)
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dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(STM32_DMA1_STREAM5_EVENT_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA1 stream 5 shared interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_DMA1_STREAM5_EVENT_HANDLER) {
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uint32_t flags;
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OSAL_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = flags << 16;
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if (dma_isr_redir[4].dma_func)
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dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(STM32_DMA1_STREAM6_EVENT_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA1 stream 6 shared interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_DMA1_STREAM6_EVENT_HANDLER) {
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uint32_t flags;
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OSAL_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = flags << 20;
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if (dma_isr_redir[5].dma_func)
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dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(STM32_DMA1_STREAM7_EVENT_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA1 stream 7 shared interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_DMA1_STREAM7_EVENT_HANDLER) {
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uint32_t flags;
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OSAL_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = flags << 24;
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if (dma_isr_redir[6].dma_func)
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dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(STM32_DMA2_STREAM1_EVENT_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA2 stream 1 shared interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_DMA2_STREAM1_EVENT_HANDLER) {
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uint32_t flags;
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OSAL_IRQ_PROLOGUE();
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flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
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DMA2->IFCR = flags << 0;
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if (dma_isr_redir[7].dma_func)
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dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(STM32_DMA2_STREAM2_EVENT_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA2 stream 2 shared interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_DMA2_STREAM2_EVENT_HANDLER) {
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uint32_t flags;
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OSAL_IRQ_PROLOGUE();
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flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
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DMA2->IFCR = flags << 4;
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if (dma_isr_redir[8].dma_func)
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dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(STM32_DMA2_STREAM3_EVENT_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA2 stream 3 shared interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_DMA2_STREAM3_EVENT_HANDLER) {
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uint32_t flags;
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OSAL_IRQ_PROLOGUE();
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flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
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DMA2->IFCR = flags << 8;
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if (dma_isr_redir[9].dma_func)
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dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(STM32_DMA2_STREAM4_EVENT_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA2 stream 4 shared interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_DMA2_STREAM4_EVENT_HANDLER) {
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uint32_t flags;
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OSAL_IRQ_PROLOGUE();
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flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
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DMA2->IFCR = flags << 12;
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if (dma_isr_redir[10].dma_func)
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dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(STM32_DMA2_STREAM5_EVENT_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA2 stream 5 shared interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_DMA2_STREAM5_EVENT_HANDLER) {
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uint32_t flags;
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OSAL_IRQ_PROLOGUE();
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flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
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DMA2->IFCR = flags << 16;
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if (dma_isr_redir[11].dma_func)
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dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief STM32 DMA helper initialization.
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*
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* @init
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*/
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void dmaInit(void) {
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int i;
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dma_streams_mask = 0;
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for (i = 0; i < STM32_DMA_STREAMS; i++) {
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__stm32_dma_streams[i].channel->CCR = STM32_DMA_CCR_RESET_VALUE;
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dma_isr_redir[i].dma_func = NULL;
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}
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DMA1->IFCR = 0xFFFFFFFFU;
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#if STM32_HAS_DMA2
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DMA2->IFCR = 0xFFFFFFFFU;
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#endif
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}
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/**
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* @brief Allocates a DMA stream.
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* @details The stream is allocated and, if required, the DMA clock enabled.
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* The function also enables the IRQ vector associated to the stream
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* and initializes its priority.
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* @pre The stream must not be already in use or an error is returned.
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* @post The stream is allocated and the default ISR handler redirected
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* to the specified function.
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* @post The stream ISR vector is enabled and its priority configured.
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* @post The stream must be freed using @p dmaStreamRelease() before it can
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* be reused with another peripheral.
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* @post The stream is in its post-reset state.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] priority IRQ priority mask for the DMA stream
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* @param[in] func handling function pointer, can be @p NULL
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* @param[in] param a parameter to be passed to the handling function
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* @return The operation status.
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* @retval false no error, stream taken.
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* @retval true error, stream already taken.
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*
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* @special
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*/
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bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
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uint32_t priority,
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stm32_dmaisr_t func,
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void *param) {
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osalDbgCheck(dmastp != NULL);
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/* Checks if the stream is already taken.*/
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if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
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return true;
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/* Marks the stream as allocated.*/
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dma_isr_redir[dmastp->selfindex].dma_func = func;
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dma_isr_redir[dmastp->selfindex].dma_param = param;
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dma_streams_mask |= (1 << dmastp->selfindex);
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/* Enabling DMA clocks required by the current streams set.*/
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if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
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rccEnableDMA1(false);
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#if STM32_HAS_DMA2
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if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
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rccEnableDMA2(false);
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#endif
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/* Putting the stream in a safe state.*/
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dmaStreamDisable(dmastp);
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dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
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/* Enables the associated IRQ vector if a callback is defined.*/
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if (func != NULL)
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nvicEnableVector(dmastp->vector, priority);
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return false;
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}
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/**
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* @brief Releases a DMA stream.
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* @details The stream is freed and, if required, the DMA clock disabled.
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* Trying to release a unallocated stream is an illegal operation
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* and is trapped if assertions are enabled.
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* @pre The stream must have been allocated using @p dmaStreamAllocate().
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* @post The stream is again available.
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* @note This function can be invoked in both ISR or thread context.
|
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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*
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* @special
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||||
*/
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void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
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osalDbgCheck(dmastp != NULL);
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/* Check if the streams is not taken.*/
|
||||
osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
|
||||
"not allocated");
|
||||
|
||||
/* Disables the associated IRQ vector.*/
|
||||
nvicDisableVector(dmastp->vector);
|
||||
|
||||
/* Marks the stream as not allocated.*/
|
||||
dma_streams_mask &= ~(1 << dmastp->selfindex);
|
||||
|
||||
/* Shutting down clocks that are no more required, if any.*/
|
||||
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
|
||||
rccDisableDMA1(false);
|
||||
#if STM32_HAS_DMA2
|
||||
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
|
||||
rccDisableDMA2(false);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* STM32_DMA_REQUIRED */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,418 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file DMAv1/stm32_dma.h
|
||||
* @brief DMA helper driver header.
|
||||
* @note This driver uses the new naming convention used for the STM32F2xx
|
||||
* so the "DMA channels" are referred as "DMA streams".
|
||||
*
|
||||
* @addtogroup STM32_DMA_V1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _STM32_DMA_H_
|
||||
#define _STM32_DMA_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Mask of the ISR bits passed to the DMA callback functions.
|
||||
*/
|
||||
#define STM32_DMA_ISR_MASK 0x0F
|
||||
|
||||
/**
|
||||
* @brief Returns the channel associated to the specified stream.
|
||||
*
|
||||
* @param[in] n the stream number (0...STM32_DMA_STREAMS-1)
|
||||
* @param[in] c a stream/channel association word, one channel per
|
||||
* nibble, not associated channels must be set to 0xF
|
||||
* @return Always zero, in this platform there is no dynamic
|
||||
* association between streams and channels.
|
||||
*/
|
||||
#define STM32_DMA_GETCHANNEL(n, c) 0
|
||||
|
||||
/**
|
||||
* @brief Checks if a DMA priority is within the valid range.
|
||||
* @param[in] prio DMA priority
|
||||
*
|
||||
* @retval The check result.
|
||||
* @retval FALSE invalid DMA priority.
|
||||
* @retval TRUE correct DMA priority.
|
||||
*/
|
||||
#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
|
||||
|
||||
/**
|
||||
* @brief Returns an unique numeric identifier for a DMA stream.
|
||||
*
|
||||
* @param[in] dma the DMA unit number
|
||||
* @param[in] stream the stream number
|
||||
* @return An unique numeric stream identifier.
|
||||
*/
|
||||
#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
|
||||
|
||||
/**
|
||||
* @brief Returns a DMA stream identifier mask.
|
||||
*
|
||||
*
|
||||
* @param[in] dma the DMA unit number
|
||||
* @param[in] stream the stream number
|
||||
* @return A DMA stream identifier mask.
|
||||
*/
|
||||
#define STM32_DMA_STREAM_ID_MSK(dma, stream) \
|
||||
(1 << STM32_DMA_STREAM_ID(dma, stream))
|
||||
|
||||
/**
|
||||
* @brief Checks if a DMA stream unique identifier belongs to a mask.
|
||||
* @param[in] id the stream numeric identifier
|
||||
* @param[in] mask the stream numeric identifiers mask
|
||||
*
|
||||
* @retval The check result.
|
||||
* @retval FALSE id does not belong to the mask.
|
||||
* @retval TRUE id belongs to the mask.
|
||||
*/
|
||||
#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
|
||||
|
||||
/**
|
||||
* @name DMA streams identifiers
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Returns a pointer to a stm32_dma_stream_t structure.
|
||||
*
|
||||
* @param[in] id the stream numeric identifier
|
||||
* @return A pointer to the stm32_dma_stream_t constant structure
|
||||
* associated to the DMA stream.
|
||||
*/
|
||||
#define STM32_DMA_STREAM(id) (&__stm32_dma_streams[id])
|
||||
|
||||
#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0)
|
||||
#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1)
|
||||
#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2)
|
||||
#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3)
|
||||
#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4)
|
||||
#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5)
|
||||
#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6)
|
||||
#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7)
|
||||
#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8)
|
||||
#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9)
|
||||
#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10)
|
||||
#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name CR register constants common to all DMA types
|
||||
* @{
|
||||
*/
|
||||
#define STM32_DMA_CR_EN DMA_CCR_EN
|
||||
#define STM32_DMA_CR_TEIE DMA_CCR_TEIE
|
||||
#define STM32_DMA_CR_HTIE DMA_CCR_HTIE
|
||||
#define STM32_DMA_CR_TCIE DMA_CCR_TCIE
|
||||
#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
|
||||
#define STM32_DMA_CR_DIR_P2M 0
|
||||
#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR
|
||||
#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM
|
||||
#define STM32_DMA_CR_CIRC DMA_CCR_CIRC
|
||||
#define STM32_DMA_CR_PINC DMA_CCR_PINC
|
||||
#define STM32_DMA_CR_MINC DMA_CCR_MINC
|
||||
#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE
|
||||
#define STM32_DMA_CR_PSIZE_BYTE 0
|
||||
#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0
|
||||
#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1
|
||||
#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE
|
||||
#define STM32_DMA_CR_MSIZE_BYTE 0
|
||||
#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0
|
||||
#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1
|
||||
#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \
|
||||
STM32_DMA_CR_MSIZE_MASK)
|
||||
#define STM32_DMA_CR_PL_MASK DMA_CCR_PL
|
||||
#define STM32_DMA_CR_PL(n) ((n) << 12)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name CR register constants only found in enhanced DMA
|
||||
* @{
|
||||
*/
|
||||
#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */
|
||||
#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */
|
||||
#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Status flags passed to the ISR callbacks
|
||||
* @{
|
||||
*/
|
||||
#define STM32_DMA_ISR_FEIF 0
|
||||
#define STM32_DMA_ISR_DMEIF 0
|
||||
#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1
|
||||
#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1
|
||||
#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(STM32_ADVANCED_DMA)
|
||||
#error "missing STM32_ADVANCED_DMA definition in registry"
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_DMA_STREAMS)
|
||||
#error "missing STM32_DMA_STREAMS definition in registry"
|
||||
#error
|
||||
|
||||
#if !defined(STM32_DMA_RELOCATION)
|
||||
#error "missing STM32_DMA_RELOCATION definition in registry"
|
||||
#endif
|
||||
|
||||
#if STM32_ADVANCED_DMA == TRUE
|
||||
#error "DMAv1 driver does not support STM32_ADVANCED_DMA"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Presence of DMA2 controller.
|
||||
*/
|
||||
#if (STM32_DMA_STREAMS > 7) || defined(__DOXYGEN__)
|
||||
#define STM32_HAS_DMA2 TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief STM32 DMA stream descriptor structure.
|
||||
*/
|
||||
typedef struct {
|
||||
DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
|
||||
volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
|
||||
uint8_t ishift; /**< @brief Bits offset in xIFCR
|
||||
register. */
|
||||
uint8_t selfindex; /**< @brief Index to self in array. */
|
||||
uint8_t vector; /**< @brief Associated IRQ vector. */
|
||||
} stm32_dma_stream_t;
|
||||
|
||||
/**
|
||||
* @brief STM32 DMA ISR function type.
|
||||
*
|
||||
* @param[in] p parameter for the registered function
|
||||
* @param[in] flags pre-shifted content of the ISR register, the bits
|
||||
* are aligned to bit zero
|
||||
*/
|
||||
typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Macro Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Associates a peripheral data register to a DMA stream.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] addr value to be written in the CPAR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetPeripheral(dmastp, addr) { \
|
||||
(dmastp)->channel->CPAR = (uint32_t)(addr); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Associates a memory destination to a DMA stream.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] addr value to be written in the CMAR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetMemory0(dmastp, addr) { \
|
||||
(dmastp)->channel->CMAR = (uint32_t)(addr); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the number of transfers to be performed.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] size value to be written in the CNDTR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetTransactionSize(dmastp, size) { \
|
||||
(dmastp)->channel->CNDTR = (uint32_t)(size); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of transfers to be performed.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @return The number of transfers to be performed.
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
|
||||
|
||||
/**
|
||||
* @brief Programs the stream mode settings.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] mode value to be written in the CCR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetMode(dmastp, mode) { \
|
||||
(dmastp)->channel->CCR = (uint32_t)(mode); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA stream enable.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamEnable(dmastp) { \
|
||||
(dmastp)->channel->CCR |= STM32_DMA_CR_EN; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA stream disable.
|
||||
* @details The function disables the specified stream and then clears any
|
||||
* pending interrupt.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @note Interrupts enabling flags are set to zero after this call, see
|
||||
* bug 3607518.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamDisable(dmastp) { \
|
||||
(dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
|
||||
STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \
|
||||
dmaStreamClearInterrupt(dmastp); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA stream interrupt sources clear.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamClearInterrupt(dmastp) { \
|
||||
*(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts a memory to memory operation using the specified stream.
|
||||
* @note The default transfer data mode is "byte to byte" but it can be
|
||||
* changed by specifying extra options in the @p mode parameter.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] mode value to be written in the CCR register, this value
|
||||
* is implicitly ORed with:
|
||||
* - @p STM32_DMA_CR_MINC
|
||||
* - @p STM32_DMA_CR_PINC
|
||||
* - @p STM32_DMA_CR_DIR_M2M
|
||||
* - @p STM32_DMA_CR_EN
|
||||
* .
|
||||
* @param[in] src source address
|
||||
* @param[in] dst destination address
|
||||
* @param[in] n number of data units to copy
|
||||
*/
|
||||
#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
|
||||
dmaStreamSetPeripheral(dmastp, src); \
|
||||
dmaStreamSetMemory0(dmastp, dst); \
|
||||
dmaStreamSetTransactionSize(dmastp, n); \
|
||||
dmaStreamSetMode(dmastp, (mode) | \
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
|
||||
STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polled wait for DMA transfer end.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*/
|
||||
#define dmaWaitCompletion(dmastp) { \
|
||||
while ((dmastp)->channel->CNDTR > 0) \
|
||||
; \
|
||||
dmaStreamDisable(dmastp); \
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
extern const stm32_dma_stream_t __stm32_dma_streams[STM32_DMA_STREAMS];
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void dmaInit(void);
|
||||
bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
|
||||
uint32_t priority,
|
||||
stm32_dmaisr_t func,
|
||||
void *param);
|
||||
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _STM32_DMA_H_ */
|
||||
|
||||
/** @} */
|
Loading…
Reference in New Issue