QUADSPIv2 fixes.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14460 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-06-03 08:39:29 +00:00
parent 369e1b6a5f
commit 128da3d596
13 changed files with 51 additions and 10 deletions

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@ -39,6 +39,7 @@
#define STM32H755_MCUCONF
#define STM32H747_MCUCONF
#define STM32H757_MCUCONF
#define STM32H750_MCUCONF
/*
* General settings.
@ -491,6 +492,7 @@
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_SET_CR_SSHIFT TRUE
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")

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@ -39,6 +39,7 @@
#define STM32H755_MCUCONF
#define STM32H747_MCUCONF
#define STM32H757_MCUCONF
#define STM32H750_MCUCONF
/*
* General settings.
@ -491,6 +492,7 @@
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_SET_CR_SSHIFT TRUE
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")

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@ -198,7 +198,7 @@
* @brief Enables the WSPI subsystem.
*/
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
#define HAL_USE_WSPI FALSE
#define HAL_USE_WSPI TRUE
#endif
/*===========================================================================*/

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@ -39,6 +39,7 @@
#define STM32H755_MCUCONF
#define STM32H747_MCUCONF
#define STM32H757_MCUCONF
#define STM32H750_MCUCONF
/*
* General settings.
@ -491,6 +492,7 @@
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_SET_CR_SSHIFT TRUE
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")

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@ -39,6 +39,7 @@
#define STM32H755_MCUCONF
#define STM32H747_MCUCONF
#define STM32H757_MCUCONF
#define STM32H750_MCUCONF
/*
* General settings.
@ -491,6 +492,7 @@
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_SET_CR_SSHIFT TRUE
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")

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@ -15,7 +15,7 @@
*/
/**
* @file QUADSPIv2//hal_wspi_lld.c
* @file QUADSPIv2/hal_wspi_lld.c
* @brief STM32 WSPI subsystem low level driver source.
*
* @addtogroup WSPI
@ -73,6 +73,13 @@ static void wspi_lld_serve_mdma_interrupt(WSPIDriver *wspip, uint32_t flags) {
(void)wspip;
(void)flags;
if (wspip->state == WSPI_RECEIVE) {
/* Portable WSPI ISR code defined in the high level driver, note, it is
a macro.*/
_wspi_isr_code(wspip);
mdmaChannelDisableX(wspip->mdma);
}
/* DMA errors handling.*/
#if defined(STM32_WSPI_MDMA_ERROR_HOOK)
if ((flags & STM32_MDMA_CISR_TEIF) != 0) {
@ -127,8 +134,14 @@ void wspi_lld_start(WSPIDriver *wspip) {
/* WSPI setup and enable.*/
wspip->qspi->DCR = wspip->config->dcr;
#if STM32_WSPI_SET_CR_SSHIFT
wspip->qspi->CR = ((STM32_WSPI_QUADSPI1_PRESCALER_VALUE - 1U) << 24U) |
QUADSPI_CR_TCIE | QUADSPI_CR_DMAEN | QUADSPI_CR_SSHIFT |
QUADSPI_CR_EN;
#else
wspip->qspi->CR = ((STM32_WSPI_QUADSPI1_PRESCALER_VALUE - 1U) << 24U) |
QUADSPI_CR_TCIE | QUADSPI_CR_DMAEN | QUADSPI_CR_EN;
#endif
wspip->qspi->FCR = QUADSPI_FCR_CTEF | QUADSPI_FCR_CTCF |
QUADSPI_FCR_CSMF | QUADSPI_FCR_CTOF;
}
@ -221,14 +234,14 @@ void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,
STM32_MDMA_CTCR_SINC_INC; /* Source incremented. */
uint32_t ccr = STM32_MDMA_CCR_PL(STM32_WSPI_QUADSPI1_MDMA_PRIORITY) |
STM32_MDMA_CCR_CTCIE | /* On transfer complete.*/
STM32_MDMA_CCR_TCIE; /* On transfer error. */
STM32_MDMA_CCR_TEIE; /* On transfer error. */
/* MDMA initializations.*/
mdmaChannelSetSourceX(wspip->mdma, txbuf);
mdmaChannelSetDestinationX(wspip->mdma, &wspip->qspi->DR);
mdmaChannelSetTransactionSizeX(wspip->mdma, n, 0, 0);
mdmaChannelSetModeX(wspip->mdma, ctcr, ccr);
mdmaChannelSetTrigModeX(wspip->mdma, MDMA_REQUEST_QUADSPI_TC);
mdmaChannelSetTrigModeX(wspip->mdma, MDMA_REQUEST_QUADSPI_FIFO_TH);
wspip->qspi->DLR = n - 1;
wspip->qspi->ABR = cmdp->alt;
@ -266,15 +279,14 @@ void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,
STM32_MDMA_CTCR_SINC_FIXED; /* Source fixed. */
uint32_t ccr = STM32_MDMA_CCR_PL(STM32_WSPI_QUADSPI1_MDMA_PRIORITY) |
STM32_MDMA_CCR_CTCIE | /* On transfer complete.*/
STM32_MDMA_CCR_TCIE; /* On transfer error. */
STM32_MDMA_CCR_TEIE; /* On transfer error. */
/* MDMA initializations.*/
mdmaChannelSetSourceX(wspip->mdma, &wspip->qspi->DR);
mdmaChannelSetDestinationX(wspip->mdma, rxbuf);
mdmaChannelSetTransactionSizeX(wspip->mdma, n, 0, 0);
mdmaChannelSetModeX(wspip->mdma, ctcr, ccr);
mdmaChannelSetTrigModeX(wspip->mdma, MDMA_REQUEST_QUADSPI_TC);
mdmaChannelSetTrigModeX(wspip->mdma, MDMA_REQUEST_QUADSPI_FIFO_TH);
wspip->qspi->DLR = n - 1;
wspip->qspi->ABR = cmdp->alt;
@ -353,12 +365,14 @@ void wspi_lld_serve_interrupt(WSPIDriver *wspip) {
wspip->qspi->FCR = QUADSPI_FCR_CTEF | QUADSPI_FCR_CTCF |
QUADSPI_FCR_CSMF | QUADSPI_FCR_CTOF;
if (wspip->state == WSPI_SEND) {
/* Portable WSPI ISR code defined in the high level driver, note, it is
a macro.*/
_wspi_isr_code(wspip);
mdmaChannelDisableX(wspip->mdma);
}
}
#endif /* HAL_USE_WSPI */

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@ -149,6 +149,13 @@
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#endif
/**
* @brief QUADSPI1 CR_SSHIFT enforcing.
*/
#if !defined(STM32_WSPI_SET_CR_SSHIFT) || defined(__DOXYGEN__)
#define STM32_WSPI_SET_CR_SSHIFT TRUE
#endif
/**
* @brief QUADSPI1 MDMA priority (0..3|lowest..highest).
*/

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@ -39,6 +39,7 @@
#define STM32H755_MCUCONF
#define STM32H747_MCUCONF
#define STM32H757_MCUCONF
#define STM32H750_MCUCONF
/*
* General settings.
@ -491,6 +492,7 @@
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_SET_CR_SSHIFT TRUE
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")

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@ -39,6 +39,7 @@
#define STM32H755_MCUCONF
#define STM32H747_MCUCONF
#define STM32H757_MCUCONF
#define STM32H750_MCUCONF
/*
* General settings.
@ -491,6 +492,7 @@
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_SET_CR_SSHIFT TRUE
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")

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@ -39,6 +39,7 @@
#define STM32H755_MCUCONF
#define STM32H747_MCUCONF
#define STM32H757_MCUCONF
#define STM32H750_MCUCONF
/*
* General settings.
@ -491,6 +492,7 @@
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_SET_CR_SSHIFT TRUE
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")

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@ -39,6 +39,7 @@
#define STM32H755_MCUCONF
#define STM32H747_MCUCONF
#define STM32H757_MCUCONF
#define STM32H750_MCUCONF
/*
* General settings.
@ -491,6 +492,7 @@
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_SET_CR_SSHIFT TRUE
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")

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@ -39,6 +39,7 @@
#define STM32H755_MCUCONF
#define STM32H747_MCUCONF
#define STM32H757_MCUCONF
#define STM32H750_MCUCONF
/*
* General settings.
@ -491,6 +492,7 @@
*/
#define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
#define STM32_WSPI_SET_CR_SSHIFT TRUE
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")

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@ -50,6 +50,7 @@
#define STM32H755_MCUCONF
#define STM32H747_MCUCONF
#define STM32H757_MCUCONF
#define STM32H750_MCUCONF
/*
* General settings.
@ -502,6 +503,7 @@
*/
#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_QUADSPI1_PRESCALER_VALUE!"1"}
#define STM32_WSPI_SET_CR_SSHIFT ${doc.STM32_WSPI_SET_CR_SSHIFT!"TRUE"}
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL ${doc.STM32_WSPI_QUADSPI1_MDMA_CHANNEL!"STM32_MDMA_CHANNEL_ID_ANY"}
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY ${doc.STM32_WSPI_QUADSPI1_MDMA_PRIORITY!"1"}
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) ${doc.STM32_WSPI_MDMA_ERROR_HOOK!"osalSysHalt(\"MDMA failure\")"}