QUADSPIv2 fixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14460 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -39,6 +39,7 @@
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#define STM32H755_MCUCONF
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#define STM32H747_MCUCONF
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#define STM32H757_MCUCONF
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#define STM32H750_MCUCONF
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/*
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* General settings.
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@ -491,6 +492,7 @@
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#define STM32_WSPI_SET_CR_SSHIFT TRUE
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#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
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#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
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#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
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@ -39,6 +39,7 @@
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#define STM32H755_MCUCONF
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#define STM32H747_MCUCONF
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#define STM32H757_MCUCONF
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#define STM32H750_MCUCONF
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/*
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* General settings.
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@ -491,6 +492,7 @@
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#define STM32_WSPI_SET_CR_SSHIFT TRUE
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#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
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#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
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#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
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@ -198,7 +198,7 @@
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* @brief Enables the WSPI subsystem.
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*/
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#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
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#define HAL_USE_WSPI FALSE
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#define HAL_USE_WSPI TRUE
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#endif
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/*===========================================================================*/
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@ -39,6 +39,7 @@
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#define STM32H755_MCUCONF
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#define STM32H747_MCUCONF
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#define STM32H757_MCUCONF
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#define STM32H750_MCUCONF
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/*
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* General settings.
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@ -491,6 +492,7 @@
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#define STM32_WSPI_SET_CR_SSHIFT TRUE
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#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
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#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
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#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
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@ -39,6 +39,7 @@
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#define STM32H755_MCUCONF
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#define STM32H747_MCUCONF
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#define STM32H757_MCUCONF
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#define STM32H750_MCUCONF
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/*
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* General settings.
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@ -491,6 +492,7 @@
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#define STM32_WSPI_SET_CR_SSHIFT TRUE
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#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
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#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
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#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
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@ -15,7 +15,7 @@
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*/
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/**
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* @file QUADSPIv2//hal_wspi_lld.c
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* @file QUADSPIv2/hal_wspi_lld.c
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* @brief STM32 WSPI subsystem low level driver source.
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*
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* @addtogroup WSPI
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@ -73,6 +73,13 @@ static void wspi_lld_serve_mdma_interrupt(WSPIDriver *wspip, uint32_t flags) {
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(void)wspip;
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(void)flags;
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if (wspip->state == WSPI_RECEIVE) {
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/* Portable WSPI ISR code defined in the high level driver, note, it is
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a macro.*/
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_wspi_isr_code(wspip);
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mdmaChannelDisableX(wspip->mdma);
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}
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/* DMA errors handling.*/
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#if defined(STM32_WSPI_MDMA_ERROR_HOOK)
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if ((flags & STM32_MDMA_CISR_TEIF) != 0) {
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@ -127,8 +134,14 @@ void wspi_lld_start(WSPIDriver *wspip) {
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/* WSPI setup and enable.*/
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wspip->qspi->DCR = wspip->config->dcr;
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#if STM32_WSPI_SET_CR_SSHIFT
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wspip->qspi->CR = ((STM32_WSPI_QUADSPI1_PRESCALER_VALUE - 1U) << 24U) |
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QUADSPI_CR_TCIE | QUADSPI_CR_DMAEN | QUADSPI_CR_SSHIFT |
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QUADSPI_CR_EN;
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#else
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wspip->qspi->CR = ((STM32_WSPI_QUADSPI1_PRESCALER_VALUE - 1U) << 24U) |
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QUADSPI_CR_TCIE | QUADSPI_CR_DMAEN | QUADSPI_CR_EN;
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#endif
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wspip->qspi->FCR = QUADSPI_FCR_CTEF | QUADSPI_FCR_CTCF |
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QUADSPI_FCR_CSMF | QUADSPI_FCR_CTOF;
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}
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@ -221,14 +234,14 @@ void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,
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STM32_MDMA_CTCR_SINC_INC; /* Source incremented. */
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uint32_t ccr = STM32_MDMA_CCR_PL(STM32_WSPI_QUADSPI1_MDMA_PRIORITY) |
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STM32_MDMA_CCR_CTCIE | /* On transfer complete.*/
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STM32_MDMA_CCR_TCIE; /* On transfer error. */
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STM32_MDMA_CCR_TEIE; /* On transfer error. */
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/* MDMA initializations.*/
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mdmaChannelSetSourceX(wspip->mdma, txbuf);
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mdmaChannelSetDestinationX(wspip->mdma, &wspip->qspi->DR);
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mdmaChannelSetTransactionSizeX(wspip->mdma, n, 0, 0);
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mdmaChannelSetModeX(wspip->mdma, ctcr, ccr);
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mdmaChannelSetTrigModeX(wspip->mdma, MDMA_REQUEST_QUADSPI_TC);
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mdmaChannelSetTrigModeX(wspip->mdma, MDMA_REQUEST_QUADSPI_FIFO_TH);
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wspip->qspi->DLR = n - 1;
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wspip->qspi->ABR = cmdp->alt;
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@ -266,15 +279,14 @@ void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,
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STM32_MDMA_CTCR_SINC_FIXED; /* Source fixed. */
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uint32_t ccr = STM32_MDMA_CCR_PL(STM32_WSPI_QUADSPI1_MDMA_PRIORITY) |
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STM32_MDMA_CCR_CTCIE | /* On transfer complete.*/
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STM32_MDMA_CCR_TCIE; /* On transfer error. */
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STM32_MDMA_CCR_TEIE; /* On transfer error. */
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/* MDMA initializations.*/
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mdmaChannelSetSourceX(wspip->mdma, &wspip->qspi->DR);
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mdmaChannelSetDestinationX(wspip->mdma, rxbuf);
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mdmaChannelSetTransactionSizeX(wspip->mdma, n, 0, 0);
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mdmaChannelSetModeX(wspip->mdma, ctcr, ccr);
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mdmaChannelSetTrigModeX(wspip->mdma, MDMA_REQUEST_QUADSPI_TC);
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mdmaChannelSetTrigModeX(wspip->mdma, MDMA_REQUEST_QUADSPI_FIFO_TH);
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wspip->qspi->DLR = n - 1;
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wspip->qspi->ABR = cmdp->alt;
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@ -353,12 +365,14 @@ void wspi_lld_serve_interrupt(WSPIDriver *wspip) {
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wspip->qspi->FCR = QUADSPI_FCR_CTEF | QUADSPI_FCR_CTCF |
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QUADSPI_FCR_CSMF | QUADSPI_FCR_CTOF;
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if (wspip->state == WSPI_SEND) {
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/* Portable WSPI ISR code defined in the high level driver, note, it is
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a macro.*/
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_wspi_isr_code(wspip);
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mdmaChannelDisableX(wspip->mdma);
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}
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}
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#endif /* HAL_USE_WSPI */
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@ -149,6 +149,13 @@
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif
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/**
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* @brief QUADSPI1 CR_SSHIFT enforcing.
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*/
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#if !defined(STM32_WSPI_SET_CR_SSHIFT) || defined(__DOXYGEN__)
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#define STM32_WSPI_SET_CR_SSHIFT TRUE
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#endif
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/**
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* @brief QUADSPI1 MDMA priority (0..3|lowest..highest).
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*/
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#define STM32H755_MCUCONF
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#define STM32H747_MCUCONF
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#define STM32H757_MCUCONF
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#define STM32H750_MCUCONF
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/*
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* General settings.
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#define STM32_WSPI_SET_CR_SSHIFT TRUE
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#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
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#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
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#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
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#define STM32H755_MCUCONF
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#define STM32H747_MCUCONF
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#define STM32H757_MCUCONF
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#define STM32H750_MCUCONF
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/*
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* General settings.
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#define STM32_WSPI_SET_CR_SSHIFT TRUE
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#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
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#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
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#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
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#define STM32H755_MCUCONF
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#define STM32H747_MCUCONF
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#define STM32H757_MCUCONF
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#define STM32H750_MCUCONF
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/*
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* General settings.
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#define STM32_WSPI_SET_CR_SSHIFT TRUE
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#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
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#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
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#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
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#define STM32H755_MCUCONF
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#define STM32H747_MCUCONF
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#define STM32H757_MCUCONF
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#define STM32H750_MCUCONF
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/*
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* General settings.
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#define STM32_WSPI_SET_CR_SSHIFT TRUE
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#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
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#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
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#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
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#define STM32H755_MCUCONF
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#define STM32H747_MCUCONF
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#define STM32H757_MCUCONF
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#define STM32H750_MCUCONF
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/*
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* General settings.
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#define STM32_WSPI_SET_CR_SSHIFT TRUE
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#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
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#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
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#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure")
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@ -50,6 +50,7 @@
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#define STM32H755_MCUCONF
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#define STM32H747_MCUCONF
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#define STM32H757_MCUCONF
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#define STM32H750_MCUCONF
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/*
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* General settings.
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*/
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#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_QUADSPI1_PRESCALER_VALUE!"1"}
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#define STM32_WSPI_SET_CR_SSHIFT ${doc.STM32_WSPI_SET_CR_SSHIFT!"TRUE"}
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#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL ${doc.STM32_WSPI_QUADSPI1_MDMA_CHANNEL!"STM32_MDMA_CHANNEL_ID_ANY"}
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#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY ${doc.STM32_WSPI_QUADSPI1_MDMA_PRIORITY!"1"}
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#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) ${doc.STM32_WSPI_MDMA_ERROR_HOOK!"osalSysHalt(\"MDMA failure\")"}
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