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STM32 library integration improvements. Updated to the latest version 2.03. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@744 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2009-02-08 11:07:35 +00:00
parent 330944e658
commit 1aa7798d0e
9 changed files with 7995 additions and 1178 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
demos/ARMCM3-STM32F103-GCC/Makefile
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@ -83,7 +83,8 @@ ASMSRC = ../../ports/ARMCM3/crt0.s ../../ports/ARMCM3-STM32F103/vectors.s
# List all user directories here
UINCDIR = ../../src/include ../../src/lib ../../test \
../../ports/ARMCM3 ../../ports/ARMCM3-STM32F103
../../ports/ARMCM3 ../../ports/ARMCM3-STM32F103 \
./stm32lib/inc
# List the user directory to look for the libraries here
ULIBDIR =

2
demos/ARMCM3-STM32F103-GCC/board.h
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@ -27,7 +27,7 @@
#undef FALSE
#undef TRUE
#ifndef __STM32F10x_MAP_H
#include "stm32lib/stm32f10x_map.h"
#include "stm32f10x_map.h"
#endif
#define FALSE 0
#define TRUE (!FALSE)

18
demos/ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h → demos/ARMCM3-STM32F103-GCC/stm32lib/inc/cortexm3_macro.h
View File

@ -1,15 +1,15 @@
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : cortexm3_macro.h
* Author : MCD Application Team
* Version : V1.0
* Date : 10/08/2007
* Version : V2.0.3
* Date : 09/22/2008
* Description : Header file for cortexm3_macro.s.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
@ -37,10 +37,12 @@ u32 __MRS_PSP(void);
void __MSR_PSP(u32 TopOfProcessStack);
u32 __MRS_MSP(void);
void __MSR_MSP(u32 TopOfMainStack);
void __SETPRIMASK(void);
void __RESETPRIMASK(void);
void __SETFAULTMASK(void);
void __SETPRIMASK(void);
u32 __READ_PRIMASK(void);
void __RESETFAULTMASK(void);
void __SETFAULTMASK(void);
u32 __READ_FAULTMASK(void);
void __BASEPRICONFIG(u32 NewPriority);
u32 __GetBASEPRI(void);
u16 __REV_HalfWord(u16 Data);
@ -48,4 +50,4 @@ u32 __REV_Word(u32 Data);
#endif /* __CORTEXM3_MACRO_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

136
demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h → demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h
View File

@ -1,15 +1,15 @@
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_conf.h
* Author : MCD Application Team
* Version : V1.0
* Date : 10/08/2007
* Version : V2.0.3
* Date : 09/22/2008
* Description : Library configuration file.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
@ -25,32 +25,47 @@
/* Uncomment the line below to compile the library in DEBUG mode, this will expanse
the "assert_param" macro in the firmware library code (see "Exported macro"
section below) */
/* #define DEBUG 1*/
/*#define DEBUG 1*/
/* Comment the line below to disable the specific peripheral inclusion */
/************************************* ADC ************************************/
//#define _ADC
//#define _ADC1
//#define _ADC2
//#define _ADC
//#define _ADC1
//#define _ADC2
//#define _ADC3
/************************************* BKP ************************************/
//#define _BKP
//#define _BKP
/************************************* CAN ************************************/
//#define _CAN
//#define _CAN
/************************************* CRC ************************************/
//#define _CRC
/************************************* DAC ************************************/
//#define _DAC
/************************************* DBGMCU *********************************/
//#define _DBGMCU
/************************************* DMA ************************************/
//#define _DMA
//#define _DMA_Channel1
//#define _DMA_Channel2
//#define _DMA_Channel3
//#define _DMA_Channel4
//#define _DMA_Channel5
//#define _DMA_Channel6
//#define _DMA_Channel7
//#define _DMA
//#define _DMA1_Channel1
//#define _DMA1_Channel2
//#define _DMA1_Channel3
//#define _DMA1_Channel4
//#define _DMA1_Channel5
//#define _DMA1_Channel6
//#define _DMA1_Channel7
//#define _DMA2_Channel1
//#define _DMA2_Channel2
//#define _DMA2_Channel3
//#define _DMA2_Channel4
//#define _DMA2_Channel5
/************************************* EXTI ***********************************/
//#define _EXTI
//#define _EXTI
/************************************* FLASH and Option Bytes *****************/
#define _FLASH
@ -59,65 +74,82 @@
are enabled */
/* #define _FLASH_PROG */
/************************************* FSMC ***********************************/
//#define _FSMC
/************************************* GPIO ***********************************/
#define _GPIO
#define _GPIOA
#define _GPIOB
#define _GPIOC
#define _GPIOD
//#define _GPIOE
//#define _AFIO
#define _GPIO
#define _GPIOA
#define _GPIOB
#define _GPIOC
#define _GPIOD
//#define _GPIOE
//#define _GPIOF
//#define _GPIOG
//#define _AFIO
/************************************* I2C ************************************/
//#define _I2C
//#define _I2C1
//#define _I2C2
//#define _I2C
//#define _I2C1
//#define _I2C2
/************************************* IWDG ***********************************/
//#define _IWDG
//#define _IWDG
/************************************* NVIC ***********************************/
//#define _NVIC
//#define _NVIC
/************************************* PWR ************************************/
//#define _PWR
//#define _PWR
/************************************* RCC ************************************/
#define _RCC
#define _RCC
/************************************* RTC ************************************/
//#define _RTC
//#define _RTC
/************************************* SDIO ***********************************/
//#define _SDIO
/************************************* SPI ************************************/
//#define _SPI
//#define _SPI1
//#define _SPI2
//#define _SPI
//#define _SPI1
//#define _SPI2
//#define _SPI3
/************************************* SysTick ********************************/
//#define _SysTick
/************************************* TIM1 ***********************************/
//#define _TIM1
//#define _SysTick
/************************************* TIM ************************************/
//#define _TIM
//#define _TIM2
//#define _TIM3
//#define _TIM4
//#define _TIM
//#define _TIM1
//#define _TIM2
//#define _TIM3
//#define _TIM4
//#define _TIM5
//#define _TIM6
//#define _TIM7
//#define _TIM8
/************************************* USART **********************************/
#define _USART
#define _USART1
#define _USART2
#define _USART3
#define _USART
#define _USART1
#define _USART2
#define _USART3
//#define _UART4
//#define _UART5
/************************************* WWDG ***********************************/
//#define _WWDG
//#define _WWDG
/* In the following line adjust the value of External High Speed oscillator (HSE)
used in your application */
#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/
/* In the following line adjust the External High Speed oscillator (HSE) Startup
Timeout value */
#define HSEStartUp_TimeOut ((u16)0x0500) /* Time out for HSE start up */
/* Exported macro ------------------------------------------------------------*/
#ifdef DEBUG
/*******************************************************************************
@ -139,4 +171,4 @@
#endif /* __STM32F10x_CONF_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

7603
demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_map.h Normal file
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File diff suppressed because it is too large Load Diff

287
demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_nvic.h Normal file
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@ -0,0 +1,287 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_nvic.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* NVIC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_NVIC_H
#define __STM32F10x_NVIC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* NVIC Init Structure definition */
typedef struct
{
u8 NVIC_IRQChannel;
u8 NVIC_IRQChannelPreemptionPriority;
u8 NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* IRQ Channels --------------------------------------------------------------*/
#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */
#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */
#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */
#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */
#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */
#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */
#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */
#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */
#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */
#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */
#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */
#define DMA1_Channel1_IRQChannel ((u8)0x0B) /* DMA1 Channel 1 global Interrupt */
#define DMA1_Channel2_IRQChannel ((u8)0x0C) /* DMA1 Channel 2 global Interrupt */
#define DMA1_Channel3_IRQChannel ((u8)0x0D) /* DMA1 Channel 3 global Interrupt */
#define DMA1_Channel4_IRQChannel ((u8)0x0E) /* DMA1 Channel 4 global Interrupt */
#define DMA1_Channel5_IRQChannel ((u8)0x0F) /* DMA1 Channel 5 global Interrupt */
#define DMA1_Channel6_IRQChannel ((u8)0x10) /* DMA1 Channel 6 global Interrupt */
#define DMA1_Channel7_IRQChannel ((u8)0x11) /* DMA1 Channel 7 global Interrupt */
#define ADC1_2_IRQChannel ((u8)0x12) /* ADC1 et ADC2 global Interrupt */
#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */
#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */
#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */
#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */
#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */
#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */
#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */
#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */
#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */
#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */
#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */
#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */
#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */
#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */
#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */
#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */
#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */
#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */
#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */
#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */
#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */
#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */
#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */
#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */
#define TIM8_BRK_IRQChannel ((u8)0x2B) /* TIM8 Break Interrupt */
#define TIM8_UP_IRQChannel ((u8)0x2C) /* TIM8 Update Interrupt */
#define TIM8_TRG_COM_IRQChannel ((u8)0x2D) /* TIM8 Trigger and Commutation Interrupt */
#define TIM8_CC_IRQChannel ((u8)0x2E) /* TIM8 Capture Compare Interrupt */
#define ADC3_IRQChannel ((u8)0x2F) /* ADC3 global Interrupt */
#define FSMC_IRQChannel ((u8)0x30) /* FSMC global Interrupt */
#define SDIO_IRQChannel ((u8)0x31) /* SDIO global Interrupt */
#define TIM5_IRQChannel ((u8)0x32) /* TIM5 global Interrupt */
#define SPI3_IRQChannel ((u8)0x33) /* SPI3 global Interrupt */
#define UART4_IRQChannel ((u8)0x34) /* UART4 global Interrupt */
#define UART5_IRQChannel ((u8)0x35) /* UART5 global Interrupt */
#define TIM6_IRQChannel ((u8)0x36) /* TIM6 global Interrupt */
#define TIM7_IRQChannel ((u8)0x37) /* TIM7 global Interrupt */
#define DMA2_Channel1_IRQChannel ((u8)0x38) /* DMA2 Channel 1 global Interrupt */
#define DMA2_Channel2_IRQChannel ((u8)0x39) /* DMA2 Channel 2 global Interrupt */
#define DMA2_Channel3_IRQChannel ((u8)0x3A) /* DMA2 Channel 3 global Interrupt */
#define DMA2_Channel4_5_IRQChannel ((u8)0x3B) /* DMA2 Channel 4 and DMA2 Channel 5 global Interrupt */
#define IS_NVIC_IRQ_CHANNEL(CHANNEL) (((CHANNEL) == WWDG_IRQChannel) || \
((CHANNEL) == PVD_IRQChannel) || \
((CHANNEL) == TAMPER_IRQChannel) || \
((CHANNEL) == RTC_IRQChannel) || \
((CHANNEL) == FLASH_IRQChannel) || \
((CHANNEL) == RCC_IRQChannel) || \
((CHANNEL) == EXTI0_IRQChannel) || \
((CHANNEL) == EXTI1_IRQChannel) || \
((CHANNEL) == EXTI2_IRQChannel) || \
((CHANNEL) == EXTI3_IRQChannel) || \
((CHANNEL) == EXTI4_IRQChannel) || \
((CHANNEL) == DMA1_Channel1_IRQChannel) || \
((CHANNEL) == DMA1_Channel2_IRQChannel) || \
((CHANNEL) == DMA1_Channel3_IRQChannel) || \
((CHANNEL) == DMA1_Channel4_IRQChannel) || \
((CHANNEL) == DMA1_Channel5_IRQChannel) || \
((CHANNEL) == DMA1_Channel6_IRQChannel) || \
((CHANNEL) == DMA1_Channel7_IRQChannel) || \
((CHANNEL) == ADC1_2_IRQChannel) || \
((CHANNEL) == USB_HP_CAN_TX_IRQChannel) || \
((CHANNEL) == USB_LP_CAN_RX0_IRQChannel) || \
((CHANNEL) == CAN_RX1_IRQChannel) || \
((CHANNEL) == CAN_SCE_IRQChannel) || \
((CHANNEL) == EXTI9_5_IRQChannel) || \
((CHANNEL) == TIM1_BRK_IRQChannel) || \
((CHANNEL) == TIM1_UP_IRQChannel) || \
((CHANNEL) == TIM1_TRG_COM_IRQChannel) || \
((CHANNEL) == TIM1_CC_IRQChannel) || \
((CHANNEL) == TIM2_IRQChannel) || \
((CHANNEL) == TIM3_IRQChannel) || \
((CHANNEL) == TIM4_IRQChannel) || \
((CHANNEL) == I2C1_EV_IRQChannel) || \
((CHANNEL) == I2C1_ER_IRQChannel) || \
((CHANNEL) == I2C2_EV_IRQChannel) || \
((CHANNEL) == I2C2_ER_IRQChannel) || \
((CHANNEL) == SPI1_IRQChannel) || \
((CHANNEL) == SPI2_IRQChannel) || \
((CHANNEL) == USART1_IRQChannel) || \
((CHANNEL) == USART2_IRQChannel) || \
((CHANNEL) == USART3_IRQChannel) || \
((CHANNEL) == EXTI15_10_IRQChannel) || \
((CHANNEL) == RTCAlarm_IRQChannel) || \
((CHANNEL) == USBWakeUp_IRQChannel) || \
((CHANNEL) == TIM8_BRK_IRQChannel) || \
((CHANNEL) == TIM8_UP_IRQChannel) || \
((CHANNEL) == TIM8_TRG_COM_IRQChannel) || \
((CHANNEL) == TIM8_CC_IRQChannel) || \
((CHANNEL) == ADC3_IRQChannel) || \
((CHANNEL) == FSMC_IRQChannel) || \
((CHANNEL) == SDIO_IRQChannel) || \
((CHANNEL) == TIM5_IRQChannel) || \
((CHANNEL) == SPI3_IRQChannel) || \
((CHANNEL) == UART4_IRQChannel) || \
((CHANNEL) == UART5_IRQChannel) || \
((CHANNEL) == TIM6_IRQChannel) || \
((CHANNEL) == TIM7_IRQChannel) || \
((CHANNEL) == DMA2_Channel1_IRQChannel) || \
((CHANNEL) == DMA2_Channel2_IRQChannel) || \
((CHANNEL) == DMA2_Channel3_IRQChannel) || \
((CHANNEL) == DMA2_Channel4_5_IRQChannel))
/* System Handlers -----------------------------------------------------------*/
#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */
#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */
#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */
#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */
#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */
#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */
#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */
#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */
#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */
#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault))
#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault) || \
((HANDLER) == SystemHandler_SVCall) || \
((HANDLER) == SystemHandler_DebugMonitor) || \
((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_SVCall))
#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_NMI) || \
((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault) || \
((HANDLER) == SystemHandler_SVCall) || \
((HANDLER) == SystemHandler_DebugMonitor) || \
((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_HardFault) || \
((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault) || \
((HANDLER) == SystemHandler_DebugMonitor))
#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault))
/* Vector Table Base ---------------------------------------------------------*/
#define NVIC_VectTab_RAM ((u32)0x20000000)
#define NVIC_VectTab_FLASH ((u32)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/* System Low Power ----------------------------------------------------------*/
#define NVIC_LP_SEVONPEND ((u8)0x10)
#define NVIC_LP_SLEEPDEEP ((u8)0x04)
#define NVIC_LP_SLEEPONEXIT ((u8)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/* Preemption Priority Group -------------------------------------------------*/
#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
#define IS_NVIC_BASE_PRI(PRI) ((PRI) < 0x10)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NVIC_DeInit(void);
void NVIC_SCBDeInit(void);
void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SETPRIMASK(void);
void NVIC_RESETPRIMASK(void);
void NVIC_SETFAULTMASK(void);
void NVIC_RESETFAULTMASK(void);
void NVIC_BASEPRICONFIG(u32 NewPriority);
u32 NVIC_GetBASEPRI(void);
u16 NVIC_GetCurrentPendingIRQChannel(void);
ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);
void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);
void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);
u16 NVIC_GetCurrentActiveHandler(void);
ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);
u32 NVIC_GetCPUID(void);
void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);
void NVIC_GenerateSystemReset(void);
void NVIC_GenerateCoreReset(void);
void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);
void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);
void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
u8 SystemHandlerSubPriority);
ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);
void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);
void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);
ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);
u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);
u32 NVIC_GetFaultAddress(u32 SystemHandler);
#endif /* __STM32F10x_NVIC_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

16
demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h → demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_type.h
View File

@ -1,16 +1,16 @@
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_type.h
* Author : MCD Application Team
* Version : V1.0
* Date : 10/08/2007
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the common data types used for the
* STM32F10x firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
@ -57,7 +57,7 @@ typedef enum {FALSE = 0, TRUE = !FALSE} bool;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) ((STATE == DISABLE) || (STATE == ENABLE))
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
@ -69,7 +69,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#define S16_MIN ((s16)-32768)
#define U32_MAX ((u32)4294967295uL)
#define S32_MAX ((s32)2147483647)
#define S32_MIN ((s32)2147483648uL)
#define S32_MIN ((s32)-2147483648)
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
@ -77,4 +77,4 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#endif /* __STM32F10x_TYPE_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

857
demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h
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@ -1,857 +0,0 @@
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_map.h
* Author : MCD Application Team
* Version : V1.0
* Date : 10/08/2007
* Description : This file contains all the peripheral register's definitions
* and memory mapping.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_MAP_H
#define __STM32F10x_MAP_H
#ifndef EXT
#define EXT extern
#endif /* EXT */
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_conf.h"
#include "stm32f10x_type.h"
#include "cortexm3_macro.h"
/* Exported types ------------------------------------------------------------*/
/******************************************************************************/
/* Peripheral registers structures */
/******************************************************************************/
/*------------------------ Analog to Digital Converter -----------------------*/
typedef struct
{
vu32 SR;
vu32 CR1;
vu32 CR2;
vu32 SMPR1;
vu32 SMPR2;
vu32 JOFR1;
vu32 JOFR2;
vu32 JOFR3;
vu32 JOFR4;
vu32 HTR;
vu32 LTR;
vu32 SQR1;
vu32 SQR2;
vu32 SQR3;
vu32 JSQR;
vu32 JDR1;
vu32 JDR2;
vu32 JDR3;
vu32 JDR4;
vu32 DR;
} ADC_TypeDef;
/*------------------------ Backup Registers ----------------------------------*/
typedef struct
{
u32 RESERVED0;
vu16 DR1;
u16 RESERVED1;
vu16 DR2;
u16 RESERVED2;
vu16 DR3;
u16 RESERVED3;
vu16 DR4;
u16 RESERVED4;
vu16 DR5;
u16 RESERVED5;
vu16 DR6;
u16 RESERVED6;
vu16 DR7;
u16 RESERVED7;
vu16 DR8;
u16 RESERVED8;
vu16 DR9;
u16 RESERVED9;
vu16 DR10;
u16 RESERVED10;
vu16 RTCCR;
u16 RESERVED11;
vu16 CR;
u16 RESERVED12;
vu16 CSR;
u16 RESERVED13;
} BKP_TypeDef;
/*------------------------ Controller Area Network ---------------------------*/
typedef struct
{
vu32 TIR;
vu32 TDTR;
vu32 TDLR;
vu32 TDHR;
} CAN_TxMailBox_TypeDef;
typedef struct
{
vu32 RIR;
vu32 RDTR;
vu32 RDLR;
vu32 RDHR;
} CAN_FIFOMailBox_TypeDef;
typedef struct
{
vu32 FR0;
vu32 FR1;
} CAN_FilterRegister_TypeDef;
typedef struct
{
vu32 MCR;
vu32 MSR;
vu32 TSR;
vu32 RF0R;
vu32 RF1R;
vu32 IER;
vu32 ESR;
vu32 BTR;
u32 RESERVED0[88];
CAN_TxMailBox_TypeDef sTxMailBox[3];
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
u32 RESERVED1[12];
vu32 FMR;
vu32 FM0R;
u32 RESERVED2[1];
vu32 FS0R;
u32 RESERVED3[1];
vu32 FFA0R;
u32 RESERVED4[1];
vu32 FA0R;
u32 RESERVED5[8];
CAN_FilterRegister_TypeDef sFilterRegister[14];
} CAN_TypeDef;
/*------------------------ DMA Controller ------------------------------------*/
typedef struct
{
vu32 CCR;
vu32 CNDTR;
vu32 CPAR;
vu32 CMAR;
} DMA_Channel_TypeDef;
typedef struct
{
vu32 ISR;
vu32 IFCR;
} DMA_TypeDef;
/*------------------------ External Interrupt/Event Controller ---------------*/
typedef struct
{
vu32 IMR;
vu32 EMR;
vu32 RTSR;
vu32 FTSR;
vu32 SWIER;
vu32 PR;
} EXTI_TypeDef;
/*------------------------ FLASH and Option Bytes Registers ------------------*/
typedef struct
{
vu32 ACR;
vu32 KEYR;
vu32 OPTKEYR;
vu32 SR;
vu32 CR;
vu32 AR;
vu32 RESERVED;
vu32 OBR;
vu32 WRPR;
} FLASH_TypeDef;
typedef struct
{
vu16 RDP;
vu16 USER;
vu16 Data0;
vu16 Data1;
vu16 WRP0;
vu16 WRP1;
vu16 WRP2;
vu16 WRP3;
} OB_TypeDef;
/*------------------------ General Purpose and Alternate Function IO ---------*/
typedef struct
{
vu32 CRL;
vu32 CRH;
vu32 IDR;
vu32 ODR;
vu32 BSRR;
vu32 BRR;
vu32 LCKR;
} GPIO_TypeDef;
typedef struct
{
vu32 EVCR;
vu32 MAPR;
vu32 EXTICR[4];
} AFIO_TypeDef;
/*------------------------ Inter-integrated Circuit Interface ----------------*/
typedef struct
{
vu16 CR1;
u16 RESERVED0;
vu16 CR2;
u16 RESERVED1;
vu16 OAR1;
u16 RESERVED2;
vu16 OAR2;
u16 RESERVED3;
vu16 DR;
u16 RESERVED4;
vu16 SR1;
u16 RESERVED5;
vu16 SR2;
u16 RESERVED6;
vu16 CCR;
u16 RESERVED7;
vu16 TRISE;
u16 RESERVED8;
} I2C_TypeDef;
/*------------------------ Independent WATCHDOG ------------------------------*/
typedef struct
{
vu32 KR;
vu32 PR;
vu32 RLR;
vu32 SR;
} IWDG_TypeDef;
/*------------------------ Nested Vectored Interrupt Controller --------------*/
typedef struct
{
vu32 ISER[2];
u32 RESERVED0[30];
vu32 ICER[2];
u32 RSERVED1[30];
vu32 ISPR[2];
u32 RESERVED2[30];
vu32 ICPR[2];
u32 RESERVED3[30];
vu32 IABR[2];
u32 RESERVED4[62];
vu32 IPR[11];
} NVIC_TypeDef;
typedef struct
{
vuc32 CPUID;
vu32 ICSR;
vu32 VTOR;
vu32 AIRCR;
vu32 SCR;
vu32 CCR;
vu32 SHPR[3];
vu32 SHCSR;
vu32 CFSR;
vu32 HFSR;
vu32 DFSR;
vu32 MMFAR;
vu32 BFAR;
vu32 AFSR;
} SCB_TypeDef;
/*------------------------ Power Control -------------------------------------*/
typedef struct
{
vu32 CR;
vu32 CSR;
} PWR_TypeDef;
/*------------------------ Reset and Clock Control ---------------------------*/
typedef struct
{
vu32 CR;
vu32 CFGR;
vu32 CIR;
vu32 APB2RSTR;
vu32 APB1RSTR;
vu32 AHBENR;
vu32 APB2ENR;
vu32 APB1ENR;
vu32 BDCR;
vu32 CSR;
} RCC_TypeDef;
/*------------------------ Real-Time Clock -----------------------------------*/
typedef struct
{
vu16 CRH;
u16 RESERVED0;
vu16 CRL;
u16 RESERVED1;
vu16 PRLH;
u16 RESERVED2;
vu16 PRLL;
u16 RESERVED3;
vu16 DIVH;
u16 RESERVED4;
vu16 DIVL;
u16 RESERVED5;
vu16 CNTH;
u16 RESERVED6;
vu16 CNTL;
u16 RESERVED7;
vu16 ALRH;
u16 RESERVED8;
vu16 ALRL;
u16 RESERVED9;
} RTC_TypeDef;
/*------------------------ Serial Peripheral Interface -----------------------*/
typedef struct
{
vu16 CR1;
u16 RESERVED0;
vu16 CR2;
u16 RESERVED1;
vu16 SR;
u16 RESERVED2;
vu16 DR;
u16 RESERVED3;
vu16 CRCPR;
u16 RESERVED4;
vu16 RXCRCR;
u16 RESERVED5;
vu16 TXCRCR;
u16 RESERVED6;
} SPI_TypeDef;
/*------------------------ SystemTick ----------------------------------------*/
typedef struct
{
vu32 CTRL;
vu32 LOAD;
vu32 VAL;
vuc32 CALIB;
} SysTick_TypeDef;
/*------------------------ Advanced Control Timer ----------------------------*/
typedef struct
{
vu16 CR1;
u16 RESERVED0;
vu16 CR2;
u16 RESERVED1;
vu16 SMCR;
u16 RESERVED2;
vu16 DIER;
u16 RESERVED3;
vu16 SR;
u16 RESERVED4;
vu16 EGR;
u16 RESERVED5;
vu16 CCMR1;
u16 RESERVED6;
vu16 CCMR2;
u16 RESERVED7;
vu16 CCER;
u16 RESERVED8;
vu16 CNT;
u16 RESERVED9;
vu16 PSC;
u16 RESERVED10;
vu16 ARR;
u16 RESERVED11;
vu16 RCR;
u16 RESERVED12;
vu16 CCR1;
u16 RESERVED13;
vu16 CCR2;
u16 RESERVED14;
vu16 CCR3;
u16 RESERVED15;
vu16 CCR4;
u16 RESERVED16;
vu16 BDTR;
u16 RESERVED17;
vu16 DCR;
u16 RESERVED18;
vu16 DMAR;
u16 RESERVED19;
} TIM1_TypeDef;
/*------------------------ General Purpose Timer -----------------------------*/
typedef struct
{
vu16 CR1;
u16 RESERVED0;
vu16 CR2;
u16 RESERVED1;
vu16 SMCR;
u16 RESERVED2;
vu16 DIER;
u16 RESERVED3;
vu16 SR;
u16 RESERVED4;
vu16 EGR;
u16 RESERVED5;
vu16 CCMR1;
u16 RESERVED6;
vu16 CCMR2;
u16 RESERVED7;
vu16 CCER;
u16 RESERVED8;
vu16 CNT;
u16 RESERVED9;
vu16 PSC;
u16 RESERVED10;
vu16 ARR;
u16 RESERVED11[3];
vu16 CCR1;
u16 RESERVED12;
vu16 CCR2;
u16 RESERVED13;
vu16 CCR3;
u16 RESERVED14;
vu16 CCR4;
u16 RESERVED15[3];
vu16 DCR;
u16 RESERVED16;
vu16 DMAR;
u16 RESERVED17;
} TIM_TypeDef;
/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/
typedef struct
{
vu16 SR;
u16 RESERVED0;
vu16 DR;
u16 RESERVED1;
vu16 BRR;
u16 RESERVED2;
vu16 CR1;
u16 RESERVED3;
vu16 CR2;
u16 RESERVED4;
vu16 CR3;
u16 RESERVED5;
vu16 GTPR;
u16 RESERVED6;
} USART_TypeDef;
/*------------------------ Window WATCHDOG -----------------------------------*/
typedef struct
{
vu32 CR;
vu32 CFR;
vu32 SR;
} WWDG_TypeDef;
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* Peripheral and SRAM base address in the alias region */
#define PERIPH_BB_BASE ((u32)0x42000000)
#define SRAM_BB_BASE ((u32)0x22000000)
/* Peripheral and SRAM base address in the bit-band region */
#define SRAM_BASE ((u32)0x20000000)
#define PERIPH_BASE ((u32)0x40000000)
/* Flash refisters base address */
#define FLASH_BASE ((u32)0x40022000)
/* Flash Option Bytes base address */
#define OB_BASE ((u32)0x1FFFF800)
/* Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define CAN_BASE (APB1PERIPH_BASE + 0x6400)
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
#define DMA_BASE (AHBPERIPH_BASE + 0x0000)
#define DMA_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
#define DMA_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
#define DMA_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
#define DMA_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
#define DMA_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
#define DMA_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
#define DMA_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
/* System Control Space memory map */
#define SCS_BASE ((u32)0xE000E000)
#define SysTick_BASE (SCS_BASE + 0x0010)
#define NVIC_BASE (SCS_BASE + 0x0100)
#define SCB_BASE (SCS_BASE + 0x0D00)
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
/*------------------------ Non Debug Mode ------------------------------------*/
#ifndef DEBUG
#ifdef _TIM2
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#endif /*_TIM2 */
#ifdef _TIM3
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#endif /*_TIM3 */
#ifdef _TIM4
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#endif /*_TIM4 */
#ifdef _RTC
#define RTC ((RTC_TypeDef *) RTC_BASE)
#endif /*_RTC */
#ifdef _WWDG
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#endif /*_WWDG */
#ifdef _IWDG
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#endif /*_IWDG */
#ifdef _SPI2
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#endif /*_SPI2 */
#ifdef _USART2
#define USART2 ((USART_TypeDef *) USART2_BASE)
#endif /*_USART2 */
#ifdef _USART3
#define USART3 ((USART_TypeDef *) USART3_BASE)
#endif /*_USART3 */
#ifdef _I2C1
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#endif /*_I2C1 */
#ifdef _I2C2
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#endif /*_I2C2 */
#ifdef _CAN
#define CAN ((CAN_TypeDef *) CAN_BASE)
#endif /*_CAN */
#ifdef _BKP
#define BKP ((BKP_TypeDef *) BKP_BASE)
#endif /*_BKP */
#ifdef _PWR
#define PWR ((PWR_TypeDef *) PWR_BASE)
#endif /*_PWR */
#ifdef _AFIO
#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
#endif /*_AFIO */
#ifdef _EXTI
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#endif /*_EXTI */
#ifdef _GPIOA
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#endif /*_GPIOA */
#ifdef _GPIOB
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#endif /*_GPIOB */
#ifdef _GPIOC
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#endif /*_GPIOC */
#ifdef _GPIOD
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#endif /*_GPIOD */
#ifdef _GPIOE
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#endif /*_GPIOE */
#ifdef _ADC1
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#endif /*_ADC1 */
#ifdef _ADC2
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#endif /*_ADC2 */
#ifdef _TIM1
#define TIM1 ((TIM1_TypeDef *) TIM1_BASE)
#endif /*_TIM1 */
#ifdef _SPI1
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#endif /*_SPI1 */
#ifdef _USART1
#define USART1 ((USART_TypeDef *) USART1_BASE)
#endif /*_USART1 */
#ifdef _DMA
#define DMA ((DMA_TypeDef *) DMA_BASE)
#endif /*_DMA */
#ifdef _DMA_Channel1
#define DMA_Channel1 ((DMA_Channel_TypeDef *) DMA_Channel1_BASE)
#endif /*_DMA_Channel1 */
#ifdef _DMA_Channel2
#define DMA_Channel2 ((DMA_Channel_TypeDef *) DMA_Channel2_BASE)
#endif /*_DMA_Channel2 */
#ifdef _DMA_Channel3
#define DMA_Channel3 ((DMA_Channel_TypeDef *) DMA_Channel3_BASE)
#endif /*_DMA_Channel3 */
#ifdef _DMA_Channel4
#define DMA_Channel4 ((DMA_Channel_TypeDef *) DMA_Channel4_BASE)
#endif /*_DMA_Channel4 */
#ifdef _DMA_Channel5
#define DMA_Channel5 ((DMA_Channel_TypeDef *) DMA_Channel5_BASE)
#endif /*_DMA_Channel5 */
#ifdef _DMA_Channel6
#define DMA_Channel6 ((DMA_Channel_TypeDef *) DMA_Channel6_BASE)
#endif /*_DMA_Channel6 */
#ifdef _DMA_Channel7
#define DMA_Channel7 ((DMA_Channel_TypeDef *) DMA_Channel7_BASE)
#endif /*_DMA_Channel7 */
#ifdef _FLASH
#define FLASH ((FLASH_TypeDef *) FLASH_BASE)
#define OB ((OB_TypeDef *) OB_BASE)
#endif /*_FLASH */
#ifdef _RCC
#define RCC ((RCC_TypeDef *) RCC_BASE)
#endif /*_RCC */
#ifdef _SysTick
#define SysTick ((SysTick_TypeDef *) SysTick_BASE)
#endif /*_SysTick */
#ifdef _NVIC
#define NVIC ((NVIC_TypeDef *) NVIC_BASE)
#define SCB ((SCB_TypeDef *) SCB_BASE)
#endif /*_NVIC */
/*------------------------ Debug Mode ----------------------------------------*/
#else /* DEBUG */
#ifdef _TIM2
EXT TIM_TypeDef *TIM2;
#endif /*_TIM2 */
#ifdef _TIM3
EXT TIM_TypeDef *TIM3;
#endif /*_TIM3 */
#ifdef _TIM4
EXT TIM_TypeDef *TIM4;
#endif /*_TIM4 */
#ifdef _RTC
EXT RTC_TypeDef *RTC;
#endif /*_RTC */
#ifdef _WWDG
EXT WWDG_TypeDef *WWDG;
#endif /*_WWDG */
#ifdef _IWDG
EXT IWDG_TypeDef *IWDG;
#endif /*_IWDG */
#ifdef _SPI2
EXT SPI_TypeDef *SPI2;
#endif /*_SPI2 */
#ifdef _USART2
EXT USART_TypeDef *USART2;
#endif /*_USART2 */
#ifdef _USART3
EXT USART_TypeDef *USART3;
#endif /*_USART3 */
#ifdef _I2C1
EXT I2C_TypeDef *I2C1;
#endif /*_I2C1 */
#ifdef _I2C2
EXT I2C_TypeDef *I2C2;
#endif /*_I2C2 */
#ifdef _CAN
EXT CAN_TypeDef *CAN;
#endif /*_CAN */
#ifdef _BKP
EXT BKP_TypeDef *BKP;
#endif /*_BKP */
#ifdef _PWR
EXT PWR_TypeDef *PWR;
#endif /*_PWR */
#ifdef _AFIO
EXT AFIO_TypeDef *AFIO;
#endif /*_AFIO */
#ifdef _EXTI
EXT EXTI_TypeDef *EXTI;
#endif /*_EXTI */
#ifdef _GPIOA
EXT GPIO_TypeDef *GPIOA;
#endif /*_GPIOA */
#ifdef _GPIOB
EXT GPIO_TypeDef *GPIOB;
#endif /*_GPIOB */
#ifdef _GPIOC
EXT GPIO_TypeDef *GPIOC;
#endif /*_GPIOC */
#ifdef _GPIOD
EXT GPIO_TypeDef *GPIOD;
#endif /*_GPIOD */
#ifdef _GPIOE
EXT GPIO_TypeDef *GPIOE;
#endif /*_GPIOE */
#ifdef _ADC1
EXT ADC_TypeDef *ADC1;
#endif /*_ADC1 */
#ifdef _ADC2
EXT ADC_TypeDef *ADC2;
#endif /*_ADC2 */
#ifdef _TIM1
EXT TIM1_TypeDef *TIM1;
#endif /*_TIM1 */
#ifdef _SPI1
EXT SPI_TypeDef *SPI1;
#endif /*_SPI1 */
#ifdef _USART1
EXT USART_TypeDef *USART1;
#endif /*_USART1 */
#ifdef _DMA
EXT DMA_TypeDef *DMA;
#endif /*_DMA */
#ifdef _DMA_Channel1
EXT DMA_Channel_TypeDef *DMA_Channel1;
#endif /*_DMA_Channel1 */
#ifdef _DMA_Channel2
EXT DMA_Channel_TypeDef *DMA_Channel2;
#endif /*_DMA_Channel2 */
#ifdef _DMA_Channel3
EXT DMA_Channel_TypeDef *DMA_Channel3;
#endif /*_DMA_Channel3 */
#ifdef _DMA_Channel4
EXT DMA_Channel_TypeDef *DMA_Channel4;
#endif /*_DMA_Channel4 */
#ifdef _DMA_Channel5
EXT DMA_Channel_TypeDef *DMA_Channel5;
#endif /*_DMA_Channel5 */
#ifdef _DMA_Channel6
EXT DMA_Channel_TypeDef *DMA_Channel6;
#endif /*_DMA_Channel6 */
#ifdef _DMA_Channel7
EXT DMA_Channel_TypeDef *DMA_Channel7;
#endif /*_DMA_Channel7 */
#ifdef _FLASH
EXT FLASH_TypeDef *FLASH;
EXT OB_TypeDef *OB;
#endif /*_FLASH */
#ifdef _RCC
EXT RCC_TypeDef *RCC;
#endif /*_RCC */
#ifdef _SysTick
EXT SysTick_TypeDef *SysTick;
#endif /*_SysTick */
#ifdef _NVIC
EXT NVIC_TypeDef *NVIC;
EXT SCB_TypeDef *SCB;
#endif /*_NVIC */
#endif /* DEBUG */
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
#endif /* __STM32F10x_MAP_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/

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@ -1,251 +0,0 @@
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_nvic.h
* Author : MCD Application Team
* Version : V1.0
* Date : 10/08/2007
* Description : This file contains all the functions prototypes for the
* NVIC firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_NVIC_H
#define __STM32F10x_NVIC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* NVIC Init Structure definition */
typedef struct
{
u8 NVIC_IRQChannel;
u8 NVIC_IRQChannelPreemptionPriority;
u8 NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* IRQ Channels --------------------------------------------------------------*/
#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */
#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */
#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */
#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */
#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */
#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */
#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */
#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */
#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */
#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */
#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */
#define DMAChannel1_IRQChannel ((u8)0x0B) /* DMA Channel 1 global Interrupt */
#define DMAChannel2_IRQChannel ((u8)0x0C) /* DMA Channel 2 global Interrupt */
#define DMAChannel3_IRQChannel ((u8)0x0D) /* DMA Channel 3 global Interrupt */
#define DMAChannel4_IRQChannel ((u8)0x0E) /* DMA Channel 4 global Interrupt */
#define DMAChannel5_IRQChannel ((u8)0x0F) /* DMA Channel 5 global Interrupt */
#define DMAChannel6_IRQChannel ((u8)0x10) /* DMA Channel 6 global Interrupt */
#define DMAChannel7_IRQChannel ((u8)0x11) /* DMA Channel 7 global Interrupt */
#define ADC_IRQChannel ((u8)0x12) /* ADC global Interrupt */
#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */
#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */
#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */
#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */
#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */
#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */
#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */
#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */
#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */
#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */
#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */
#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */
#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */
#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */
#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */
#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */
#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */
#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */
#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */
#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */
#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */
#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */
#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */
#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */
#define IS_NVIC_IRQ_CHANNEL(CHANNEL) ((CHANNEL == WWDG_IRQChannel) || \
(CHANNEL == PVD_IRQChannel) || \
(CHANNEL == TAMPER_IRQChannel) || \
(CHANNEL == RTC_IRQChannel) || \
(CHANNEL == FLASH_IRQChannel) || \
(CHANNEL == RCC_IRQChannel) || \
(CHANNEL == EXTI0_IRQChannel) || \
(CHANNEL == EXTI1_IRQChannel) || \
(CHANNEL == EXTI2_IRQChannel) || \
(CHANNEL == EXTI3_IRQChannel) || \
(CHANNEL == EXTI4_IRQChannel) || \
(CHANNEL == DMAChannel1_IRQChannel) || \
(CHANNEL == DMAChannel2_IRQChannel) || \
(CHANNEL == DMAChannel3_IRQChannel) || \
(CHANNEL == DMAChannel4_IRQChannel) || \
(CHANNEL == DMAChannel5_IRQChannel) || \
(CHANNEL == DMAChannel6_IRQChannel) || \
(CHANNEL == DMAChannel7_IRQChannel) || \
(CHANNEL == ADC_IRQChannel) || \
(CHANNEL == USB_HP_CAN_TX_IRQChannel) || \
(CHANNEL == USB_LP_CAN_RX0_IRQChannel) || \
(CHANNEL == CAN_RX1_IRQChannel) || \
(CHANNEL == CAN_SCE_IRQChannel) || \
(CHANNEL == EXTI9_5_IRQChannel) || \
(CHANNEL == TIM1_BRK_IRQChannel) || \
(CHANNEL == TIM1_UP_IRQChannel) || \
(CHANNEL == TIM1_TRG_COM_IRQChannel) || \
(CHANNEL == TIM1_CC_IRQChannel) || \
(CHANNEL == TIM2_IRQChannel) || \
(CHANNEL == TIM3_IRQChannel) || \
(CHANNEL == TIM4_IRQChannel) || \
(CHANNEL == I2C1_EV_IRQChannel) || \
(CHANNEL == I2C1_ER_IRQChannel) || \
(CHANNEL == I2C2_EV_IRQChannel) || \
(CHANNEL == I2C2_ER_IRQChannel) || \
(CHANNEL == SPI1_IRQChannel) || \
(CHANNEL == SPI2_IRQChannel) || \
(CHANNEL == USART1_IRQChannel) || \
(CHANNEL == USART2_IRQChannel) || \
(CHANNEL == USART3_IRQChannel) || \
(CHANNEL == EXTI15_10_IRQChannel) || \
(CHANNEL == RTCAlarm_IRQChannel) || \
(CHANNEL == USBWakeUp_IRQChannel))
/* System Handlers -----------------------------------------------------------*/
#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */
#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */
#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */
#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */
#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */
#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */
#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */
#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */
#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */
#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_UsageFault))
#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_UsageFault) || \
(HANDLER == SystemHandler_SVCall) || \
(HANDLER == SystemHandler_DebugMonitor) || \
(HANDLER == SystemHandler_PSV) || \
(HANDLER == SystemHandler_SysTick))
#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_SVCall))
#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_NMI) || \
(HANDLER == SystemHandler_PSV) || \
(HANDLER == SystemHandler_SysTick))
#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_PSV) || \
(HANDLER == SystemHandler_SysTick))
#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_UsageFault) || \
(HANDLER == SystemHandler_SVCall) || \
(HANDLER == SystemHandler_DebugMonitor) || \
(HANDLER == SystemHandler_PSV) || \
(HANDLER == SystemHandler_SysTick))
#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_HardFault) || \
(HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault) || \
(HANDLER == SystemHandler_UsageFault) || \
(HANDLER == SystemHandler_DebugMonitor))
#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
(HANDLER == SystemHandler_BusFault))
/* Vector Table Base ---------------------------------------------------------*/
#define NVIC_VectTab_RAM ((u32)0x20000000)
#define NVIC_VectTab_FLASH ((u32)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) ((VECTTAB == NVIC_VectTab_RAM) || \
(VECTTAB == NVIC_VectTab_FLASH))
/* System Low Power ----------------------------------------------------------*/
#define NVIC_LP_SEVONPEND ((u8)0x10)
#define NVIC_LP_SLEEPDEEP ((u8)0x04)
#define NVIC_LP_SLEEPONEXIT ((u8)0x02)
#define IS_NVIC_LP(LP) ((LP == NVIC_LP_SEVONPEND) || \
(LP == NVIC_LP_SLEEPDEEP) || \
(LP == NVIC_LP_SLEEPONEXIT))
/* Preemption Priority Group -------------------------------------------------*/
#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) ((GROUP == NVIC_PriorityGroup_0) || \
(GROUP == NVIC_PriorityGroup_1) || \
(GROUP == NVIC_PriorityGroup_2) || \
(GROUP == NVIC_PriorityGroup_3) || \
(GROUP == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) (PRIORITY < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) (PRIORITY < 0x10)
#define IS_NVIC_OFFSET(OFFSET) (OFFSET < 0x0001FFFF)
#define IS_NVIC_BASE_PRI(PRI) ((PRI > 0x00) && (PRI < 0x10))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NVIC_DeInit(void);
void NVIC_SCBDeInit(void);
void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SETPRIMASK(void);
void NVIC_RESETPRIMASK(void);
void NVIC_SETFAULTMASK(void);
void NVIC_RESETFAULTMASK(void);
void NVIC_BASEPRICONFIG(u32 NewPriority);
u32 NVIC_GetBASEPRI(void);
u16 NVIC_GetCurrentPendingIRQChannel(void);
ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);
void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);
void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);
u16 NVIC_GetCurrentActiveHandler(void);
ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);
u32 NVIC_GetCPUID(void);
void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);
void NVIC_GenerateSystemReset(void);
void NVIC_GenerateCoreReset(void);
void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);
void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);
void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
u8 SystemHandlerSubPriority);
ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);
void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);
void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);
ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);
u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);
u32 NVIC_GetFaultAddress(u32 SystemHandler);
#endif /* __STM32F10x_NVIC_H */
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/