debugging...
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12771 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
e69242273d
commit
2376c38058
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@ -172,7 +172,7 @@
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* @note The default is @p TRUE.
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*/
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#if !defined(CH_CFG_USE_TM)
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#define CH_CFG_USE_TM TRUE
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#define CH_CFG_USE_TM FALSE
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#endif
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/**
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@ -120,15 +120,15 @@
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* @{
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*/
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#define STM32_HSIDIV_MASK (7U << 11U) /**< HSIDIV field mask. */
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#define STM32_HSIDIV(n) ((n) << 11U) /**< HSIDIV field value. */
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#define STM32_HSIDIV_1 STM32_HSIDIV(0U)
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#define STM32_HSIDIV_2 STM32_HSIDIV(1U)
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#define STM32_HSIDIV_4 STM32_HSIDIV(2U)
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#define STM32_HSIDIV_8 STM32_HSIDIV(3U)
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#define STM32_HSIDIV_16 STM32_HSIDIV(4U)
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#define STM32_HSIDIV_32 STM32_HSIDIV(5U)
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#define STM32_HSIDIV_64 STM32_HSIDIV(6U)
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#define STM32_HSIDIV_128 STM32_HSIDIV(7U)
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#define STM32_HSIDIV_FIELD(n) ((n) << 11U) /**< HSIDIV field value. */
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#define STM32_HSIDIV_1 STM32_HSIDIV_FIELD(0U)
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#define STM32_HSIDIV_2 STM32_HSIDIV_FIELD(1U)
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#define STM32_HSIDIV_4 STM32_HSIDIV_FIELD(2U)
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#define STM32_HSIDIV_8 STM32_HSIDIV_FIELD(3U)
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#define STM32_HSIDIV_16 STM32_HSIDIV_FIELD(4U)
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#define STM32_HSIDIV_32 STM32_HSIDIV_FIELD(5U)
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#define STM32_HSIDIV_64 STM32_HSIDIV_FIELD(6U)
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#define STM32_HSIDIV_128 STM32_HSIDIV_FIELD(7U)
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/** @} */
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/**
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@ -143,24 +143,24 @@
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#define STM32_SW_LSE (4U << 0U) /**< SYSCLK source is LSE. */
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#define STM32_HPRE_MASK (15U << 8U) /**< HPRE field mask. */
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#define STM32_HPRE(n) ((n) << 8U) /**< HPRE field value. */
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#define STM32_HPRE_DIV1 STM32_HPRE(0U)
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#define STM32_HPRE_DIV2 STM32_HPRE(8U)
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#define STM32_HPRE_DIV4 STM32_HPRE(9U)
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#define STM32_HPRE_DIV8 STM32_HPRE(10U)
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#define STM32_HPRE_DIV16 STM32_HPRE(11U)
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#define STM32_HPRE_DIV64 STM32_HPRE(12U)
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#define STM32_HPRE_DIV128 STM32_HPRE(13U)
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#define STM32_HPRE_DIV256 STM32_HPRE(14U)
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#define STM32_HPRE_DIV512 STM32_HPRE(15U)
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#define STM32_HPRE_FIELD(n) ((n) << 8U) /**< HPRE field value. */
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#define STM32_HPRE_DIV1 STM32_HPRE_FIELD(0U)
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#define STM32_HPRE_DIV2 STM32_HPRE_FIELD(8U)
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#define STM32_HPRE_DIV4 STM32_HPRE_FIELD(9U)
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#define STM32_HPRE_DIV8 STM32_HPRE_FIELD(10U)
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#define STM32_HPRE_DIV16 STM32_HPRE_FIELD(11U)
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#define STM32_HPRE_DIV64 STM32_HPRE_FIELD(12U)
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#define STM32_HPRE_DIV128 STM32_HPRE_FIELD(13U)
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#define STM32_HPRE_DIV256 STM32_HPRE_FIELD(14U)
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#define STM32_HPRE_DIV512 STM32_HPRE_FIELD(15U)
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#define STM32_PPRE_MASK (7U << 12U) /**< PPRE field mask. */
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#define STM32_PPRE(n) (7U << 12U) /**< PPRE field value. */
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#define STM32_PPRE_DIV1 STM32_PPRE(0U)
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#define STM32_PPRE_DIV2 STM32_PPRE(4U)
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#define STM32_PPRE_DIV4 STM32_PPRE(5U)
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#define STM32_PPRE_DIV8 STM32_PPRE(6U)
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#define STM32_PPRE_DIV16 STM32_PPRE(7U)
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#define STM32_PPRE_FIELD(n) (7U << 12U) /**< PPRE field value. */
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#define STM32_PPRE_DIV1 STM32_PPRE_FIELD(0U)
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#define STM32_PPRE_DIV2 STM32_PPRE_FIELD(4U)
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#define STM32_PPRE_DIV4 STM32_PPRE_FIELD(5U)
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#define STM32_PPRE_DIV8 STM32_PPRE_FIELD(6U)
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#define STM32_PPRE_DIV16 STM32_PPRE_FIELD(7U)
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#define STM32_MCOSEL_MASK (7U << 24U) /**< MCOSEL field mask. */
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#define STM32_MCOSEL_NOCLOCK (0U << 24U) /**< No clock on MCO pin. */
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@ -172,15 +172,15 @@
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#define STM32_MCOSEL_LSE (7U << 24U) /**< LSE clock on MCO pin. */
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#define STM32_MCOPRE_MASK (7U << 28U) /**< MCOPRE field mask. */
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#define STM32_MCOPRE(n) ((n) << 28U)/**< MCOPRE field value */
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#define STM32_MCOPRE_DIV1 STM32_MCOPRE(0U)
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#define STM32_MCOPRE_DIV2 STM32_MCOPRE(1U)
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#define STM32_MCOPRE_DIV4 STM32_MCOPRE(2U)
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#define STM32_MCOPRE_DIV8 STM32_MCOPRE(3U)
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#define STM32_MCOPRE_DIV16 STM32_MCOPRE(4U)
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#define STM32_MCOPRE_DIV32 STM32_MCOPRE(5U)
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#define STM32_MCOPRE_DIV64 STM32_MCOPRE(6U)
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#define STM32_MCOPRE_DIV128 STM32_MCOPRE(7U)
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#define STM32_MCOPRE_FIELD(n) ((n) << 28U)/**< MCOPRE field value */
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#define STM32_MCOPRE_DIV1 STM32_MCOPRE_FIELD(0U)
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#define STM32_MCOPRE_DIV2 STM32_MCOPRE_FIELD(1U)
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#define STM32_MCOPRE_DIV4 STM32_MCOPRE_FIELD(2U)
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#define STM32_MCOPRE_DIV8 STM32_MCOPRE_FIELD(3U)
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#define STM32_MCOPRE_DIV16 STM32_MCOPRE_FIELD(4U)
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#define STM32_MCOPRE_DIV32 STM32_MCOPRE_FIELD(5U)
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#define STM32_MCOPRE_DIV64 STM32_MCOPRE_FIELD(6U)
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#define STM32_MCOPRE_DIV128 STM32_MCOPRE_FIELD(7U)
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/** @} */
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/**
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@ -257,11 +257,11 @@
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#define STM32_RNGSEL_PLLQCLK (3U << 26U) /**< RNG source is PLLQCLK. */
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#define STM32_RNGDIV_MASK (3U << 28U) /**< RNGDIV field mask. */
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#define STM32_RNGDIV(n) ((n) << 28U)/**< RNGDIV field value */
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#define STM32_RNGDIV_1 STM32_RNGDIV(0U)
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#define STM32_RNGDIV_2 STM32_RNGDIV(1U)
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#define STM32_RNGDIV_4 STM32_RNGDIV(2U)
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#define STM32_RNGDIV_8 STM32_RNGDIV(3U)
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#define STM32_RNGDIV_FIELD(n) ((n) << 28U)/**< RNGDIV field value */
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#define STM32_RNGDIV_1 STM32_RNGDIV_FIELD(0U)
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#define STM32_RNGDIV_2 STM32_RNGDIV_FIELD(1U)
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#define STM32_RNGDIV_4 STM32_RNGDIV_FIELD(2U)
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#define STM32_RNGDIV_8 STM32_RNGDIV_FIELD(3U)
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#define STM32_ADCSEL_MASK (3U << 30U) /**< ADCSEL mask. */
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#define STM32_ADCSEL_NOCLK (0U << 30U) /**< ADC source is SYSCLK. */
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@ -341,6 +341,13 @@
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#define STM32_HSE_ENABLED FALSE
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#endif
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/**
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* @brief Enables or disables the LSI clock source.
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*/
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#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
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#define STM32_LSI_ENABLED FALSE
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#endif
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/**
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* @brief Enables or disables the LSE clock source.
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*/
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@ -492,7 +499,7 @@
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* @brief I2S1 clock source.
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*/
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#if !defined(STM32_I2S1SEL) || defined(__DOXYGEN__)
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#define STM32_I2S1SEL STM32_I2S1SEL_PCLK
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#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
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#endif
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/**
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@ -753,11 +760,11 @@
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#if STM32_HSI16_ENABLED
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#else /* !STM32_HSI16_ENABLED */
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#if STM32_SW == STM32_SW_HSI16
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#if STM32_SW == STM32_SW_HSISYS
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#error "HSI16 not enabled, required by STM32_SW"
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#endif
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#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI16)
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#if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSI16)
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#error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC"
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#endif
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@ -833,12 +840,12 @@
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#error "HSE not enabled, required by STM32_SW"
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#endif
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#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
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#if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
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#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
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#endif
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#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
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((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
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((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \
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(STM32_PLLSRC == STM32_PLLSRC_HSE))
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#error "HSE not enabled, required by STM32_MCOSEL"
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#endif
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@ -958,8 +965,8 @@
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/*
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* PLL enable check.
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*/
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#if (STM32_SW == STM32_SW_PLL) || \
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(STM32_MCOSEL == STM32_MCOSEL_PLL) || \
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#if (STM32_SW == STM32_SW_PLLRCLK) || \
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(STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
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(STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK) || \
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(STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK) || \
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(STM32_RNGSEL == STM32_RNGSEL_PLLQCLK) || \
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@ -1022,8 +1029,8 @@
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/**
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* @brief STM32_PLLREN field.
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*/
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#if (STM32_SW == STM32_SW_PLL) || \
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(STM32_MCOSEL == STM32_MCOSEL_PLL) || \
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#if (STM32_SW == STM32_SW_PLLRCLK) || \
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(STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
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defined(__DOXYGEN__)
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#define STM32_PLLREN (1 << 28)
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#else
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/**
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* @brief PLL P output clock frequency.
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*/
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#if (STM32_PLLPDIV_VALUE == 0) || defined(__DOXYGEN__)
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#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
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#else
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#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLPDIV_VALUE)
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#endif
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/*
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* PLL-R output frequency range check.
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/**
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* @brief USART1 clock frequency.
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*/
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#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__)
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#if (STM32_USART1SEL == STM32_USART1SEL_PCLK) || defined(__DOXYGEN__)
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#define STM32_USART1CLK STM32_PCLK
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#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
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#define STM32_USART1CLK STM32_SYSCLK
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@ -1310,7 +1313,7 @@
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/**
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* @brief USART2 clock frequency.
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*/
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#if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__)
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#if (STM32_USART2SEL == STM32_USART2SEL_PCLK) || defined(__DOXYGEN__)
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#define STM32_USART2CLK STM32_PCLK
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#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
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#define STM32_USART2CLK STM32_SYSCLK
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@ -1325,7 +1328,7 @@
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/**
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* @brief LPUART1 clock frequency.
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*/
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#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN__)
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#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK) || defined(__DOXYGEN__)
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#define STM32_LPUART1CLK STM32_PCLK
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#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
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#define STM32_LPUART1CLK STM32_SYSCLK
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@ -1351,7 +1354,7 @@
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/**
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* @brief I2C1 clock frequency.
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*/
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#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__)
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#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK) || defined(__DOXYGEN__)
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#define STM32_I2C1CLK STM32_PCLK
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#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
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#define STM32_I2C1CLK STM32_SYSCLK
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/**
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* @brief LPTIM1 clock frequency.
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*/
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#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__)
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#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK) || defined(__DOXYGEN__)
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#define STM32_LPTIM1CLK STM32_PCLK
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#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
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#define STM32_LPTIM1CLK STM32_LSICLK
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@ -1394,7 +1397,7 @@
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/**
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* @brief LPTIM2 clock frequency.
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*/
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#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK1) || defined(__DOXYGEN__)
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#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK) || defined(__DOXYGEN__)
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#define STM32_LPTIM2CLK STM32_PCLK
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#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI
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#define STM32_LPTIM2CLK STM32_LSICLK
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* @name ISR names and numbers remapping
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* @{
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*/
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/*
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/*
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* I2C units.
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*/
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@ -258,6 +258,204 @@
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#endif /* defined(STM32G070xx) */
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/*===========================================================================*/
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/* STM32G070xx. */
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/*===========================================================================*/
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#if defined(STM32G071xx) || defined(STM32G081xx)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_HANDLER Vector70
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#define STM32_ADC1_NUMBER 12
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_HAS_CAN3 FALSE
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_DMAMUX TRUE
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#define STM32_DMA_SUPPORTS_CSELR FALSE
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#define STM32_DMA1_NUM_CHANNELS 7
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#define STM32_DMA1_CH1_HANDLER Vector64
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#define STM32_DMA1_CH23_HANDLER Vector68
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#define STM32_DMA1_CH4567_HANDLER Vector6C
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#define STM32_DMA1_CH1_NUMBER 9
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#define STM32_DMA1_CH23_NUMBER 10
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#define STM32_DMA1_CH4567_NUMBER 11
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#define STM32_DMA2_NUM_CHANNELS 0
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_LINES 33
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#define STM32_EXTI_IMR1_MASK 0xFFF80000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFFFFU
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#define STM32_EXTI_LINE01_HANDLER Vector54
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#define STM32_EXTI_LINE23_HANDLER Vector58
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#define STM32_EXTI_LINE4_15_HANDLER Vector5C
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#define STM32_EXTI_LINE16_HANDLER Vector44
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#define STM32_EXTI_LINE1921_HANDLER Vector48
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#define STM32_EXTI_LINE01_NUMBER 5
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#define STM32_EXTI_LINE23_NUMBER 6
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#define STM32_EXTI_LINE4_15_NUMBER 7
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#define STM32_EXTI_LINE16_NUMBER 1
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#define STM32_EXTI_LINE1921_NUMBER 2
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \
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RCC_IOPENR_GPIOBEN | \
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RCC_IOPENR_GPIOCEN | \
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RCC_IOPENR_GPIODEN | \
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RCC_IOPENR_GPIOFEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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#define STM32_HAS_I2C3 FALSE
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#define STM32_HAS_I2C4 FALSE
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/* OCTOSPI attributes.*/
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#define STM32_HAS_OCTOSPI1 FALSE
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#define STM32_HAS_OCTOSPI2 FALSE
|
||||
|
||||
/* QUADSPI attributes.*/
|
||||
#define STM32_HAS_QUADSPI1 FALSE
|
||||
|
||||
/* SDMMC attributes.*/
|
||||
#define STM32_HAS_SDMMC1 FALSE
|
||||
#define STM32_HAS_SDMMC2 FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_SUPPORTS_I2S TRUE
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI2_SUPPORTS_I2S FALSE
|
||||
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
#define STM32_HAS_SPI5 FALSE
|
||||
#define STM32_HAS_SPI6 FALSE
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_TIM_MAX_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_TIM1_IS_32BITS FALSE
|
||||
#define STM32_TIM1_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_TIM2_IS_32BITS TRUE
|
||||
#define STM32_TIM2_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_TIM3_IS_32BITS FALSE
|
||||
#define STM32_TIM3_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_TIM6_IS_32BITS FALSE
|
||||
#define STM32_TIM6_CHANNELS 0
|
||||
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_TIM7_IS_32BITS FALSE
|
||||
#define STM32_TIM7_CHANNELS 0
|
||||
|
||||
#define STM32_HAS_TIM14 TRUE
|
||||
#define STM32_TIM14_IS_32BITS FALSE
|
||||
#define STM32_TIM14_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_TIM15_IS_32BITS FALSE
|
||||
#define STM32_TIM15_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
#define STM32_HAS_TIM20 FALSE
|
||||
#define STM32_HAS_TIM21 FALSE
|
||||
#define STM32_HAS_TIM22 FALSE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_HAS_UART4 TRUE
|
||||
#define STM32_HAS_LPUART1 TRUE
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_HAS_UART7 FALSE
|
||||
#define STM32_HAS_UART8 FALSE
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
#define STM32_HAS_USB FALSE
|
||||
|
||||
/* IWDG attributes.*/
|
||||
#define STM32_HAS_IWDG TRUE
|
||||
#define STM32_IWDG_IS_WINDOWED TRUE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
|
||||
/* CRC attributes.*/
|
||||
#define STM32_HAS_CRC FALSE
|
||||
|
||||
/* DCMI attributes.*/
|
||||
#define STM32_HAS_DCMI FALSE
|
||||
|
||||
#endif /* defined(STM32G070xx) */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* STM32_REGISTRY_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue