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STM32WL missing folder 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14179 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
cinsights 2021-04-15 00:54:36 +00:00
parent 7a01e980a8
commit 272eae6537
10 changed files with 4335 additions and 0 deletions
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539
os/hal/ports/STM32/STM32WLxx/hal_efl_lld.c Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_efl_lld.c
* @brief STM32L4xx Embedded Flash subsystem low level driver source.
*
* @addtogroup HAL_EFL
* @{
*/
#include <string.h>
#include "hal.h"
#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define STM32_FLASH_SECTOR_SIZE 2048U
#define STM32_FLASH_LINE_SIZE 8U
#define STM32_FLASH_LINE_MASK (STM32_FLASH_LINE_SIZE - 1U)
#define FLASH_PDKEY1 0x04152637U
#define FLASH_PDKEY2 0xFAFBFCFDU
#define FLASH_KEY1 0x45670123U
#define FLASH_KEY2 0xCDEF89ABU
#define FLASH_OPTKEY1 0x08192A3BU
#define FLASH_OPTKEY2 0x4C5D6E7FU
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief EFL1 driver identifier.
*/
EFlashDriver EFLD1;
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
static const flash_descriptor_t efl_lld_descriptor = {
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED |
FLASH_ATTR_ECC_CAPABLE |
FLASH_ATTR_ECC_ZERO_LINE_CAPABLE,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH_NUMBER_OF_BANKS *
STM32_FLASH_SECTORS_PER_BANK,
.sectors = NULL,
.sectors_size = STM32_FLASH_SECTOR_SIZE,
.address = (uint8_t *)0x08000000U,
.size = STM32_FLASH_NUMBER_OF_BANKS *
STM32_FLASH_SECTORS_PER_BANK *
STM32_FLASH_SECTOR_SIZE
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void stm32_flash_lock(EFlashDriver *eflp) {
eflp->flash->CR |= FLASH_CR_LOCK;
}
static inline void stm32_flash_unlock(EFlashDriver *eflp) {
eflp->flash->KEYR |= FLASH_KEY1;
eflp->flash->KEYR |= FLASH_KEY2;
}
static inline void stm32_flash_enable_pgm(EFlashDriver *eflp) {
eflp->flash->CR |= FLASH_CR_PG;
}
static inline void stm32_flash_disable_pgm(EFlashDriver *eflp) {
eflp->flash->CR &= ~FLASH_CR_PG;
}
static inline void stm32_flash_clear_status(EFlashDriver *eflp) {
eflp->flash->SR = 0x0000FFFFU;
}
static inline void stm32_flash_wait_busy(EFlashDriver *eflp) {
/* Wait for busy bit clear.*/
while ((eflp->flash->SR & FLASH_SR_BSY) != 0U) {
}
}
static inline flash_error_t stm32_flash_check_errors(EFlashDriver *eflp) {
uint32_t sr = eflp->flash->SR;
/* Clearing error conditions.*/
eflp->flash->SR = sr & 0x0000FFFFU;
/* Some errors are only caught by assertion.*/
osalDbgAssert((sr & (FLASH_SR_FASTERR |
FLASH_SR_MISERR |
FLASH_SR_SIZERR)) == 0U, "unexpected flash error");
/* Decoding relevant errors.*/
if ((sr & FLASH_SR_WRPERR) != 0U) {
return FLASH_ERROR_HW_FAILURE;
}
if ((sr & (FLASH_SR_PGAERR | FLASH_SR_PROGERR | FLASH_SR_OPERR)) != 0U) {
return eflp->state == FLASH_PGM ? FLASH_ERROR_PROGRAM : FLASH_ERROR_ERASE;
}
return FLASH_NO_ERROR;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level Embedded Flash driver initialization.
*
* @notapi
*/
void efl_lld_init(void) {
/* Driver initialization.*/
eflObjectInit(&EFLD1);
EFLD1.flash = FLASH;
}
/**
* @brief Configures and activates the Embedded Flash peripheral.
*
* @param[in] eflp pointer to a @p EFlashDriver structure
*
* @notapi
*/
void efl_lld_start(EFlashDriver *eflp) {
stm32_flash_unlock(eflp);
FLASH->CR = 0x00000000U;
}
/**
* @brief Deactivates the Embedded Flash peripheral.
*
* @param[in] eflp pointer to a @p EFlashDriver structure
*
* @notapi
*/
void efl_lld_stop(EFlashDriver *eflp) {
stm32_flash_lock(eflp);
}
/**
* @brief Gets the flash descriptor structure.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @return A flash device descriptor.
*
* @notapi
*/
const flash_descriptor_t *efl_lld_get_descriptor(void *instance) {
(void)instance;
return &efl_lld_descriptor;
}
/**
* @brief Read operation.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[in] offset flash offset
* @param[in] n number of bytes to be read
* @param[out] rp pointer to the data buffer
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_READ if the read operation failed.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
size_t n, uint8_t *rp) {
EFlashDriver *devp = (EFlashDriver *)instance;
flash_error_t err = FLASH_NO_ERROR;
osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U));
osalDbgCheck((size_t)offset + n <= (size_t)efl_lld_descriptor.size);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No reading while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
/* FLASH_READY state while the operation is performed.*/
devp->state = FLASH_READ;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
/* Actual read implementation.*/
memcpy((void *)rp, (const void *)efl_lld_descriptor.address + offset, n);
/* Checking for errors after reading.*/
if ((devp->flash->SR & FLASH_SR_RDERR) != 0U) {
err = FLASH_ERROR_READ;
}
/* Ready state again.*/
devp->state = FLASH_READY;
return err;
}
/**
* @brief Program operation.
* @note The device supports ECC, it is only possible to write erased
* pages once except when writing all zeroes.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[in] offset flash offset
* @param[in] n number of bytes to be programmed
* @param[in] pp pointer to the data buffer
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_PROGRAM if the program operation failed.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
size_t n, const uint8_t *pp) {
EFlashDriver *devp = (EFlashDriver *)instance;
flash_error_t err = FLASH_NO_ERROR;
osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U));
osalDbgCheck((size_t)offset + n <= (size_t)efl_lld_descriptor.size);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No programming while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
/* FLASH_PGM state while the operation is performed.*/
devp->state = FLASH_PGM;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
/* Enabling PGM mode in the controller.*/
stm32_flash_enable_pgm(devp);
/* Actual program implementation.*/
while (n > 0U) {
volatile uint32_t *address;
union {
uint32_t w[STM32_FLASH_LINE_SIZE / sizeof (uint32_t)];
uint8_t b[STM32_FLASH_LINE_SIZE / sizeof (uint8_t)];
} line;
/* Unwritten bytes are initialized to all ones.*/
line.w[0] = 0xFFFFFFFFU;
line.w[1] = 0xFFFFFFFFU;
/* Programming address aligned to flash lines.*/
address = (volatile uint32_t *)(efl_lld_descriptor.address +
(offset & ~STM32_FLASH_LINE_MASK));
/* Copying data inside the prepared line.*/
do {
line.b[offset & STM32_FLASH_LINE_MASK] = *pp;
offset++;
n--;
pp++;
}
while ((n > 0U) & ((offset & STM32_FLASH_LINE_MASK) != 0U));
/* Programming line.*/
address[0] = line.w[0];
address[1] = line.w[1];
stm32_flash_wait_busy(devp);
err = stm32_flash_check_errors(devp);
if (err != FLASH_NO_ERROR) {
break;
}
}
/* Disabling PGM mode in the controller.*/
stm32_flash_disable_pgm(devp);
/* Ready state again.*/
devp->state = FLASH_READY;
return err;
}
/**
* @brief Starts a whole-device erase operation.
* @note This function only erases bank 2 if it is present. Bank 1 is not
* touched because it is where the program is running on.
* Pages on bank 1 can be individually erased.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_start_erase_all(void *instance) {
EFlashDriver *devp = (EFlashDriver *)instance;
osalDbgCheck(instance != NULL);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No erasing while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
/* FLASH_PGM state while the operation is performed.*/
devp->state = FLASH_ERASE;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
#if defined(FLASH_CR_MER2)
devp->flash->CR |= FLASH_CR_MER2;
devp->flash->CR |= FLASH_CR_STRT;
#endif
return FLASH_NO_ERROR;
}
/**
* @brief Starts an sector erase operation.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[in] sector sector to be erased
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_start_erase_sector(void *instance,
flash_sector_t sector) {
EFlashDriver *devp = (EFlashDriver *)instance;
osalDbgCheck(instance != NULL);
osalDbgCheck(sector < efl_lld_descriptor.sectors_count);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No erasing while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
/* FLASH_PGM state while the operation is performed.*/
devp->state = FLASH_ERASE;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
/* Enable page erase.*/
devp->flash->CR |= FLASH_CR_PER;
#if defined(FLASH_CR_BKER)
/* Bank selection.*/
if (sector < STM32_FLASH_SECTORS_PER_BANK) {
/* First bank.*/
devp->flash->CR &= ~FLASH_CR_BKER;
}
else {
/* Second bank.*/
devp->flash->CR |= FLASH_CR_BKER;
}
#endif
/* Mask off the page selection bits.*/
devp->flash->CR &= ~FLASH_CR_PNB;
/* Set the page selection bits.*/
devp->flash->CR |= sector << FLASH_CR_PNB_Pos;
/* Start the erase.*/
devp->flash->CR |= FLASH_CR_STRT;
return FLASH_NO_ERROR;
}
/**
* @brief Queries the driver for erase operation progress.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[out] msec recommended time, in milliseconds, that
* should be spent before calling this
* function again, can be @p NULL
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_ERASE if the erase operation failed.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @api
*/
flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) {
EFlashDriver *devp = (EFlashDriver *)instance;
flash_error_t err;
/* If there is an erase in progress then the device must be checked.*/
if (devp->state == FLASH_ERASE) {
/* Checking for operation in progress.*/
if ((devp->flash->SR & FLASH_SR_BSY) == 0U) {
/* Disabling the various erase control bits.*/
devp->flash->CR &= ~(FLASH_CR_MER |
FLASH_CR_PER);
/* No operation in progress, checking for errors.*/
err = stm32_flash_check_errors(devp);
/* Back to ready state.*/
devp->state = FLASH_READY;
}
else {
/* Recommended time before polling again, this is a simplified
implementation.*/
if (msec != NULL) {
*msec = (uint32_t)STM32_FLASH_WAIT_TIME_MS;
}
err = FLASH_BUSY_ERASING;
}
}
else {
err = FLASH_NO_ERROR;
}
return err;
}
/**
* @brief Returns the erase state of a sector.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[in] sector sector to be verified
* @return An error code.
* @retval FLASH_NO_ERROR if the sector is erased.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_VERIFY if the verify operation failed.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) {
EFlashDriver *devp = (EFlashDriver *)instance;
uint32_t *address;
flash_error_t err = FLASH_NO_ERROR;
unsigned i;
osalDbgCheck(instance != NULL);
osalDbgCheck(sector < efl_lld_descriptor.sectors_count);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No verifying while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
/* Address of the sector.*/
address = (uint32_t *)(efl_lld_descriptor.address +
flashGetSectorOffset(getBaseFlash(devp), sector));
/* FLASH_READY state while the operation is performed.*/
devp->state = FLASH_READ;
/* Scanning the sector space.*/
for (i = 0U; i < STM32_FLASH_SECTOR_SIZE / sizeof(uint32_t); i++) {
if (*address != 0xFFFFFFFFU) {
err = FLASH_ERROR_VERIFY;
break;
}
address++;
}
/* Ready state again.*/
devp->state = FLASH_READY;
return err;
}
#endif /* HAL_USE_EFL == TRUE */
/** @} */

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os/hal/ports/STM32/STM32WLxx/hal_efl_lld.h Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_efl_lld.h
* @brief STM32L4xx Embedded Flash subsystem low level driver header.
*
* @addtogroup HAL_EFL
* @{
*/
#ifndef HAL_EFL_LLD_H
#define HAL_EFL_LLD_H
#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name STM32L4xx configuration options
* @{
*/
/**
* @brief Suggested wait time during erase operations polling.
*/
#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__)
#define STM32_FLASH_WAIT_TIME_MS 5
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if !defined(STM32_FLASH_NUMBER_OF_BANKS)
#error "STM32_FLASH_NUMBER_OF_BANKS not defined in registry"
#endif
#if !defined(STM32_FLASH_SECTORS_PER_BANK)
#error "STM32_FLASH_SECTORS_PER_BANK not defined in registry"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Low level fields of the embedded flash driver structure.
*/
#define efl_lld_driver_fields \
/* Flash registers.*/ \
FLASH_TypeDef *flash
/**
* @brief Low level fields of the embedded flash configuration structure.
*/
#define efl_lld_config_fields \
/* Dummy configuration, it is not needed.*/ \
uint32_t dummy
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern EFlashDriver EFLD1;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void efl_lld_init(void);
void efl_lld_start(EFlashDriver *eflp);
void efl_lld_stop(EFlashDriver *eflp);
const flash_descriptor_t *efl_lld_get_descriptor(void *instance);
flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
size_t n, uint8_t *rp);
flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
size_t n, const uint8_t *pp);
flash_error_t efl_lld_start_erase_all(void *instance);
flash_error_t efl_lld_start_erase_sector(void *instance,
flash_sector_t sector);
flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec);
flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_EFL == TRUE */
#endif /* HAL_EFL_LLD_H */
/** @} */

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os/hal/ports/STM32/STM32WLxx/hal_lld.c Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32WLxx/hal_lld.c
* @brief STM32WLxx HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief CMSIS system core clock variable.
* @note It is declared in system_stm32wlxx.h.
*/
uint32_t SystemCoreClock = STM32_HCLK;
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Initializes the backup domain.
* @note WARNING! Changing RTC clock source impossible without resetting
* of the whole BKP domain.
*/
static void hal_lld_backup_domain_init(void) {
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
}
#if STM32_LSE_ENABLED
/* LSE activation.*/
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Wait until LSE is stable. */
#endif
#if STM32_MSIPLL_ENABLED
/* MSI PLL activation depends on LSE. Reactivating and checking for
MSI stability.*/
RCC->CR |= RCC_CR_MSIPLLEN;
while ((RCC->CR & RCC_CR_MSIRDY) == 0)
; /* Wait until MSI is stable. */
#endif
#if HAL_USE_RTC
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
RCC->BDCR |= STM32_RTCSEL;
/* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
}
#endif /* HAL_USE_RTC */
/* Low speed output mode.*/
RCC->BDCR |= STM32_LSCOSEL;
#if STM32_LSCO_ENABLED
/* Enable LSCO */
RCC->BDCR |= RCC_BDCR_LSCOEN | ;
#endif /* STM32_LSCO_ENABLED */
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
/* Reset of all peripherals.
Note, GPIOs are not reset because initialized before this point in
board files.*/
rccResetAHB1(~0);
rccResetAHB2(~STM32_GPIO_EN_MASK);
/* Reset all except FLASH.*/
rccResetAHB3(RCC_AHB3RSTR_PKARST | RCC_AHB3RSTR_AESRST |
RCC_AHB3RSTR_RNGRST | RCC_AHB3RSTR_HSEMRST);
rccResetAPB1R1(~0);
rccResetAPB1R2(~0);
rccResetAPB2(~0);
/* Initializes the backup domain.*/
hal_lld_backup_domain_init();
/* DMA subsystems initialization.*/
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* IRQ subsystem initialization.*/
irqInit();
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
PWR->CR2 = PWR_CR2_PVDE | (STM32_PLS & STM32_PLS_MASK);
#else
PWR->CR2 = 0;
#endif /* STM32_PVD_ENABLE */
}
/**
* @brief STM32WLxx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function should be invoked just after the system reset.
*
* @special
*/
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* Initial clocks setup and wait for MSI stabilization, the MSI clock is
always enabled because it is the fall back clock when PLL the fails.
Trim fields are not altered from reset values.*/
/* MSIRANGE can be set only when MSI is OFF or READY.*/
RCC->CR = RCC_CR_MSION;
while ((RCC->CR & RCC_CR_MSIRDY) == 0)
; /* Wait until MSI is stable. */
/* Clocking from MSI, in case MSI was not the default source.*/
RCC->CFGR = 0;
while ((RCC->CFGR & RCC_CFGR_SWS) != 0)
; /* Wait until MSI is selected. */
/* Core voltage setup.*/
PWR->CR1 = STM32_VOS;
while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
; /* stable. */
#if STM32_HSI16_ENABLED
/* HSI activation.*/
RCC->CR |= RCC_CR_HSION;
while ((RCC->CR & RCC_CR_HSIRDY) == 0)
; /* Wait until HSI16 is stable. */
#endif
#if STM32_HSE_ENABLED
#if STM32_HSESRC == STM32_HSE_TCXO
/* Enable PB0-VDDTCXO.*/
RCC->CR |= RCC_CR_HSEBYPPWR;
#endif /* STM32_HSESRC == STM32_HSE_TCXO */
/* Set HSE SYSCLK prescaler.*/
RCC-CR |= STM32_HSEPRE;
/* HSE activation.*/
RCC->CR |= RCC_CR_HSEON;
while ((RCC->CR & RCC_CR_HSERDY) == 0)
; /* Wait until HSE is stable. */
#endif
#if STM32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSION;
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
; /* Wait until LSI is stable. */
#endif
/* Backup domain access enabled and left open.*/
PWR->CR1 |= PWR_CR1_DBP;
#if STM32_LSE_ENABLED
/* LSE activation.*/
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Wait until LSE is stable. */
#endif
/* Flash setup for selected MSI speed setting.*/
FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
STM32_MSI_FLASHBITS;
/* Changing MSIRANGE to configured value.*/
RCC->CR |= STM32_MSIRANGE;
/* Switching from MSISRANGE to MSIRANGE.*/
RCC->CR |= RCC_CR_MSIRGSEL;
while ((RCC->CR & RCC_CR_MSIRDY) == 0)
;
/* MSI is configured SYSCLK source so wait for it to be stable as well.*/
while ((RCC->CFGR & RCC_CFGR_SWS) != 0)
;
#if STM32_MSIPLL_ENABLED
/* MSI PLL (to LSE) activation */
RCC->CR |= RCC_CR_MSIPLLEN;
#endif
/* Updating MSISRANGE value. MSISRANGE can be set only when MSIRGSEL is high.
This range is used exiting the Standby mode until MSIRGSEL is set.*/
RCC->CSR |= STM32_MSISRANGE;
#if STM32_ACTIVATE_PLL
/* PLLM and PLLSRC are common to all PLLs.*/
RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
STM32_PLLQ | STM32_PLLQEN |
STM32_PLLP | STM32_PLLPEN |
STM32_PLLN | STM32_PLLM |
STM32_PLLSRC;
/* PLL activation.*/
RCC->CR |= RCC_CR_PLLON;
/* Waiting for PLL lock.*/
while ((RCC->CR & RCC_CR_PLLRDY) == 0)
;
#endif
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
RCC->EXTCFGR = STM32_SHDHPRE;
/* CCIPR register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t ccipr = STM32_RNGSEL | STM32_ADCSEL | STM32_LPTIM3SEL |
STM32_LPTIM2SEL | STM32_LPTIM1SEL | STM32_I2C3SEL |
STM32_I2C2SEL | STM32_I2C1SEL | STM32_LPUART1SEL |
STM32_SPI2SEL | STM32_USART2SEL | STM32_USART1SEL;
RCC->CCIPR = ccipr;
}
/* Set flash WS's for SYSCLK source */
if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) {
FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
(STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
}
}
/* Switching to the configured SYSCLK source if it is different from MSI.*/
#if (STM32_SW != STM32_SW_MSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
/* Wait until SYSCLK is stable.*/
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
#endif
/* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */
if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) {
FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
(STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
}
}
#endif /* STM32_NO_INIT */
}
/** @} */

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# Required platform files.
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32WLxx/stm32_isr.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32WLxx/hal_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32WLxx/hal_efl_lld.c
# Required include directories.
PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
$(CHIBIOS)/os/hal/ports/STM32/STM32WLxx
# Optional platform files.
ifeq ($(USE_SMART_BUILD),yes)
# Configuration files directory
ifeq ($(HALCONFDIR),)
ifeq ($(CONFDIR),)
HALCONFDIR = .
else
HALCONFDIR := $(CONFDIR)
endif
endif
HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
else
endif
# Drivers compatible with the platform.
include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/CRYPv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv3/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
# Shared variables
ALLCSRC += $(PLATFORMSRC)
ALLINC += $(PLATFORMINC)

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32WLxx/stm32_dmamux.h
* @brief STM32WLxx DMAMUX handler header.
*
* @addtogroup STM32WLxx_DMAMUX
* @{
*/
#ifndef STM32_DMAMUX_H
#define STM32_DMAMUX_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name DMAMUX1 request sources
* @{
*/
#define STM32_DMAMUX1_REQ_GEN0 1
#define STM32_DMAMUX1_REQ_GEN1 2
#define STM32_DMAMUX1_REQ_GEN2 3
#define STM32_DMAMUX1_REQ_GEN3 4
#define STM32_DMAMUX1_ADC1 5
#define STM32_DMAMUX1_DAC1_CH1 6
#define STM32_DMAMUX1_SPI1_RX 7
#define STM32_DMAMUX1_SPI1_TX 8
#define STM32_DMAMUX1_SPI2_RX 9
#define STM32_DMAMUX1_SPI2_TX 10
#define STM32_DMAMUX1_I2C1_RX 11
#define STM32_DMAMUX1_I2C1_TX 12
#define STM32_DMAMUX1_I2C2_RX 13
#define STM32_DMAMUX1_I2C2_TX 14
#define STM32_DMAMUX1_I2C3_RX 15
#define STM32_DMAMUX1_I2C3_TX 16
#define STM32_DMAMUX1_USART1_RX 17
#define STM32_DMAMUX1_USART1_TX 18
#define STM32_DMAMUX1_USART2_RX 19
#define STM32_DMAMUX1_USART2_TX 20
#define STM32_DMAMUX1_LPUART1_RX 21
#define STM32_DMAMUX1_LPUART1_TX 22
#define STM32_DMAMUX1_TIM1_CH1 23
#define STM32_DMAMUX1_TIM1_CH2 24
#define STM32_DMAMUX1_TIM1_CH3 25
#define STM32_DMAMUX1_TIM1_CH4 26
#define STM32_DMAMUX1_TIM1_UP 27
#define STM32_DMAMUX1_TIM1_TRIG 28
#define STM32_DMAMUX1_TIM1_COM 29
#define STM32_DMAMUX1_TIM2_CH1 30
#define STM32_DMAMUX1_TIM2_CH2 31
#define STM32_DMAMUX1_TIM2_CH3 32
#define STM32_DMAMUX1_TIM2_CH4 33
#define STM32_DMAMUX1_TIM2_UP 34
#define STM32_DMAMUX1_TIM16_CH1 35
#define STM32_DMAMUX1_TIM16_UP 36
#define STM32_DMAMUX1_TIM17_CH1 37
#define STM32_DMAMUX1_TIM17_UP 38
#define STM32_DMAMUX1_AES_IN 39
#define STM32_DMAMUX1_AES_OUT 40
#define STM32_DMAMUX1_SPIR_RX 41
#define STM32_DMAMUX1_SPIR_TX 42
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* STM32_DMAMUX_H */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32L4xx/stm32_isr.c
* @brief STM32L4xx ISR handler code.
*
* @addtogroup STM32L4xx_ISR
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
#define exti_serve_irq(pr, channel) { \
\
if ((pr) & (1U << (channel))) { \
_pal_isr_code(channel); \
} \
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#include "stm32_exti0.inc"
#include "stm32_exti1.inc"
#include "stm32_exti2.inc"
#include "stm32_exti3.inc"
#include "stm32_exti4.inc"
#include "stm32_exti5_9.inc"
#include "stm32_exti10_15.inc"
#include "stm32_exti16_34.inc"
#include "stm32_exti45.inc"
#include "stm32_usart1.inc"
#include "stm32_usart2.inc"
#include "stm32_lpuart1.inc"
#include "stm32_tim1.inc"
#include "stm32_tim2.inc"
#include "stm32_tim16.inc"
#include "stm32_tim17.inc"
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Enables IRQ sources.
*
* @notapi
*/
void irqInit(void) {
exti0_irq_init();
exti1_irq_init();
exti2_irq_init();
exti3_irq_init();
exti4_irq_init();
exti5_9_irq_init();
exti10_15_irq_init();
exti16_exti34_irq_init();
exti45_irq_init();
tim1_irq_init();
tim2_irq_init();
tim16_irq_init();
tim17_irq_init();
usart1_irq_init();
usart2_irq_init();
lpuart1_irq_init();
}
/**
* @brief Disables IRQ sources.
*
* @notapi
*/
void irqDeinit(void) {
exti0_irq_deinit();
exti1_irq_deinit();
exti2_irq_deinit();
exti3_irq_deinit();
exti4_irq_deinit();
exti5_9_irq_deinit();
exti10_15_irq_deinit();
exti16_exti34_irq_deinit();
exti45_irq_deinit();
tim1_irq_deinit();
tim2_irq_deinit();
tim16_irq_deinit();
tim17_irq_deinit();
usart1_irq_deinit();
usart2_irq_deinit();
lpuart1_irq_deinit();
}
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32WLxx/stm32_isr.h
* @brief STM32WLxx ISR handler header.
*
* @addtogroup SRM32WLxx_ISR
* @{
*/
#ifndef STM32_ISR_H
#define STM32_ISR_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISRs suppressed in standard drivers
* @{
*/
#define STM32_TIM1_SUPPRESS_ISR
#define STM32_TIM2_SUPPRESS_ISR
#define STM32_TIM16_SUPPRESS_ISR
#define STM32_TIM17_SUPPRESS_ISR
#define STM32_USART1_SUPPRESS_ISR
#define STM32_USART2_SUPPRESS_ISR
#define STM32_LPUART1_SUPPRESS_ISR
/** @} */
/**
* @name ISR names and numbers
* @{
*/
/*
* ADC unit.
*/
#define STM32_ADC1_HANDLER Vector88
#define STM32_ADC1_NUMBER 18
/*
* DMA unit.
*/
#define STM32_DMA1_CH1_HANDLER Vector6C
#define STM32_DMA1_CH2_HANDLER Vector70
#define STM32_DMA1_CH3_HANDLER Vector74
#define STM32_DMA1_CH4_HANDLER Vector78
#define STM32_DMA1_CH5_HANDLER Vector7C
#define STM32_DMA1_CH6_HANDLER Vector80
#define STM32_DMA1_CH7_HANDLER Vector84
#define STM32_DMA2_CH1_HANDLER Vector118
#define STM32_DMA2_CH2_HANDLER Vector11C
#define STM32_DMA2_CH3_HANDLER Vector120
#define STM32_DMA2_CH4_HANDLER Vector124
#define STM32_DMA2_CH5_HANDLER Vector128
#define STM32_DMA2_CH6_HANDLER Vector12C
#define STM32_DMA2_CH7_HANDLER Vector130
#define STM32_DMA1_CH1_NUMBER 11
#define STM32_DMA1_CH2_NUMBER 12
#define STM32_DMA1_CH3_NUMBER 13
#define STM32_DMA1_CH4_NUMBER 14
#define STM32_DMA1_CH5_NUMBER 15
#define STM32_DMA1_CH6_NUMBER 16
#define STM32_DMA1_CH7_NUMBER 17
#define STM32_DMA2_CH1_NUMBER 54
#define STM32_DMA2_CH2_NUMBER 55
#define STM32_DMA2_CH3_NUMBER 56
#define STM32_DMA2_CH4_NUMBER 57
#define STM32_DMA2_CH5_NUMBER 58
#define STM32_DMA2_CH6_NUMBER 59
#define STM32_DMA2_CH7_NUMBER 60
/*
* EXTI unit.
*/
#define STM32_EXTI0_HANDLER Vector58
#define STM32_EXTI1_HANDLER Vector5C
#define STM32_EXTI2_HANDLER Vector60
#define STM32_EXTI3_HANDLER Vector64
#define STM32_EXTI4_HANDLER Vector68
#define STM32_EXTI5_9_HANDLER Vector98
#define STM32_EXTI10_15_HANDLER VectorE4
#define STM32_EXTI16_34_HANDLER Vector44 /* PVD PVM3 */
#define STM32_EXTI21_22_HANDLER Vector140 /* COMP1..2 */
#define STM32_EXTI45_HANDLER Vector108 /* RTR */
#define STM32_EXTI0_NUMBER 6
#define STM32_EXTI1_NUMBER 7
#define STM32_EXTI2_NUMBER 8
#define STM32_EXTI3_NUMBER 9
#define STM32_EXTI4_NUMBER 10
#define STM32_EXTI5_9_NUMBER 22
#define STM32_EXTI10_15_NUMBER 41
#define STM32_EXTI16_34_NUMBER 1
#define STM32_EXTI21_22_NUMBER 21
#define STM32_EXTI45_NUMBER 50
/*
* I2C units.
*/
#define STM32_I2C1_EVENT_HANDLER VectorB8
#define STM32_I2C1_ERROR_HANDLER VectorBC
#define STM32_I2C2_EVENT_HANDLER VectorC0
#define STM32_I2C2_ERROR_HANDLER VectorC4
#define STM32_I2C3_EVENT_HANDLER Vector100
#define STM32_I2C3_ERROR_HANDLER Vector104
#define STM32_I2C1_EVENT_NUMBER 30
#define STM32_I2C1_ERROR_NUMBER 31
#define STM32_I2C2_EVENT_NUMBER 32
#define STM32_I2C2_ERROR_NUMBER 33
#define STM32_I2C3_EVENT_NUMBER 48
#define STM32_I2C3_ERROR_NUMBER 49
/*
* TIM units.
*/
#define STM32_TIM1_BRK_HANDLER Vector9C
#define STM32_TIM1_UP_HANDLER VectorA0
#define STM32_TIM1_TRGCO_HANDLER VectorA4
#define STM32_TIM1_CC_HANDLER VectorA8
#define STM32_TIM2_HANDLER VectorAC
#define STM32_TIM16_HANDLER VectorB0
#define STM32_TIM17_HANDLER VectorB4
#define STM32_TIM1_BRK_NUMBER 23
#define STM32_TIM1_UP_NUMBER 24
#define STM32_TIM1_TRGCO_TIM17_NUMBER 25
#define STM32_TIM1_CC_NUMBER 26
#define STM32_TIM2_NUMBER 27
#define STM32_TIM16_NUMBER 28
#define STM32_TIM17_NUMBER 29
/*
* USART/UART units.
*/
#define STM32_USART1_HANDLER VectorD0
#define STM32_USART2_HANDLER VectorD4
#define STM32_LPUART1_HANDLER VectorD8
#define STM32_USART1_NUMBER 36
#define STM32_USART2_NUMBER 37
#define STM32_LPUART1_NUMBER 38
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void irqInit(void);
void irqDeinit(void);
#ifdef __cplusplus
}
#endif
#endif /* STM32_ISR_H */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32WLxx/stm32_rcc.h
* @brief RCC helper driver header.
* @note This file requires definitions from the ST header file
* @p stm32wlxx.h.
*
* @addtogroup STM32WLxx_RCC
* @{
*/
#ifndef STM32_RCC_H
#define STM32_RCC_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @name Generic RCC operations
* @{
*/
/**
* @brief Enables the clock of one or more peripheral on the APB1 bus (R1).
*
* @param[in] mask APB1 R1 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB1R1(mask, lp) { \
RCC->APB1ENR1 |= (mask); \
if (lp) \
RCC->APB1SMENR1 |= (mask); \
else \
RCC->APB1SMENR1 &= ~(mask); \
(void)RCC->APB1SMENR1; \
}
/**
* @brief Disables the clock of one or more peripheral on the APB1 bus (R1).
*
* @param[in] mask APB1 R1 peripherals mask
*
* @api
*/
#define rccDisableAPB1R1(mask) { \
RCC->APB1ENR1 &= ~(mask); \
RCC->APB1SMENR1 &= ~(mask); \
(void)RCC->APB1SMENR1; \
}
/**
* @brief Resets one or more peripheral on the APB1 bus (R1).
*
* @param[in] mask APB1 R1 peripherals mask
*
* @api
*/
#define rccResetAPB1R1(mask) { \
RCC->APB1RSTR1 |= (mask); \
RCC->APB1RSTR1 &= ~(mask); \
(void)RCC->APB1RSTR1; \
}
/**
* @brief Enables the clock of one or more peripheral on the APB1 bus (R2).
*
* @param[in] mask APB1 R2 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB1R2(mask, lp) { \
RCC->APB1ENR2 |= (mask); \
if (lp) \
RCC->APB1SMENR2 |= (mask); \
else \
RCC->APB1SMENR2 &= ~(mask); \
(void)RCC->APB1SMENR2; \
}
/**
* @brief Disables the clock of one or more peripheral on the APB1 bus (R2).
*
* @param[in] mask APB1 R2 peripherals mask
*
* @api
*/
#define rccDisableAPB1R2(mask) { \
RCC->APB1ENR2 &= ~(mask); \
RCC->APB1SMENR2 &= ~(mask); \
(void)RCC->APB1SMENR2; \
}
/**
* @brief Resets one or more peripheral on the APB1 bus (R2).
*
* @param[in] mask APB1 R2 peripherals mask
*
* @api
*/
#define rccResetAPB1R2(mask) { \
RCC->APB1RSTR2 |= (mask); \
RCC->APB1RSTR2 &= ~(mask); \
(void)RCC->APB1RSTR2; \
}
/**
* @brief Enables the clock of one or more peripheral on the APB2 bus.
*
* @param[in] mask APB2 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB2(mask, lp) { \
RCC->APB2ENR |= (mask); \
if (lp) \
RCC->APB2SMENR |= (mask); \
else \
RCC->APB2SMENR &= ~(mask); \
(void)RCC->APB2SMENR; \
}
/**
* @brief Disables the clock of one or more peripheral on the APB2 bus.
*
* @param[in] mask APB2 peripherals mask
*
* @api
*/
#define rccDisableAPB2(mask) { \
RCC->APB2ENR &= ~(mask); \
RCC->APB2SMENR &= ~(mask); \
(void)RCC->APB2SMENR; \
}
/**
* @brief Resets one or more peripheral on the APB2 bus.
*
* @param[in] mask APB2 peripherals mask
*
* @api
*/
#define rccResetAPB2(mask) { \
RCC->APB2RSTR |= (mask); \
RCC->APB2RSTR &= ~(mask); \
(void)RCC->APB2RSTR; \
}
/**
* @brief Enables the clock of one or more peripheral on the APB3 bus.
*
* @param[in] mask APB3 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB3(mask, lp) { \
RCC->APB3ENR |= (mask); \
if (lp) \
RCC->APB3SMENR |= (mask); \
else \
RCC->APB3SMENR &= ~(mask); \
(void)RCC->APB3SMENR; \
}
/**
* @brief Disables the clock of one or more peripheral on the APB3 bus.
*
* @param[in] mask APB3 peripherals mask
*
* @api
*/
#define rccDisableAPB3(mask) { \
RCC->APB3ENR &= ~(mask); \
RCC->APB3SMENR &= ~(mask); \
(void)RCC->APB3SMENR; \
}
/**
* @brief Resets one or more peripheral on the APB3 bus.
*
* @param[in] mask APB3 peripherals mask
*
* @api
*/
#define rccResetAPB3(mask) { \
RCC->APB3RSTR |= (mask); \
RCC->APB3RSTR &= ~(mask); \
(void)RCC->APB3RSTR; \
}
/**
* @brief Enables the clock of one or more peripheral on the AHB1 bus.
*
* @param[in] mask AHB1 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAHB1(mask, lp) { \
RCC->AHB1ENR |= (mask); \
if (lp) \
RCC->AHB1SMENR |= (mask); \
else \
RCC->AHB1SMENR &= ~(mask); \
(void)RCC->AHB1SMENR; \
}
/**
* @brief Disables the clock of one or more peripheral on the AHB1 bus.
*
* @param[in] mask AHB1 peripherals mask
*
* @api
*/
#define rccDisableAHB1(mask) { \
RCC->AHB1ENR &= ~(mask); \
RCC->AHB1SMENR &= ~(mask); \
(void)RCC->AHB1SMENR; \
}
/**
* @brief Resets one or more peripheral on the AHB1 bus.
*
* @param[in] mask AHB1 peripherals mask
*
* @api
*/
#define rccResetAHB1(mask) { \
RCC->AHB1RSTR |= (mask); \
RCC->AHB1RSTR &= ~(mask); \
(void)RCC->AHB1RSTR; \
}
/**
* @brief Enables the clock of one or more peripheral on the AHB2 bus.
*
* @param[in] mask AHB2 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAHB2(mask, lp) { \
RCC->AHB2ENR |= (mask); \
if (lp) \
RCC->AHB2SMENR |= (mask); \
else \
RCC->AHB2SMENR &= ~(mask); \
(void)RCC->AHB2SMENR; \
}
/**
* @brief Disables the clock of one or more peripheral on the AHB2 bus.
*
* @param[in] mask AHB2 peripherals mask
*
* @api
*/
#define rccDisableAHB2(mask) { \
RCC->AHB2ENR &= ~(mask); \
RCC->AHB2SMENR &= ~(mask); \
(void)RCC->AHB2SMENR; \
}
/**
* @brief Resets one or more peripheral on the AHB2 bus.
*
* @param[in] mask AHB2 peripherals mask
*
* @api
*/
#define rccResetAHB2(mask) { \
RCC->AHB2RSTR |= (mask); \
RCC->AHB2RSTR &= ~(mask); \
(void)RCC->AHB2RSTR; \
}
/**
* @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus.
*
* @param[in] mask AHB3 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAHB3(mask, lp) { \
RCC->AHB3ENR |= (mask); \
if (lp) \
RCC->AHB3SMENR |= (mask); \
else \
RCC->AHB3SMENR &= ~(mask); \
(void)RCC->AHB3SMENR; \
}
/**
* @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus.
*
* @param[in] mask AHB3 peripherals mask
*
* @api
*/
#define rccDisableAHB3(mask) { \
RCC->AHB3ENR &= ~(mask); \
RCC->AHB3SMENR &= ~(mask); \
(void)RCC->AHB3SMENR; \
}
/**
* @brief Resets one or more peripheral on the AHB3 (FSMC) bus.
*
* @param[in] mask AHB3 peripherals mask
*
* @api
*/
#define rccResetAHB3(mask) { \
RCC->AHB3RSTR |= (mask); \
RCC->AHB3RSTR &= ~(mask); \
(void)RCC->AHB3RSTR; \
}
/** @} */
/**
* @name ADC peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the ADC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableADC1(lp) rccEnableAHB2(RCC_AHB2ENR_ADCEN, lp)
/**
* @brief Disables the ADC1 peripheral clock.
*
* @api
*/
#define rccDisableADC1() rccDisableAHB2(RCC_APB2RSTR_ADCRST)
/**
* @brief Resets the ADC1 peripheral.
*
* @api
*/
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADCRST)
/** @} */
/**
* @name DAC peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the DAC1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDAC1(lp) rccEnableAPB1R1(RCC_APB1ENR1_DAC1EN, lp)
/**
* @brief Disables the DAC1 peripheral clock.
*
* @api
*/
#define rccDisableDAC1() rccDisableAPB1R1(RCC_APB1ENR1_DAC1EN)
/**
* @brief Resets the DAC1 peripheral.
*
* @api
*/
#define rccResetDAC1() rccResetAPB1R1(RCC_APB1RSTR1_DAC1RST)
/** @} */
/**
* @name DMA peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the DMA1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
/**
* @brief Disables the DMA1 peripheral clock.
*
* @api
*/
#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN)
/**
* @brief Resets the DMA1 peripheral.
*
* @api
*/
#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
/**
* @brief Enables the DMA2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
/**
* @brief Disables the DMA2 peripheral clock.
*
* @api
*/
#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN)
/**
* @brief Resets the DMA2 peripheral.
*
* @api
*/
#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
/** @} */
/**
* @name I2C peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the I2C1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableI2C1(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C1EN, lp)
/**
* @brief Disables the I2C1 peripheral clock.
*
* @api
*/
#define rccDisableI2C1() rccDisableAPB1R1(RCC_APB1ENR1_I2C1EN)
/**
* @brief Resets the I2C1 peripheral.
*
* @api
*/
#define rccResetI2C1() rccResetAPB1R1(RCC_APB1RSTR1_I2C1RST)
/**
* @brief Enables the I2C2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableI2C2(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C2EN, lp)
/**
* @brief Disables the I2C2 peripheral clock.
*
* @api
*/
#define rccDisableI2C2() rccDisableAPB1R1(RCC_APB1ENR1_I2C2EN)
/**
* @brief Resets the I2C2 peripheral.
*
* @api
*/
#define rccResetI2C2() rccResetAPB1R1(RCC_APB1RSTR1_I2C2RST)
/**
* @brief Enables the I2C3 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableI2C3(lp) rccEnableAPB1R1(RCC_APB1ENR1_I2C3EN, lp)
/**
* @brief Disables the I2C3 peripheral clock.
*
* @api
*/
#define rccDisableI2C3() rccDisableAPB1R1(RCC_APB1ENR1_I2C3EN)
/**
* @brief Resets the I2C3 peripheral.
*
* @api
*/
#define rccResetI2C3() rccResetAPB1R1(RCC_APB1RSTR1_I2C3RST)
/** @} */
/**
* @name RNG peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the RNG peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableRNG(lp) rccEnableAHB3(RCC_AHB3ENR_RNGEN, lp)
/**
* @brief Disables the RNG peripheral clock.
*
* @api
*/
#define rccDisableRNG() rccDisableAHB3(RCC_AHB3ENR_RNGEN)
/**
* @brief Resets the RNG peripheral.
*
* @api
*/
#define rccResetRNG() rccResetAHB3(RCC_AHB3RSTR_RNGRST)
/** @} */
/**
* @name SPI peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the SPI1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
/**
* @brief Disables the SPI1 peripheral clock.
*
* @api
*/
#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN)
/**
* @brief Resets the SPI1 peripheral.
*
* @api
*/
#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
/**
* @brief Enables the SPI2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSPI2(lp) rccEnableAPB1R1(RCC_APB1ENR1_SPI2EN, lp)
/**
* @brief Disables the SPI2 peripheral clock.
*
* @api
*/
#define rccDisableSPI2() rccDisableAPB1R1(RCC_APB1ENR1_SPI2EN)
/**
* @brief Resets the SPI2 peripheral.
*
* @api
*/
#define rccResetSPI2() rccResetAPB1R1(RCC_APB1RSTR1_SPI2RST)
/**
* @brief Enables the SPIR peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSPIR(lp) rccEnableAPB3(RCC_APB3ENR_SUBGHZSPIEN, lp)
/**
* @brief Disables the SPI2 peripheral clock.
*
* @api
*/
#define rccDisableSPIR() rccDisableAPB3(RCC_APB3ENR_SUBGHZSPIEN)
/**
* @brief Resets the SPI2 peripheral.
*
* @api
*/
#define rccResetSPIR() rccResetAPB3(RCC_APB3RSTR_SUBGHZSPIRST)
/** @} */
/**
* @name TIM peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the TIM1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
/**
* @brief Disables the TIM1 peripheral clock.
*
* @api
*/
#define rccDisableTIM1() rccDisableAPB2(RCC_APB2ENR_TIM1EN)
/**
* @brief Resets the TIM1 peripheral.
*
* @api
*/
#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
/**
* @brief Enables the TIM2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM2(lp) rccEnableAPB1R1(RCC_APB1ENR1_TIM2EN, lp)
/**
* @brief Disables the TIM2 peripheral clock.
*
* @api
*/
#define rccDisableTIM2() rccDisableAPB1R1(RCC_APB1ENR1_TIM2EN)
/**
* @brief Resets the TIM2 peripheral.
*
* @api
*/
#define rccResetTIM2() rccResetAPB1R1(RCC_APB1RSTR1_TIM2RST)
/**
* @brief Enables the TIM16 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
/**
* @brief Disables the TIM16 peripheral clock.
*
* @api
*/
#define rccDisableTIM16() rccDisableAPB2(RCC_APB2ENR_TIM16EN)
/**
* @brief Resets the TIM16 peripheral.
*
* @api
*/
#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
/**
* @brief Enables the TIM17 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
/**
* @brief Disables the TIM17 peripheral clock.
*
* @api
*/
#define rccDisableTIM17() rccDisableAPB2(RCC_APB2ENR_TIM17EN)
/**
* @brief Resets the TIM17 peripheral.
*
* @api
*/
#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
/** @} */
/**
* @name USART/UART peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the USART1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
/**
* @brief Disables the USART1 peripheral clock.
*
* @api
*/
#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN)
/**
* @brief Resets the USART1 peripheral.
*
* @api
*/
#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
/**
* @brief Enables the USART2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableUSART2(lp) rccEnableAPB1R1(RCC_APB1ENR1_USART2EN, lp)
/**
* @brief Disables the USART2 peripheral clock.
*
* @api
*/
#define rccDisableUSART2() rccDisableAPB1R1(RCC_APB1ENR1_USART2EN)
/**
* @brief Resets the USART2 peripheral.
*
* @api
*/
#define rccResetUSART2() rccResetAPB1R1(RCC_APB1RSTR1_USART2RST)
/**
* @brief Enables the LPUART1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableLPUART1(lp) rccEnableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp)
/**
* @brief Disables the LPUART1 peripheral clock.
*
* @api
*/
#define rccDisableLPUART1() rccDisableAPB1R2(RCC_APB1ENR2_LPUART1EN)
/**
* @brief Resets the USART1 peripheral.
*
* @api
*/
#define rccResetLPUART1() rccResetAPB1R2(RCC_APB1RSTR2_LPUART1RST)
/** @} */
/**
* @name CRC peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the CRC peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableCRC(lp) rccEnableAHB1(RCC_AHB1ENR_CRCEN, lp)
/**
* @brief Disables the CRC peripheral clock.
*
* @api
*/
#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
/**
* @brief Resets the CRC peripheral.
*
* @api
*/
#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
/** @} */
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* STM32_RCC_H */
/** @} */

265
os/hal/ports/STM32/STM32WLxx/stm32_registry.h Normal file
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@ -0,0 +1,265 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32WLxx/stm32_registry.h
* @brief STM32WLxx capabilities registry.
*
* @addtogroup HAL
* @{
*/
#ifndef STM32_REGISTRY_H
#define STM32_REGISTRY_H
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
/**
* @name STM32WLxx capabilities
* @{
*/
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 FALSE
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
/* CAN attributes.*/
#define STM32_HAS_CAN1 FALSE
#define STM32_HAS_CAN2 FALSE
#define STM32_HAS_CAN3 FALSE
/* CPU2 attributes.*/
#if defined(STM32WL55xx) || defined(STM32WL54xx) || defined(__DOXYGEN__)
#define STM32_HAS_CPU2 TRUE
#else
#define STM32_HAS_CPU2 FALSE
#endif /* defined(STM32WL55xx) || defined(STM32WL54xx) */
/* CRC attributes.*/
#define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE TRUE
/* CRYP attributes.*/
#define STM32_HAS_CRYP1 TRUE
/* DAC attributes.*/
#define STM32_HAS_DAC1_CH1 TRUE
#define STM32_HAS_DAC1_CH2 FALSE
#define STM32_HAS_DAC2_CH1 FALSE
#define STM32_HAS_DAC2_CH2 FALSE
/* DMA attributes.*/
#define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_DMAMUX TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 7
#define STM32_DMA2_NUM_CHANNELS 7
/* DMA2D attributes.*/
#define STM32_HAS_DMA2D FALSE
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 47
#define STM32_EXTI_IMR1_MASK 0xFF9E0000U
#define STM32_EXTI_IMR2_MASK 0xFFFFDFFBU
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
#define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/
#endif
/* FSMC attributes.*/
#define STM32_HAS_FSMC FALSE
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
#define STM32_HAS_GPIOC TRUE
#define STM32_HAS_GPIOD FALSE
#define STM32_HAS_GPIOE FALSE
#define STM32_HAS_GPIOF FALSE
#define STM32_HAS_GPIOG FALSE
#define STM32_HAS_GPIOH FALSE
#define STM32_HAS_GPIOI FALSE
#define STM32_HAS_GPIOJ FALSE
#define STM32_HAS_GPIOK FALSE
#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
RCC_AHB2ENR_GPIOBEN | \
RCC_AHB2ENR_GPIOCEN)
/* GTZC attributes.*/
#if defined(STM32WL55xx) || defined(STM32WL54xx) || defined(__DOXYGEN__)
#define STM32_HAS_GTZC_TZSC TRUE
#define STM32_HAS_GTZC_TZIC TRUE
#else
#define STM32_HAS_GTZC_TZSC FALSE
#define STM32_HAS_GTZC_TZIC FALSE
#endif /* defined(STM32WL55xx) || defined(STM32WL54xx) */
#define STM32_HAS_HASH1 FALSE
/* HSEM attributes.*/
#define STM32_HAS_HSEM TRUE
#define STM32_HSEM_SEMAPHORES 16
/* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C3 TRUE
#define STM32_HAS_I2C2 FALSE
#define STM32_HAS_I2C4 FALSE
/* IWDG attributes.*/
#define STM32_HAS_IWDG TRUE
#define STM32_IWDG_IS_WINDOWED TRUE
/* LTDC attributes.*/
#define STM32_HAS_LTDC FALSE
/* PKA attributes.*/
#define STM32_HAS_PKA TRUE
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
/* Radio Transceiver (RTR) attributes.*/
#define STM32_HAS_RTR TRUE
#if defined(STM32WLE5xx) || defined(STM32WL55xx) || defined(__DOXYGEN__)
#define STM32_RTR_HAS_LORA_MODEM TRUE
#else
#define STM32_RTR_HAS_LORA_MODEM FALSE
#endif /* defined(STM32WLE5xx) || defined(STM32WL55xx) */
#define STM32_RTR_HAS_FSK_MODEM TRUE
#define STM32_RTR_HAS_MSK_MODEM TRUE
#define STM32_RTR_HAS_BPSK_MODEM TRUE
#define STM32_RTR_IRQ_EXTI 44
#define STM32_RTR_BUSY_EXTI 45
#define STM32_RTR_IRQ_HANDLER Vector108
/* RNG attributes.*/
#define STM32_HAS_RNG1 TRUE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
#define STM32_RTC_NUM_ALARMS 2
#define STM32_RTC_STORAGE_SIZE 32
#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
#define STM32_RTC_WKUP_HANDLER Vector4C
#define STM32_RTC_ALARM_HANDLER VectorE4
#define STM32_RTC_TAMP_STAMP_NUMBER 2
#define STM32_RTC_WKUP_NUMBER 3
#define STM32_RTC_ALARM_NUMBER 42
#define STM32_RTC_ALARM_EXTI 17
#define STM32_RTC_TAMP_STAMP_EXTI 19
#define STM32_RTC_WKUP_EXTI 20
#define STM32_RTC_IRQ_ENABLE() do { \
nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \
nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
} while (false)
/* SDMMC attributes.*/
#define STM32_HAS_SDMMC1 FALSE
#define STM32_HAS_SDMMC2 FALSE
/* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_HAS_SPIR TRUE
#define STM32_SPIR_SUPPORTS_I2S FALSE
#define STM32_HAS_SPI3 FALSE
#define STM32_HAS_SPI4 FALSE
#define STM32_HAS_SPI5 FALSE
#define STM32_HAS_SPI6 FALSE
/* TIM attributes.*/
#define STM32_TIM_MAX_CHANNELS 6
#define STM32_HAS_TIM1 TRUE
#define STM32_TIM1_IS_32BITS FALSE
#define STM32_TIM1_CHANNELS 6
#define STM32_HAS_TIM2 TRUE
#define STM32_TIM2_IS_32BITS TRUE
#define STM32_TIM2_CHANNELS 4
#define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM3 FALSE
#define STM32_HAS_TIM4 FALSE
#define STM32_HAS_TIM5 FALSE
#define STM32_HAS_TIM6 FALSE
#define STM32_HAS_TIM7 FALSE
#define STM32_HAS_TIM8 FALSE
#define STM32_HAS_TIM9 FALSE
#define STM32_HAS_TIM10 FALSE
#define STM32_HAS_TIM11 FALSE
#define STM32_HAS_TIM12 FALSE
#define STM32_HAS_TIM13 FALSE
#define STM32_HAS_TIM14 FALSE
#define STM32_HAS_TIM18 FALSE
#define STM32_HAS_TIM19 FALSE
#define STM32_HAS_TIM20 FALSE
#define STM32_HAS_TIM21 FALSE
#define STM32_HAS_TIM22 FALSE
/* LPTIM attributes.*/
#define STM32_HAS_LPTIM1 TRUE
#define STM32_HAS_LPTIM2 TRUE
#define STM32_HAS_LPTIM3 TRUE
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
#define STM32_HAS_USART2 TRUE
#define STM32_HAS_LPUART1 TRUE
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
#define STM32_HAS_UART5 FALSE
#define STM32_HAS_USART6 FALSE
#define STM32_HAS_UART7 FALSE
#define STM32_HAS_UART8 FALSE
/* USB attributes.*/
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
/** @} */
#endif /* STM32_REGISTRY_H */
/** @} */