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Fixed bug #1122. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_20.3.x@13855 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-09-12 08:08:24 +00:00
parent 1430e17f20
commit 2c0ead7cbb
2 changed files with 5 additions and 13 deletions
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15
os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c
View File

@ -85,7 +85,6 @@ void wdg_lld_init(void) {
*/ */
void wdg_lld_start(WDGDriver *wdgp) { void wdg_lld_start(WDGDriver *wdgp) {
#if STM32_IWDG_IS_WINDOWED
/* Enable IWDG and unlock for write.*/ /* Enable IWDG and unlock for write.*/
wdgp->wdg->KR = KR_KEY_ENABLE; wdgp->wdg->KR = KR_KEY_ENABLE;
wdgp->wdg->KR = KR_KEY_WRITE; wdgp->wdg->KR = KR_KEY_WRITE;
@ -93,24 +92,16 @@ void wdg_lld_start(WDGDriver *wdgp) {
/* Write configuration.*/ /* Write configuration.*/
wdgp->wdg->PR = wdgp->config->pr; wdgp->wdg->PR = wdgp->config->pr;
wdgp->wdg->RLR = wdgp->config->rlr; wdgp->wdg->RLR = wdgp->config->rlr;
/* Wait the registers to be updated.*/
while (wdgp->wdg->SR != 0) while (wdgp->wdg->SR != 0)
; ;
#if STM32_IWDG_IS_WINDOWED
/* This also triggers a refresh.*/ /* This also triggers a refresh.*/
wdgp->wdg->WINR = wdgp->config->winr; wdgp->wdg->WINR = wdgp->config->winr;
#else #else
/* Unlock IWDG.*/
wdgp->wdg->KR = KR_KEY_WRITE;
/* Write configuration.*/
while (wdgp->wdg->SR != 0)
;
wdgp->wdg->PR = wdgp->config->pr;
wdgp->wdg->RLR = wdgp->config->rlr;
/* Start operations.*/
wdgp->wdg->KR = KR_KEY_RELOAD; wdgp->wdg->KR = KR_KEY_RELOAD;
wdgp->wdg->KR = KR_KEY_ENABLE;
#endif #endif
} }

3
readme.txt
View File

@ -74,7 +74,8 @@
***************************************************************************** *****************************************************************************
*** 20.3.3 *** *** 20.3.3 ***
- FIX: Ignored HSIDIV setting on STM32G0xx (bug #1121) - FIX: Fixed incorrect STM32 iWDG initialization in windowed mode (bug #1122).
- FIX: Fixed ignored HSIDIV setting on STM32G0xx (bug #1121)
*** 20.3.2 *** *** 20.3.2 ***
- NEW: Support for 3 analog watchdogs in ADCv3 (STM32F3, L4, L4+, G4). - NEW: Support for 3 analog watchdogs in ADCv3 (STM32F3, L4, L4+, G4).