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ChibiOS
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More common BD code. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14380 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-05-15 17:08:09 +00:00
parent c6f4664b18
commit 2d4e29da76
4 changed files with 4 additions and 152 deletions
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39
os/hal/ports/STM32/STM32G0xx/hal_lld.c
View File

@ -46,44 +46,7 @@ uint32_t SystemCoreClock = STM32_HCLK;
/* Driver local functions. */ /* Driver local functions. */
/*===========================================================================*/ /*===========================================================================*/
/** #include "stm32_bd.inc"
* @brief Resets the backup domain.
*/
__STATIC_INLINE void bd_reset(void) {
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0U;
}
}
/**
* @brief Initializes the backup domain.
* @note WARNING! Changing RTC clock source impossible without reset
* of the whole BKP domain.
*/
__STATIC_INLINE void bd_init(void) {
uint32_t bdcr;
/* Current settings.*/
bdcr = RCC->BDCR;
#if HAL_USE_RTC
/* RTC clock enabled.*/
if ((bdcr & RCC_BDCR_RTCEN) == 0) {
bdcr |= RCC_BDCR_RTCEN;
}
#endif /* HAL_USE_RTC */
/* Selectors.*/
bdcr &= ~(STM32_RTCSEL_MASK | STM32_LSCOSEL_MASK);
bdcr |= STM32_RTCSEL | STM32_LSCOSEL;
/* Final settings.*/
RCC->BDCR = bdcr;
}
/*===========================================================================*/ /*===========================================================================*/
/* Driver interrupt handlers. */ /* Driver interrupt handlers. */

39
os/hal/ports/STM32/STM32L4xx+/hal_lld.c
View File

@ -46,44 +46,7 @@ uint32_t SystemCoreClock = STM32_HCLK;
/* Driver local functions. */ /* Driver local functions. */
/*===========================================================================*/ /*===========================================================================*/
/** #include "stm32_bd.inc"
* @brief Resets the backup domain.
*/
__STATIC_INLINE void bd_reset(void) {
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0U;
}
}
/**
* @brief Initializes the backup domain.
* @note WARNING! Changing RTC clock source impossible without reset
* of the whole BKP domain.
*/
__STATIC_INLINE void bd_init(void) {
uint32_t bdcr;
/* Current settings.*/
bdcr = RCC->BDCR;
#if HAL_USE_RTC
/* RTC clock enabled.*/
if ((bdcr & RCC_BDCR_RTCEN) == 0) {
bdcr |= RCC_BDCR_RTCEN;
}
#endif /* HAL_USE_RTC */
/* Selectors.*/
bdcr &= ~(STM32_RTCSEL_MASK | STM32_LSCOSEL_MASK);
bdcr |= STM32_RTCSEL | STM32_LSCOSEL;
/* Final settings.*/
RCC->BDCR = bdcr;
}
/*===========================================================================*/ /*===========================================================================*/
/* Driver interrupt handlers. */ /* Driver interrupt handlers. */

39
os/hal/ports/STM32/STM32L4xx/hal_lld.c
View File

@ -46,44 +46,7 @@ uint32_t SystemCoreClock = STM32_HCLK;
/* Driver local functions. */ /* Driver local functions. */
/*===========================================================================*/ /*===========================================================================*/
/** #include "stm32_bd.inc"
* @brief Resets the backup domain.
*/
__STATIC_INLINE void bd_reset(void) {
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0U;
}
}
/**
* @brief Initializes the backup domain.
* @note WARNING! Changing RTC clock source impossible without reset
* of the whole BKP domain.
*/
__STATIC_INLINE void bd_init(void) {
uint32_t bdcr;
/* Current settings.*/
bdcr = RCC->BDCR;
#if HAL_USE_RTC
/* RTC clock enabled.*/
if ((bdcr & RCC_BDCR_RTCEN) == 0) {
bdcr |= RCC_BDCR_RTCEN;
}
#endif /* HAL_USE_RTC */
/* Selectors.*/
bdcr &= ~(STM32_RTCSEL_MASK | STM32_LSCOSEL_MASK);
bdcr |= STM32_RTCSEL | STM32_LSCOSEL;
/* Final settings.*/
RCC->BDCR = bdcr;
}
/*===========================================================================*/ /*===========================================================================*/
/* Driver interrupt handlers. */ /* Driver interrupt handlers. */

39
os/hal/ports/STM32/STM32L5xx/hal_lld.c
View File

@ -52,44 +52,7 @@ uint32_t SystemCoreClock = STM32_HCLK;
/* Driver local functions. */ /* Driver local functions. */
/*===========================================================================*/ /*===========================================================================*/
/** #include "stm32_bd.inc"
* @brief Resets the backup domain.
*/
__STATIC_INLINE void bd_reset(void) {
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0U;
}
}
/**
* @brief Initializes the backup domain.
* @note WARNING! Changing RTC clock source impossible without reset
* of the whole BKP domain.
*/
__STATIC_INLINE void bd_init(void) {
uint32_t bdcr;
/* Current settings.*/
bdcr = RCC->BDCR;
#if HAL_USE_RTC
/* RTC enable.*/
if ((bdcr & RCC_BDCR_RTCEN) == 0U) {
bdcr |= RCC_BDCR_RTCEN;
}
#endif
/* Selectors.*/
bdcr &= ~(STM32_RTCSEL_MASK | STM32_LSCOSEL_MASK);
bdcr |= STM32_RTCSEL | STM32_LSCOSEL;
/* Final settings.*/
RCC->BDCR = bdcr;
}
__STATIC_INLINE void flash_ws_init(uint32_t bits) { __STATIC_INLINE void flash_ws_init(uint32_t bits) {