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ChibiOS
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Changed defaults for PLLSAIxN on STM32L4+ (72->60). 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14923 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-10-20 14:35:35 +00:00
parent 1a07eaf04d
commit 30ec4bd812
14 changed files with 28 additions and 28 deletions
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4
demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
View File

@ -93,13 +93,13 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 1
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1N_VALUE 60
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 1
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2N_VALUE 60
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6

4
demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h
View File

@ -93,13 +93,13 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 4
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1N_VALUE 60
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 4
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2N_VALUE 60
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6

4
os/hal/ports/STM32/STM32L4xx+/hal_lld.h
View File

@ -682,7 +682,7 @@
* @note The allowed values are 8..127.
*/
#if !defined(STM32_PLLSAI1N_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1N_VALUE 60
#endif
/**
@ -732,7 +732,7 @@
* @note The allowed values are 8..127.
*/
#if !defined(STM32_PLLSAI2N_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2N_VALUE 60
#endif
/**

4
testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -93,13 +93,13 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 1
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1N_VALUE 60
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 1
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2N_VALUE 60
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6

4
testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -93,13 +93,13 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 1
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1N_VALUE 60
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 1
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2N_VALUE 60
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6

4
testhal/STM32/multi/RTC/cfg/stm32l4r5_nucleo144/mcuconf.h
View File

@ -93,13 +93,13 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 1
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1N_VALUE 60
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 1
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2N_VALUE 60
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6

4
testhal/STM32/multi/SDMMC-FATFS/cfg/stm32l4r9ai_discovery/mcuconf.h
View File

@ -91,13 +91,13 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 4
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1N_VALUE 60
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 4
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2N_VALUE 60
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6

4
testhal/STM32/multi/SDMMC/cfg/stm32l4r9ai_discovery/mcuconf.h
View File

@ -91,13 +91,13 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 4
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1N_VALUE 60
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 4
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2N_VALUE 60
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6

4
testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
View File

@ -93,13 +93,13 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 1
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1N_VALUE 60
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 1
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2N_VALUE 60
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6

4
testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h
View File

@ -91,13 +91,13 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 4
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1N_VALUE 60
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 4
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2N_VALUE 60
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6

4
testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h
View File

@ -93,13 +93,13 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 1
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1N_VALUE 60
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 1
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2N_VALUE 60
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6

4
testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
View File

@ -93,13 +93,13 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 1
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1N_VALUE 60
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 1
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2N_VALUE 60
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6

4
testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h
View File

@ -93,13 +93,13 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#define STM32_PLLSAI1M_VALUE 4
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1N_VALUE 60
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
#define STM32_PLLSAI2M_VALUE 4
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2N_VALUE 60
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
#define STM32_PLLSAI2Q_VALUE 6

4
tools/ftl/processors/conf/mcuconf_stm32l4rxxx/mcuconf.h.ftl
View File

@ -102,13 +102,13 @@
#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
#define STM32_LSCOSEL ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}
#define STM32_PLLSAI1M_VALUE ${doc.STM32_PLLSAI1M_VALUE!"1"}
#define STM32_PLLSAI1N_VALUE ${doc.STM32_PLLSAI1N_VALUE!"72"}
#define STM32_PLLSAI1N_VALUE ${doc.STM32_PLLSAI1N_VALUE!"60"}
#define STM32_PLLSAI1PDIV_VALUE ${doc.STM32_PLLSAI1PDIV_VALUE!"6"}
#define STM32_PLLSAI1P_VALUE ${doc.STM32_PLLSAI1P_VALUE!"7"}
#define STM32_PLLSAI1Q_VALUE ${doc.STM32_PLLSAI1Q_VALUE!"6"}
#define STM32_PLLSAI1R_VALUE ${doc.STM32_PLLSAI1R_VALUE!"6"}
#define STM32_PLLSAI2M_VALUE ${doc.STM32_PLLSAI2M_VALUE!"1"}
#define STM32_PLLSAI2N_VALUE ${doc.STM32_PLLSAI2N_VALUE!"72"}
#define STM32_PLLSAI2N_VALUE ${doc.STM32_PLLSAI2N_VALUE!"60"}
#define STM32_PLLSAI2PDIV_VALUE ${doc.STM32_PLLSAI2PDIV_VALUE!"6"}
#define STM32_PLLSAI2P_VALUE ${doc.STM32_PLLSAI2P_VALUE!"7"}
#define STM32_PLLSAI2Q_VALUE ${doc.STM32_PLLSAI2Q_VALUE!"6"}