git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6191 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
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8d0dc4bfd6
commit
371ef2afb5
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@ -22,7 +22,6 @@
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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@ -22,7 +22,6 @@
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_EXT || defined(__DOXYGEN__)
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@ -54,10 +53,10 @@
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*
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* @isr
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*/
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CH_IRQ_HANDLER(Vector54) {
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OSAL_IRQ_HANDLER(Vector54) {
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uint32_t pr;
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CH_IRQ_PROLOGUE();
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & ((1 << 0) | (1 << 1));
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EXTI->PR = pr;
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@ -66,7 +65,7 @@ CH_IRQ_HANDLER(Vector54) {
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if (pr & (1 << 1))
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EXTD1.config->channels[1].cb(&EXTD1, 1);
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CH_IRQ_EPILOGUE();
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OSAL_IRQ_EPILOGUE();
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}
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/**
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@ -74,10 +73,10 @@ CH_IRQ_HANDLER(Vector54) {
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*
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* @isr
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*/
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CH_IRQ_HANDLER(Vector58) {
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OSAL_IRQ_HANDLER(Vector58) {
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uint32_t pr;
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CH_IRQ_PROLOGUE();
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & ((1 << 2) | (1 << 3));
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EXTI->PR = pr;
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@ -86,7 +85,7 @@ CH_IRQ_HANDLER(Vector58) {
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if (pr & (1 << 3))
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EXTD1.config->channels[3].cb(&EXTD1, 3);
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CH_IRQ_EPILOGUE();
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OSAL_IRQ_EPILOGUE();
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}
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/**
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@ -94,10 +93,10 @@ CH_IRQ_HANDLER(Vector58) {
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*
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* @isr
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*/
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CH_IRQ_HANDLER(Vector5C) {
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OSAL_IRQ_HANDLER(Vector5C) {
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uint32_t pr;
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CH_IRQ_PROLOGUE();
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) |
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(1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) |
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@ -128,7 +127,7 @@ CH_IRQ_HANDLER(Vector5C) {
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if (pr & (1 << 15))
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EXTD1.config->channels[15].cb(&EXTD1, 15);
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CH_IRQ_EPILOGUE();
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OSAL_IRQ_EPILOGUE();
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}
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/**
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@ -136,14 +135,14 @@ CH_IRQ_HANDLER(Vector5C) {
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*
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* @isr
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*/
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CH_IRQ_HANDLER(Vector44) {
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OSAL_IRQ_HANDLER(Vector44) {
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CH_IRQ_PROLOGUE();
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OSAL_IRQ_PROLOGUE();
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EXTI->PR = (1 << 16);
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EXTD1.config->channels[16].cb(&EXTD1, 16);
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CH_IRQ_EPILOGUE();
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OSAL_IRQ_EPILOGUE();
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}
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/**
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@ -151,14 +150,14 @@ CH_IRQ_HANDLER(Vector44) {
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*
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* @isr
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*/
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CH_IRQ_HANDLER(Vector48) {
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OSAL_IRQ_HANDLER(Vector48) {
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CH_IRQ_PROLOGUE();
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OSAL_IRQ_PROLOGUE();
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EXTI->PR = (1 << 17);
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EXTD1.config->channels[17].cb(&EXTD1, 17);
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CH_IRQ_EPILOGUE();
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OSAL_IRQ_EPILOGUE();
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}
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/*===========================================================================*/
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@ -172,16 +171,11 @@ CH_IRQ_HANDLER(Vector48) {
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*/
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void ext_lld_exti_irq_enable(void) {
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nvicEnableVector(EXTI0_1_IRQn,
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CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_1_IRQ_PRIORITY));
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nvicEnableVector(EXTI2_3_IRQn,
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CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_3_IRQ_PRIORITY));
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nvicEnableVector(EXTI4_15_IRQn,
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CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_15_IRQ_PRIORITY));
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nvicEnableVector(PVD_IRQn,
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CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
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nvicEnableVector(RTC_IRQn,
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CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
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nvicEnableVector(EXTI0_1_IRQn, STM32_EXT_EXTI0_1_IRQ_PRIORITY);
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nvicEnableVector(EXTI2_3_IRQn, STM32_EXT_EXTI2_3_IRQ_PRIORITY);
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nvicEnableVector(EXTI4_15_IRQn, STM32_EXT_EXTI4_15_IRQ_PRIORITY);
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nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
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nvicEnableVector(RTC_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
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}
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/**
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@ -100,11 +100,39 @@
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/* TIM attributes.*/
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 4
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 1
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 2
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 2
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#define STM32_HAS_TIM4 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM6 TRUE
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#define STM32_HAS_TIM7 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 TRUE
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#define STM32_HAS_TIM15 TRUE
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#define STM32_HAS_TIM16 TRUE
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#define STM32_HAS_TIM17 TRUE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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@ -281,6 +281,10 @@ struct context {
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}
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#endif
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#if CH_CFG_TIMEDELTA > 0
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#include "systick.h"
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#endif
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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* setting also defines the system tick time unit.
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*/
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#if !defined(CH_CFG_ST_FREQUENCY) || defined(__DOXYGEN__)
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#define CH_CFG_ST_FREQUENCY 1000
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#define CH_CFG_ST_FREQUENCY 10000
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#endif
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/**
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* this value.
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*/
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#if !defined(CH_CFG_TIMEDELTA) || defined(__DOXYGEN__)
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#define CH_CFG_TIMEDELTA 0
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#define CH_CFG_TIMEDELTA 2
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#endif
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/**
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<link>
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<name>board</name>
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<type>2</type>
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<locationURI>CHIBIOS/boards/ST_STM32F0_DISCOVERY</locationURI>
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<locationURI>CHIBIOS/os/hal/boards/ST_STM32F0_DISCOVERY</locationURI>
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</link>
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<link>
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<name>os</name>
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* setting also defines the system tick time unit.
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*/
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#if !defined(CH_CFG_ST_FREQUENCY) || defined(__DOXYGEN__)
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#define CH_CFG_ST_FREQUENCY 1000
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#define CH_CFG_ST_FREQUENCY 10000
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#endif
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/**
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* this value.
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*/
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#if !defined(CH_CFG_TIMEDELTA) || defined(__DOXYGEN__)
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#define CH_CFG_TIMEDELTA 0
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#define CH_CFG_TIMEDELTA 2
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#endif
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/**
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* @note The default is @p FALSE.
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*/
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#if !defined(CH_DBG_STATISTICS) || defined(__DOXYGEN__)
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#define CH_DBG_STATISTICS TRUE
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#define CH_DBG_STATISTICS FALSE
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#endif
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/**
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/* Triggered when the button is pressed or released. The LED4 is set to ON.*/
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static void extcb1(EXTDriver *extp, expchannel_t channel) {
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static VirtualTimer vt4;
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static virtual_timer_t vt4;
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(void)extp;
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(void)channel;
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palSetPad(GPIOC, GPIOC_LED4);
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chSysLockFromIsr();
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if (chVTIsArmedI(&vt4))
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chVTResetI(&vt4);
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chSysLockFromISR();
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chVTResetI(&vt4);
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/* LED4 set to OFF after 200mS.*/
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chVTSetI(&vt4, MS2ST(200), led4off, NULL);
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chSysUnlockFromIsr();
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chSysUnlockFromISR();
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}
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static const EXTConfig extcfg = {
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<link>
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<name>board</name>
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<type>2</type>
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<locationURI>CHIBIOS/boards/ST_STM32F0_DISCOVERY</locationURI>
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<locationURI>CHIBIOS/os/hal/boards/ST_STM32F0_DISCOVERY</locationURI>
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</link>
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<link>
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<name>os</name>
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* setting also defines the system tick time unit.
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*/
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#if !defined(CH_CFG_ST_FREQUENCY) || defined(__DOXYGEN__)
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#define CH_CFG_ST_FREQUENCY 1000
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#define CH_CFG_ST_FREQUENCY 10000
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#endif
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/**
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* this value.
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*/
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#if !defined(CH_CFG_TIMEDELTA) || defined(__DOXYGEN__)
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#define CH_CFG_TIMEDELTA 0
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#define CH_CFG_TIMEDELTA 2
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#endif
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/**
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* @note The default is @p FALSE.
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*/
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#if !defined(CH_DBG_STATISTICS) || defined(__DOXYGEN__)
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#define CH_DBG_STATISTICS TRUE
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#define CH_DBG_STATISTICS FALSE
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#endif
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/**
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@ -368,7 +368,7 @@
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* @note The default is @p FALSE.
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*/
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#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
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#define CH_DBG_SYSTEM_STATE_CHECK TRUE
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#define CH_DBG_SYSTEM_STATE_CHECK FALSE
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#endif
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/**
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* @note The default is @p FALSE.
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*/
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#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
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#define CH_DBG_ENABLE_CHECKS TRUE
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#define CH_DBG_ENABLE_CHECKS FALSE
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#endif
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/**
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@ -391,7 +391,7 @@
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* @note The default is @p FALSE.
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*/
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#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
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#define CH_DBG_ENABLE_ASSERTS TRUE
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#define CH_DBG_ENABLE_ASSERTS FALSE
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#endif
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/**
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@ -402,7 +402,7 @@
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* @note The default is @p FALSE.
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*/
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#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
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#define CH_DBG_ENABLE_TRACE TRUE
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#define CH_DBG_ENABLE_TRACE FALSE
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#endif
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/**
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@ -416,7 +416,7 @@
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* @p panic_msg variable set to @p NULL.
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*/
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#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
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#define CH_DBG_ENABLE_STACK_CHECK TRUE
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#define CH_DBG_ENABLE_STACK_CHECK FALSE
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#endif
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/**
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@ -428,7 +428,7 @@
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* @note The default is @p FALSE.
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*/
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#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
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#define CH_DBG_FILL_THREADS TRUE
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#define CH_DBG_FILL_THREADS FALSE
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#endif
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/**
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* tickless mode.
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*/
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#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
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#define CH_DBG_THREADS_PROFILING TRUE
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#define CH_DBG_THREADS_PROFILING FALSE
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#endif
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/** @} */
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@ -51,7 +51,7 @@ static bool_t saturated;
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/*
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* Mailboxes and buffers.
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*/
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static Mailbox mb[NUM_THREADS];
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static mailbox_t mb[NUM_THREADS];
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static msg_t b[NUM_THREADS][MAILBOX_SIZE];
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/*
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@ -101,7 +101,7 @@ static msg_t WorkerThread(void *arg) {
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/* If this thread is not at the end of a chain re-sending the message,
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note this check works because the variable target is unsigned.*/
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msg = chMBPost(&mb[target], msg, TIME_IMMEDIATE);
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if (msg != RDY_OK)
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if (msg != MSG_OK)
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saturated = TRUE;
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}
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else {
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@ -121,11 +121,11 @@ static void gpt2cb(GPTDriver *gptp) {
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msg_t msg;
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(void)gptp;
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chSysLockFromIsr();
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chSysLockFromISR();
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msg = chMBPostI(&mb[0], MSG_SEND_RIGHT);
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if (msg != RDY_OK)
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if (msg != MSG_OK)
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saturated = TRUE;
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chSysUnlockFromIsr();
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chSysUnlockFromISR();
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}
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/*
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@ -135,11 +135,11 @@ static void gpt3cb(GPTDriver *gptp) {
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msg_t msg;
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(void)gptp;
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chSysLockFromIsr();
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chSysLockFromISR();
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msg = chMBPostI(&mb[NUM_THREADS - 1], MSG_SEND_LEFT);
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if (msg != RDY_OK)
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if (msg != MSG_OK)
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saturated = TRUE;
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chSysUnlockFromIsr();
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chSysUnlockFromISR();
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}
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/*
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@ -217,14 +217,14 @@ int main(void) {
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sdStart(&SD1, NULL);
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palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(1)); /* USART1 TX. */
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palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(1)); /* USART1 RX. */
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gptStart(&GPTD2, &gpt2cfg);
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gptStart(&GPTD1, &gpt2cfg);
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gptStart(&GPTD3, &gpt3cfg);
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/*
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* Initializes the mailboxes and creates the worker threads.
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*/
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for (i = 0; i < NUM_THREADS; i++) {
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chMBInit(&mb[i], b[i], MAILBOX_SIZE);
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chMBObjectInit(&mb[i], b[i], MAILBOX_SIZE);
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chThdCreateStatic(waWorkerThread[i], sizeof waWorkerThread[i],
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NORMALPRIO - 20, WorkerThread, (void *)i);
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}
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|
@ -287,10 +287,10 @@ int main(void) {
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saturated = FALSE;
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threshold = 0;
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for (interval = 2000; interval >= 20; interval -= interval / 10) {
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gptStartContinuous(&GPTD2, interval - 1); /* Slightly out of phase.*/
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gptStartContinuous(&GPTD1, interval - 1); /* Slightly out of phase.*/
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gptStartContinuous(&GPTD3, interval + 1); /* Slightly out of phase.*/
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chThdSleepMilliseconds(1000);
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gptStopTimer(&GPTD2);
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gptStopTimer(&GPTD1);
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gptStopTimer(&GPTD3);
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if (!saturated)
|
||||
print(".");
|
||||
|
@ -311,7 +311,7 @@ int main(void) {
|
|||
if (threshold > worst)
|
||||
worst = threshold;
|
||||
}
|
||||
gptStopTimer(&GPTD2);
|
||||
gptStopTimer(&GPTD1);
|
||||
gptStopTimer(&GPTD3);
|
||||
|
||||
print("Worst case at ");
|
||||
|
|
|
@ -77,12 +77,12 @@
|
|||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 FALSE
|
||||
#define STM32_GPT_USE_TIM2 TRUE
|
||||
#define STM32_GPT_USE_TIM1 TRUE
|
||||
#define STM32_GPT_USE_TIM2 FALSE
|
||||
#define STM32_GPT_USE_TIM3 TRUE
|
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY 2
|
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY 1
|
||||
#define STM32_GPT_TIM2_IRQ_PRIORITY 2
|
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY 2
|
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY 3
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
|
|
|
@ -27,7 +27,7 @@
|
|||
<link>
|
||||
<name>board</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS/boards/ST_STM32F0_DISCOVERY</locationURI>
|
||||
<locationURI>CHIBIOS/os/hal/boards/ST_STM32F0_DISCOVERY</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>os</name>
|
||||
|
|
|
@ -41,7 +41,7 @@
|
|||
* setting also defines the system tick time unit.
|
||||
*/
|
||||
#if !defined(CH_CFG_ST_FREQUENCY) || defined(__DOXYGEN__)
|
||||
#define CH_CFG_ST_FREQUENCY 1000
|
||||
#define CH_CFG_ST_FREQUENCY 10000
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -62,7 +62,7 @@
|
|||
* this value.
|
||||
*/
|
||||
#if !defined(CH_CFG_TIMEDELTA) || defined(__DOXYGEN__)
|
||||
#define CH_CFG_TIMEDELTA 0
|
||||
#define CH_CFG_TIMEDELTA 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -357,7 +357,7 @@
|
|||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_STATISTICS) || defined(__DOXYGEN__)
|
||||
#define CH_DBG_STATISTICS TRUE
|
||||
#define CH_DBG_STATISTICS FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -441,7 +441,7 @@
|
|||
* tickless mode.
|
||||
*/
|
||||
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
|
||||
#define CH_DBG_THREADS_PROFILING TRUE
|
||||
#define CH_DBG_THREADS_PROFILING FALSE
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
|
|
@ -90,11 +90,11 @@ int main(void) {
|
|||
/*
|
||||
* Initializes the PWM driver 2 and ICU driver 3.
|
||||
* GPIOA6 is the ICU input (CH1).
|
||||
* GPIOA15 is the PWM output (CH1).
|
||||
* GPIOA8 is the PWM output (CH1).
|
||||
* The two pins have to be externally connected together.
|
||||
*/
|
||||
pwmStart(&PWMD2, &pwmcfg);
|
||||
palSetPadMode(GPIOA, 15, PAL_MODE_ALTERNATE(2));
|
||||
pwmStart(&PWMD1, &pwmcfg);
|
||||
palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(2));
|
||||
icuStart(&ICUD3, &icucfg);
|
||||
palSetPadMode(GPIOA, 6, PAL_MODE_ALTERNATE(1));
|
||||
icuEnable(&ICUD3);
|
||||
|
@ -103,33 +103,33 @@ int main(void) {
|
|||
/*
|
||||
* Starts the PWM channel 0 using 75% duty cycle.
|
||||
*/
|
||||
pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 7500));
|
||||
pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 7500));
|
||||
chThdSleepMilliseconds(5000);
|
||||
|
||||
/*
|
||||
* Changes the PWM channel 0 to 50% duty cycle.
|
||||
*/
|
||||
pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 5000));
|
||||
pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000));
|
||||
chThdSleepMilliseconds(5000);
|
||||
|
||||
/*
|
||||
* Changes the PWM channel 0 to 25% duty cycle.
|
||||
*/
|
||||
pwmEnableChannel(&PWMD2, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD2, 2500));
|
||||
pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 2500));
|
||||
chThdSleepMilliseconds(5000);
|
||||
|
||||
/*
|
||||
* Changes PWM period to half second the duty cycle becomes 50%
|
||||
* implicitly.
|
||||
*/
|
||||
pwmChangePeriod(&PWMD2, 5000);
|
||||
pwmChangePeriod(&PWMD1, 5000);
|
||||
chThdSleepMilliseconds(5000);
|
||||
|
||||
/*
|
||||
* Disables channel 0 and stops the drivers.
|
||||
*/
|
||||
pwmDisableChannel(&PWMD2, 0);
|
||||
pwmStop(&PWMD2);
|
||||
pwmDisableChannel(&PWMD1, 0);
|
||||
pwmStop(&PWMD1);
|
||||
icuDisable(&ICUD3);
|
||||
icuStop(&ICUD3);
|
||||
palClearPad(GPIOC, GPIOC_LED3);
|
||||
|
|
|
@ -110,8 +110,8 @@
|
|||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED FALSE
|
||||
#define STM32_PWM_USE_TIM1 FALSE
|
||||
#define STM32_PWM_USE_TIM2 TRUE
|
||||
#define STM32_PWM_USE_TIM1 TRUE
|
||||
#define STM32_PWM_USE_TIM2 FALSE
|
||||
#define STM32_PWM_USE_TIM3 FALSE
|
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY 3
|
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY 3
|
||||
|
|
|
@ -12,7 +12,7 @@ The application demonstrates the use of the STM32F0xx PWM-ICU drivers.
|
|||
|
||||
** Board Setup **
|
||||
|
||||
- Connect PA15 and PC6 together.
|
||||
- Connect PA8 and PA6 together.
|
||||
|
||||
** Build Procedure **
|
||||
|
||||
|
|
|
@ -27,7 +27,7 @@
|
|||
<link>
|
||||
<name>board</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS/boards/ST_STM32F0_DISCOVERY</locationURI>
|
||||
<locationURI>CHIBIOS/os/hal/boards/ST_STM32F0_DISCOVERY</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>os</name>
|
||||
|
|
|
@ -41,7 +41,7 @@
|
|||
* setting also defines the system tick time unit.
|
||||
*/
|
||||
#if !defined(CH_CFG_ST_FREQUENCY) || defined(__DOXYGEN__)
|
||||
#define CH_CFG_ST_FREQUENCY 1000
|
||||
#define CH_CFG_ST_FREQUENCY 10000
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -62,7 +62,7 @@
|
|||
* this value.
|
||||
*/
|
||||
#if !defined(CH_CFG_TIMEDELTA) || defined(__DOXYGEN__)
|
||||
#define CH_CFG_TIMEDELTA 0
|
||||
#define CH_CFG_TIMEDELTA 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -357,7 +357,7 @@
|
|||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_STATISTICS) || defined(__DOXYGEN__)
|
||||
#define CH_DBG_STATISTICS TRUE
|
||||
#define CH_DBG_STATISTICS FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -441,7 +441,7 @@
|
|||
* tickless mode.
|
||||
*/
|
||||
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
|
||||
#define CH_DBG_THREADS_PROFILING TRUE
|
||||
#define CH_DBG_THREADS_PROFILING FALSE
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
|
|
@ -27,7 +27,7 @@
|
|||
<link>
|
||||
<name>board</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS/boards/ST_STM32F0_DISCOVERY</locationURI>
|
||||
<locationURI>CHIBIOS/os/hal/boards/ST_STM32F0_DISCOVERY</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>os</name>
|
||||
|
|
|
@ -41,7 +41,7 @@
|
|||
* setting also defines the system tick time unit.
|
||||
*/
|
||||
#if !defined(CH_CFG_ST_FREQUENCY) || defined(__DOXYGEN__)
|
||||
#define CH_CFG_ST_FREQUENCY 1000
|
||||
#define CH_CFG_ST_FREQUENCY 10000
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -62,7 +62,7 @@
|
|||
* this value.
|
||||
*/
|
||||
#if !defined(CH_CFG_TIMEDELTA) || defined(__DOXYGEN__)
|
||||
#define CH_CFG_TIMEDELTA 0
|
||||
#define CH_CFG_TIMEDELTA 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -357,7 +357,7 @@
|
|||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_STATISTICS) || defined(__DOXYGEN__)
|
||||
#define CH_DBG_STATISTICS TRUE
|
||||
#define CH_DBG_STATISTICS FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -441,7 +441,7 @@
|
|||
* tickless mode.
|
||||
*/
|
||||
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
|
||||
#define CH_DBG_THREADS_PROFILING TRUE
|
||||
#define CH_DBG_THREADS_PROFILING FALSE
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
|
|
@ -17,15 +17,15 @@
|
|||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
|
||||
static VirtualTimer vt1, vt2;
|
||||
static virtual_timer_t vt1, vt2;
|
||||
|
||||
static void restart(void *p) {
|
||||
|
||||
(void)p;
|
||||
|
||||
chSysLockFromIsr();
|
||||
chSysLockFromISR();
|
||||
uartStartSendI(&UARTD1, 14, "Hello World!\r\n");
|
||||
chSysUnlockFromIsr();
|
||||
chSysUnlockFromISR();
|
||||
}
|
||||
|
||||
static void ledoff(void *p) {
|
||||
|
@ -51,11 +51,10 @@ static void txend2(UARTDriver *uartp) {
|
|||
|
||||
(void)uartp;
|
||||
palClearPad(GPIOC, GPIOC_LED4);
|
||||
chSysLockFromIsr();
|
||||
if (chVTIsArmedI(&vt1))
|
||||
chVTResetI(&vt1);
|
||||
chSysLockFromISR();
|
||||
chVTResetI(&vt1);
|
||||
chVTSetI(&vt1, MS2ST(5000), restart, NULL);
|
||||
chSysUnlockFromIsr();
|
||||
chSysUnlockFromISR();
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -78,11 +77,10 @@ static void rxchar(UARTDriver *uartp, uint16_t c) {
|
|||
(void)c;
|
||||
/* Flashing the LED each time a character is received.*/
|
||||
palSetPad(GPIOC, GPIOC_LED4);
|
||||
chSysLockFromIsr();
|
||||
if (chVTIsArmedI(&vt2))
|
||||
chVTResetI(&vt2);
|
||||
chSysLockFromISR();
|
||||
chVTResetI(&vt2);
|
||||
chVTSetI(&vt2, MS2ST(200), ledoff, NULL);
|
||||
chSysUnlockFromIsr();
|
||||
chSysUnlockFromISR();
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
Loading…
Reference in New Issue