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FDCAN divider support. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16297 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2023-06-20 07:29:02 +00:00
parent a208d65eba
commit 3c6524b866
2 changed files with 31 additions and 0 deletions
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20
os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.c
View File

@ -217,6 +217,26 @@ void can_lld_init(void) {
CAND3.fdcan = FDCAN3;
CAND3.ram_base = (uint32_t *)(SRAMCAN_BASE + 2U * SRAMCAN_SIZE);
#endif
/* Configure global CKDIV for STM32G4XX */
#if defined(STM32G4XX) && STM32_CAN_CKDIV != 0
/* CAND1 needs to be put into configuration mode to allow CKDIV configuration */
rccEnableFDCAN(true);
if (fdcan_clock_stop(&CAND1)) {
osalDbgAssert(false, "CAN clock stop failed, check clocks and pin config");
return;
}
if (fdcan_init_mode(&CAND1)) {
osalDbgAssert(false, "CAN initialization failed, check clocks and pin config");
return;
}
CAND1.fdcan->CCCR |= FDCAN_CCCR_CCE;
/* Write actual configuration into CKDIV register */
FDCAN_CONFIG->CKDIV = STM32_CAN_CKDIV;
rccDisableFDCAN();
#endif
}
/**

11
os/hal/ports/STM32/LLD/FDCANv1/hal_can_lld.h
View File

@ -54,6 +54,13 @@
* @name Configuration options
* @{
*/
/**
* @brief Global clock divisor configuration (requires FDCAN1)
*/
#if (defined(STM32G4XX) && !defined(STM32_CAN_CKDIV)) || defined(__DOXYGEN__)
#define STM32_CAN_CKDIV 0
#endif
/**
* @brief CAN1 driver enable switch.
* @details If set to @p TRUE the support for FDCAN1 is included.
@ -143,6 +150,10 @@
#error "STM32_FDCAN_TM_NBR not defined in registry"
#endif
#if defined(STM32G4XX) && ((STM32_CAN_CKDIV != 0) && !defined(STM32_CAN_USE_FDCAN1))
#error "STM32_HAS_FDCAN1 is required for configuring STM32_CAN_CKDIV != 0"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/