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Added CR2 setting to STM32 SPIv1 driver. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9640 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2016-06-17 12:58:41 +00:00
parent 67b83e80b6
commit 458e6a84df
6 changed files with 19 additions and 6 deletions
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3
os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c
View File

@ -425,7 +425,8 @@ void spi_lld_start(SPIDriver *spip) {
spip->spi->CR1 = 0;
spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM |
SPI_CR1_SSI;
spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
spip->spi->CR2 = spip->config->cr2 | SPI_CR2_SSOE | SPI_CR2_RXDMAEN |
SPI_CR2_TXDMAEN;
spip->spi->CR1 |= SPI_CR1_SPE;
}

6
os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.h
View File

@ -431,9 +431,13 @@ typedef struct {
*/
uint16_t sspad;
/**
* @brief SPI initialization data.
* @brief SPI CR1 register initialization data.
*/
uint16_t cr1;
/**
* @brief SPI CR2 register initialization data.
*/
uint16_t cr2;
} SPIConfig;
/**

4
testhal/STM32/STM32F1xx/SPI/main.c
View File

@ -24,6 +24,7 @@ static const SPIConfig hs_spicfg = {
NULL,
GPIOA,
GPIOA_SPI1NSS,
0,
0
};
@ -34,7 +35,8 @@ static const SPIConfig ls_spicfg = {
NULL,
GPIOA,
GPIOA_SPI1NSS,
SPI_CR1_BR_2 | SPI_CR1_BR_1
SPI_CR1_BR_2 | SPI_CR1_BR_1,
0
};
/*

4
testhal/STM32/STM32F4xx/SPI/main.c
View File

@ -24,6 +24,7 @@ static const SPIConfig hs_spicfg = {
NULL,
GPIOB,
12,
0,
0
};
@ -34,7 +35,8 @@ static const SPIConfig ls_spicfg = {
NULL,
GPIOB,
12,
SPI_CR1_BR_2 | SPI_CR1_BR_1
SPI_CR1_BR_2 | SPI_CR1_BR_1,
0
};
/*

4
testhal/STM32/STM32L0xx/SPI/main.c
View File

@ -24,6 +24,7 @@ static const SPIConfig hs_spicfg = {
NULL,
GPIOB,
12,
0,
0
};
@ -34,7 +35,8 @@ static const SPIConfig ls_spicfg = {
NULL,
GPIOB,
12,
SPI_CR1_BR_2 | SPI_CR1_BR_1
SPI_CR1_BR_2 | SPI_CR1_BR_1,
0
};
/*

4
testhal/STM32/STM32L1xx/SPI/main.c
View File

@ -24,6 +24,7 @@ static const SPIConfig hs_spicfg = {
NULL,
GPIOB,
12,
0,
0
};
@ -34,7 +35,8 @@ static const SPIConfig ls_spicfg = {
NULL,
GPIOB,
12,
SPI_CR1_BR_2 | SPI_CR1_BR_1
SPI_CR1_BR_2 | SPI_CR1_BR_1,
0
};
/*