STM32C0 drivers test-compiled. RTC requires rework because it has no TAMP.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16354 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -73,7 +73,7 @@
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#define STM32_I2C1SEL STM32_I2C1SEL_PCLK
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#define STM32_I2C1SEL STM32_I2C1SEL_PCLK
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#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
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#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
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#define STM32_RTCSEL STM32_RTCSEL_LSE
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/*
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/*
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* Shared IRQ settings.
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* Shared IRQ settings.
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/*===========================================================================*/
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/*===========================================================================*/
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/* Supported devices checks.*/
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/* Supported devices checks.*/
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#if !defined(STM32G0XX) && !defined(STM32WLXX)
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#if !defined(STM32C0XX) && !defined(STM32G0XX) && !defined(STM32WLXX)
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#error "ADCv5 only supports G0 and WL STM32 devices"
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#error "ADCv5 only supports C0, G0 and WL STM32 devices"
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#endif
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#endif
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/* Registry checks.*/
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/* Registry checks.*/
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@ -61,6 +61,8 @@
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#define STM32_DMA1_CH1_NUMBER 9
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#define STM32_DMA1_CH1_NUMBER 9
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#define STM32_DMA1_CH23_NUMBER 10
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#define STM32_DMA1_CH23_NUMBER 10
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#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
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#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
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#define STM32_DMA1_CH1_CMASK 0x00000001U
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#define STM32_DMA1_CH1_CMASK 0x00000001U
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#define STM32_DMA1_CH2_CMASK 0x00000006U
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#define STM32_DMA1_CH2_CMASK 0x00000006U
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*
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*
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* @api
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* @api
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*/
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*/
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#define rccEnableTIM16(lp) rccEnableAPB(RCC_APBENR2_TIM16EN, lp)
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#define rccEnableTIM16(lp) rccEnableAPBR2(RCC_APBENR2_TIM16EN, lp)
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/**
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/**
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* @brief Disables the TIM16 peripheral clock.
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* @brief Disables the TIM16 peripheral clock.
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