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STM32C0 drivers test-compiled. RTC requires rework because it has no TAMP. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16354 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2023-07-31 09:15:59 +00:00
parent 0de96b017a
commit 473a0c858a
4 changed files with 6 additions and 4 deletions
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2
demos/STM32/NIL-STM32C031C6-NUCLEO64/cfg/mcuconf.h
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@ -73,7 +73,7 @@
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK
#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
* Shared IRQ settings.

4
os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h
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@ -209,8 +209,8 @@
/*===========================================================================*/
/* Supported devices checks.*/
#if !defined(STM32G0XX) && !defined(STM32WLXX)
#error "ADCv5 only supports G0 and WL STM32 devices"
#if !defined(STM32C0XX) && !defined(STM32G0XX) && !defined(STM32WLXX)
#error "ADCv5 only supports C0, G0 and WL STM32 devices"
#endif
/* Registry checks.*/

2
os/hal/ports/STM32/STM32C0xx/stm32_isr.h
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@ -61,6 +61,8 @@
#define STM32_DMA1_CH1_NUMBER 9
#define STM32_DMA1_CH23_NUMBER 10
#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
#define STM32_DMA1_CH1_CMASK 0x00000001U
#define STM32_DMA1_CH2_CMASK 0x00000006U

2
os/hal/ports/STM32/STM32C0xx/stm32_rcc.h
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@ -494,7 +494,7 @@
*
* @api
*/
#define rccEnableTIM16(lp) rccEnableAPB(RCC_APBENR2_TIM16EN, lp)
#define rccEnableTIM16(lp) rccEnableAPBR2(RCC_APBENR2_TIM16EN, lp)
/**
* @brief Disables the TIM16 peripheral clock.