Fixed Bug #746
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_16.1.x@9530 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -633,32 +633,32 @@
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#endif
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/**
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* @brief MC01 clock source value.
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* @note The default value outputs HSI clock on MC01 pin.
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* @brief MCO1 clock source value.
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* @note The default value outputs HSI clock on MCO1 pin.
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*/
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#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#endif
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/**
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* @brief MC01 prescaler value.
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* @note The default value outputs HSI clock on MC01 pin.
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* @brief MCO1 prescaler value.
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* @note The default value outputs HSI clock on MCO1 pin.
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*/
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#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#endif
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/**
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* @brief MC02 clock source value.
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* @note The default value outputs SYSCLK / 5 on MC02 pin.
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* @brief MCO2 clock source value.
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* @note The default value outputs SYSCLK / 5 on MCO2 pin.
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*/
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#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#endif
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/**
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* @brief MC02 prescaler value.
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* @note The default value outputs SYSCLK / 5 on MC02 pin.
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* @brief MCO2 prescaler value.
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* @note The default value outputs SYSCLK / 5 on MCO2 pin.
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*/
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#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
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@ -194,11 +194,11 @@
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* @name RCC_PLLCFGR register bits definitions
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* @{
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*/
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#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */
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#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */
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#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */
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#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */
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#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */
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#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */
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#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */
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#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */
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#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */
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#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */
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#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */
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#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */
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@ -224,14 +224,14 @@
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#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
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#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
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#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */
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#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */
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#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */
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#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */
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#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */
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#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */
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#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */
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#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */
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#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */
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#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */
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#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */
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#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */
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@ -582,32 +582,32 @@
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#endif
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/**
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* @brief MC01 clock source value.
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* @note The default value outputs HSI clock on MC01 pin.
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* @brief MCO1 clock source value.
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* @note The default value outputs HSI clock on MCO1 pin.
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*/
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#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#endif
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/**
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* @brief MC01 prescaler value.
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* @note The default value outputs HSI clock on MC01 pin.
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* @brief MCO1 prescaler value.
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* @note The default value outputs HSI clock on MCO1 pin.
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*/
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#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#endif
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/**
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* @brief MC02 clock source value.
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* @note The default value outputs SYSCLK / 4 on MC02 pin.
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* @brief MCO2 clock source value.
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* @note The default value outputs SYSCLK / 4 on MCO2 pin.
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*/
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#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#endif
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/**
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* @brief MC02 prescaler value.
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* @note The default value outputs SYSCLK / 4 on MC02 pin.
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* @brief MCO2 prescaler value.
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* @note The default value outputs SYSCLK / 4 on MCO2 pin.
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*/
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#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
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@ -73,6 +73,8 @@
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*****************************************************************************
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*** 16.1.5 ***
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- HAL: Fixed wrong comments and indent in STM32F4xx and STM32F7xx
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hal_lld.h (bug #746).
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- HAL: Removed wrong SAI masks in STM32F4xx hal_lld.h (bug #745).
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- HAL: Fixed wrong mask placement in STM32F4xx hal_lld.h (bug #744).
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- HAL: Fixed wrong indent in STM32F4xx hal_lld.h (bug #743).
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