Added more clock handlers for RCCv2.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14813 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
62d5bc81ae
commit
5567835ef7
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@ -0,0 +1,109 @@
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/*
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ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file RCCv1/stm32_csi.inc
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* @brief Shared CSI clock handler.
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*
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* @addtogroup STM32_CSI_HANDLER
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* @{
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*/
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @brief CSI clock frequency.
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*/
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#define STM32_CSICLK 4000000U
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* Registry checks for robustness.*/
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#if !defined(STM32_RCC_HAS_CSI)
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#error "STM32_RCC_HAS_CSI not defined in stm32_registry.h"
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#endif
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/* Checks on configurations.*/
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#if !defined(STM32_CSI_ENABLED)
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#error "STM32_CSI_ENABLED not defined in mcuconf.h"
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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__STATIC_INLINE void csi_enable(void) {
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#if 0
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RCC->CR |= RCC_CR_HSION;
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while ((RCC->CR & RCC_CR_HSIRDY) == 0U) {
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/* Waiting for CSI activation.*/
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}
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#endif
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}
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__STATIC_INLINE void csi_disable(void) {
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#if 0
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RCC->CR &= ~RCC_CR_HSION;
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#endif
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}
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__STATIC_INLINE void csi_reset(void) {
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#if 0
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/* Making sure HSI is active and ready.*/
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hsi16_enable();
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/* Clocking from HSI, in case HSI was not the default source.*/
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RCC->CFGR = RCC_CFGR_SW_HSI;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {
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/* Wait until HSI is selected.*/
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}
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#endif
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}
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__STATIC_INLINE void csi_init(void) {
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#if 0
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#if STM32_CSI_ENABLED
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/* HSI activation.*/
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hsi16_enable();
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#endif
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#endif
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/** @} */
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@ -0,0 +1,131 @@
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/*
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ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file RCCv2/stm32_hse.inc
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* @brief Shared HSE clock handler.
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*
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* @addtogroup STM32_HSE_HANDLER
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* @{
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*/
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* Registry checks for robustness.*/
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#if !defined(STM32_RCC_HAS_HSE)
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#error "STM32_RCC_HAS_HSE not defined in stm32_registry.h"
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#endif
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/* Checks on configurations.*/
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#if !defined(STM32_HSE_ENABLED)
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#error "STM32_HSE_ENABLED not defined in mcuconf.h"
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#endif
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#if !defined(STM32_HSECLK)
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#error "STM32_HSECLK not defined in board.h"
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#endif
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/* Check on limits.*/
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#if !defined(STM32_HSECLK_MAX)
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#error "STM32_HSECLK_MAX not defined in hal_lld.h"
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#endif
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#if !defined(STM32_HSECLK_MIN)
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#error "STM32_HSECLK_MIN not defined in hal_lld.h"
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#endif
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#if !defined(STM32_HSECLK_BYP_MAX)
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#error "STM32_HSECLK_BYP_MAX not defined in hal_lld.h"
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#endif
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#if !defined(STM32_HSECLK_BYP_MIN)
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#error "STM32_HSECLK_BYP_MIN not defined in hal_lld.h"
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#endif
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#if STM32_HSE_ENABLED
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#if STM32_HSECLK == 0
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#error "HSE frequency not defined"
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#else /* STM32_HSECLK != 0 */
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#if defined(STM32_HSE_BYPASS)
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#if (STM32_HSECLK < STM32_HSECLK_BYP_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
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#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_BYP_MIN...STM32_HSECLK_BYP_MAX)"
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#endif
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#else /* !defined(STM32_HSE_BYPASS) */
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#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
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#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
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#endif
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#endif /* !defined(STM32_HSE_BYPASS) */
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#endif /* STM32_HSECLK != 0 */
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#endif /* STM32_HSE_ENABLED */
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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__STATIC_INLINE void hse_enable(void) {
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#if 0
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#if defined(STM32_HSE_BYPASS)
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/* HSE Bypass case.*/
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RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
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#else
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RCC->CR |= RCC_CR_HSEON;
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#endif
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while ((RCC->CR & RCC_CR_HSERDY) == 0U) {
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/* Waiting for HSE activation.*/
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}
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#endif
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}
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__STATIC_INLINE void hse_disable(void) {
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#if 0
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RCC->CR &= ~RCC_CR_HSEON;
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#endif
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}
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__STATIC_INLINE void hse_init(void) {
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#if 0
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#if STM32_HSE_ENABLED
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hse_enable();
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#endif
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#endif
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/** @} */
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@ -0,0 +1,109 @@
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/*
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ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file RCCv1/stm32_hsi64.inc
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* @brief Shared HSI64 clock handler.
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*
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* @addtogroup STM32_HSI64_HANDLER
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* @{
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*/
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @brief HSI64 clock frequency.
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*/
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#define STM32_HSI64CLK 64000000U
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* Registry checks for robustness.*/
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#if !defined(STM32_RCC_HAS_HSI64)
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#error "STM32_RCC_HAS_HSI64 not defined in stm32_registry.h"
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#endif
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/* Checks on configurations.*/
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#if !defined(STM32_HSI64_ENABLED)
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#error "STM32_HSI64_ENABLED not defined in mcuconf.h"
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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__STATIC_INLINE void hsi65_enable(void) {
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#if 0
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RCC->CR |= RCC_CR_HSION;
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while ((RCC->CR & RCC_CR_HSIRDY) == 0U) {
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/* Waiting for HSI64 activation.*/
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}
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#endif
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}
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__STATIC_INLINE void hsi16_disable(void) {
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#if 0
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RCC->CR &= ~RCC_CR_HSION;
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#endif
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}
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__STATIC_INLINE void hsi64_reset(void) {
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#if 0
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/* Making sure HSI is active and ready.*/
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hsi16_enable();
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/* Clocking from HSI, in case HSI was not the default source.*/
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RCC->CFGR = RCC_CFGR_SW_HSI;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {
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/* Wait until HSI is selected.*/
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}
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#endif
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}
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__STATIC_INLINE void hsi64_init(void) {
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#if 0
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#if STM32_HSI64_ENABLED
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/* HSI activation.*/
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hsi16_enable();
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#endif
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#endif
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/** @} */
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@ -91,15 +91,6 @@
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#define CLK_ARRAY_SIZE 12U
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/** @} */
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/**
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* @name Internal clocks
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* @{
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*/
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#define STM32_HSICLK 64000000
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#define STM32_CSICLK 4000000
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#define STM32_LSICLK 32000
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/** @} */
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/**
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* @name RCC_RCK3SELR register bits definitions
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* @{
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@ -193,17 +184,41 @@
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#define STM32_I2S_CKIN_VALUE 0
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#endif
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/**
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* @brief Enables or disables the HSE clock source.
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* @note This initialization is performed only if TZEN=0
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* otherwise the setting must match the initialization performed
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* on the Cortex-A side.
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*/
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#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
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#define STM32_HSE_ENABLED TRUE
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#endif
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/**
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* @brief Enables or disables the HSI64 clock source.
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* @note This initialization is performed only if TZEN=0
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* otherwise the setting must match the initialization performed
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* on the Cortex-A side.
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*/
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#if !defined(STM32_HSI64_ENABLED) || defined(__DOXYGEN__)
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#define STM32_HSI64_ENABLED TRUE
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#endif
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/**
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* @brief Enables or disables the CSI clock source.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0
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* otherwise the setting must match the initialization performed
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* on the Cortex-A side.
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*/
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#if !defined(STM32_CSI_ENABLED) || defined(__DOXYGEN__)
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#define STM32_CSI_ENABLED FALSE
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#define STM32_CSI_ENABLED TRUE
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#endif
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/**
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* @brief Clock source for the PLL3.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0
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* otherwise the setting must match the initialization performed
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* on the Cortex-A side.
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*/
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#if !defined(STM32_PLL3SRC) || defined(__DOXYGEN__)
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#define STM32_PLL3SRC STM32_PLL3SRC_HSE
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@ -212,7 +227,9 @@
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/**
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* @brief PLL3 M divider value.
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* @note The allowed values are 1..64.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0
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* otherwise the setting must match the initialization performed
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* on the Cortex-A side.
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*/
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#if !defined(STM32_PLL3DIVM_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLL3DIVM_VALUE 3
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@ -221,7 +238,9 @@
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/**
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* @brief PLL3 N multiplier value.
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* @note The allowed values are 25..200.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0
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* otherwise the setting must match the initialization performed
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* on the Cortex-A side.
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*/
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#if !defined(STM32_PLL3DIVN_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLL3DIVN_VALUE 50
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@ -230,7 +249,9 @@
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/**
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* @brief PLL3 P divider value or zero if disabled.
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* @note The allowed values are 1..128.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0
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* otherwise the setting must match the initialization performed
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* on the Cortex-A side.
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*/
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#if !defined(STM32_PLL3DIVP_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLL3DIVP_VALUE 2
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@ -239,7 +260,9 @@
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/**
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* @brief PLL3 Q divider value.
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* @note The allowed values are 1..128.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0
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* otherwise the setting must match the initialization performed
|
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* on the Cortex-A side.
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*/
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#if !defined(STM32_PLL3DIVQ_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLL3DIVQ_VALUE 4
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@ -248,7 +271,9 @@
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/**
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* @brief PLL3 R divider value.
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* @note The allowed values are 1..128.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0
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* otherwise the setting must match the initialization performed
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* on the Cortex-A side.
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*/
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#if !defined(STM32_PLL3DIVR_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLL3DIVR_VALUE 4
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@ -303,7 +328,9 @@
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/**
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* @brief MCU divider setting.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0
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* otherwise the setting must match the initialization performed
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* on the Cortex-A side.
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*/
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#if !defined(STM32_MCUDIV) || defined(__DOXYGEN__)
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#define STM32_MCUDIV 2222222222
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@ -311,7 +338,9 @@
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/**
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* @brief MCU main clock source selection.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0.
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* @note This initialization is performed only if TZEN=0 or MCKPROT=0
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* otherwise the setting must match the initialization performed
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* on the Cortex-A side.
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*/
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#if !defined(STM32_MCUSSRC) || defined(__DOXYGEN__)
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#define STM32_MCUSSRC 2222222222
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@ -405,6 +434,12 @@
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* @{
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*/
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#define STM32_MCUSS_CK_MAX 209000000
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||||
#define STM32_HSECLK_MAX 48000000
|
||||
#define STM32_HSECLK_MIN 8000000
|
||||
#define STM32_HSECLK_BYP_MAX 48000000
|
||||
#define STM32_HSECLK_BYP_MIN 8000000
|
||||
|
||||
#define STM32_PLL3INCLK_MAX 16000000
|
||||
#define STM32_PLL3INCLK_MIN 4000000
|
||||
#define STM32_PLL3INCLK_SD_MIN 8000000
|
||||
|
|
@ -443,8 +478,9 @@
|
|||
#endif
|
||||
|
||||
/* Clock handlers.*/
|
||||
//#include "stm32_csi.inc"
|
||||
//#include "stm32_hsi64.inc"
|
||||
#include "stm32_csi.inc"
|
||||
#include "stm32_hsi64.inc"
|
||||
#include "stm32_hse.inc"
|
||||
|
||||
/*
|
||||
* CSI related checks.
|
||||
|
|
@ -469,7 +505,7 @@
|
|||
* @brief PLL3 input clock frequency.
|
||||
*/
|
||||
#if (STM32_PLL3SRC == STM32_PLL3SRC_HSI) || defined(__DOXYGEN__)
|
||||
#define STM32_PLL3MCLK STM32_HSICLK
|
||||
#define STM32_PLL3MCLK STM32_HSI64CLK
|
||||
|
||||
#elif STM32_PLL3SRC == STM32_PLL3SRC_HSE
|
||||
#define STM32_PLL3MCLK STM32_HSECLK
|
||||
|
|
@ -539,7 +575,7 @@
|
|||
* @brief PLL4 input clock frequency.
|
||||
*/
|
||||
#if (STM32_PLL4SRC == STM32_PLL4SRC_HSI) || defined(__DOXYGEN__)
|
||||
#define STM32_PLL4MCLK STM32_HSICLK
|
||||
#define STM32_PLL4MCLK STM32_HSI64CLK
|
||||
|
||||
#elif STM32_PLL4SRC == STM32_PLL4SRC_HSE
|
||||
#define STM32_PLL4MCLK STM32_HSECLK
|
||||
|
|
|
|||
|
|
@ -53,6 +53,9 @@
|
|||
defined(__DOXYGEN__)
|
||||
|
||||
/* RCC attributes.*/
|
||||
#define STM32_RCC_HAS_CSI TRUE
|
||||
#define STM32_RCC_HAS_HSI64 TRUE
|
||||
#define STM32_RCC_HAS_HSE TRUE
|
||||
#define STM32_RCC_HAS_PLL3 TRUE
|
||||
#define STM32_RCC_PLL3_HAS_P TRUE
|
||||
#define STM32_RCC_PLL3_HAS_Q TRUE
|
||||
|
|
|
|||
Loading…
Reference in New Issue