git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@201 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
parent
9d95345fd7
commit
58ab6d53dd
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@ -78,10 +78,11 @@ ASRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c \
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TSRC =
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# List ASM source files here
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ASMSRC = ../../ports/ARM7-AT91SAM7X/GCC/crt0.s
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ASMSRC = ../../ports/ARM7-AT91SAM7X/GCC/crt0.s ../../ports/ARM7/chsys.s
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# List all user directories here
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UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-AT91SAM7X/GCC
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UINCDIR = ../../src/include ../../src/lib \
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../../ports/ARM7 ../../ports/ARM7-AT91SAM7X/GCC
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# List the user directory to look for the libraries here
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ULIBDIR =
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@ -130,6 +131,7 @@ ODFLAGS = -x --syms
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# Thumb interwork enabled only if needed because it kills performance.
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ifneq ($(TSRC),)
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CPFLAGS += -D THUMB_PRESENT
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ASFLAGS += -D THUMB_PRESENT
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ifneq ($(ASRC),)
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# Mixed ARM and THUMB case.
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CPFLAGS += -mthumb-interwork
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@ -78,10 +78,11 @@ TSRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c \
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board.c main.c
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# List ASM source files here
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ASMSRC = ../../ports/ARM7-AT91SAM7X/GCC/crt0.s
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ASMSRC = ../../ports/ARM7-AT91SAM7X/GCC/crt0.s ../../ports/ARM7/chsys.s
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# List all user directories here
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UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-AT91SAM7X/GCC
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UINCDIR = ../../src/include ../../src/lib \
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../../ports/ARM7 ../../ports/ARM7-AT91SAM7X/GCC
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# List the user directory to look for the libraries here
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ULIBDIR =
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@ -130,6 +131,7 @@ ODFLAGS = -x --syms
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# Thumb interwork enabled only if needed because it kills performance.
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ifneq ($(TSRC),)
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CPFLAGS += -D THUMB_PRESENT
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ASFLAGS += -D THUMB_PRESENT
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ifneq ($(ASRC),)
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# Mixed ARM and THUMB case.
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CPFLAGS += -mthumb-interwork
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@ -30,7 +30,7 @@ static void SpuriousHandler(void) {
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chSysIRQEnterI();
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AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)AT91C_BASE_AIC;
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AT91C_BASE_AIC->AIC_EOICR = 0;
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chSysIRQExitI();
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}
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@ -47,6 +47,7 @@ static void SYSIrqHandler(void) {
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(void) AT91C_BASE_PITC->PITC_PIVR;
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chSysTimerHandlerI();
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}
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AT91C_BASE_AIC->AIC_EOICR = 0; \
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chSysIRQExitI();
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}
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@ -33,194 +33,12 @@ void _IdleThread(void *p) {
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}
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}
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/*
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* The following functions are present only if there is in the system any
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* code compiled as THUMB that may invoke them.
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* NOTE: The undefs are there in case this module is compiled in ARM mode but
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* there are THUMB modules in the system.
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*/
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#ifdef THUMB_PRESENT
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#undef chSysLock
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void chSysLock(void) {
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#ifdef THUMB
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asm(".p2align 2,, \n\t" \
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"mov r0, pc \n\t" \
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"bx r0 \n\t" \
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".code 32 \n\t");
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#endif
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asm("msr CPSR_c, #0x9F \n\t" \
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"bx lr \n\t");
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}
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#undef chSysUnlock
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void chSysUnlock(void) {
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#ifdef THUMB
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asm(".p2align 2,, \n\t" \
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"mov r0, pc \n\t" \
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"bx r0 \n\t" \
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".code 32 \n\t");
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#endif
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asm("msr CPSR_c, #0x1F \n\t" \
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"bx lr \n\t");
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}
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#endif
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void chSysSwitchI(Thread *otp, Thread *ntp) {
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#ifdef THUMB
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asm(".p2align 2,, \n\t" \
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"mov r2, pc \n\t" \
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"bx r2 \n\t" \
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".code 32 \n\t");
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#endif
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#ifdef CH_CURRP_REGISTER_CACHE
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asm("stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} \n\t" \
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"str sp, [r0, #16] \n\t" \
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"ldr sp, [r1, #16] \n\t");
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#ifdef THUMB_PRESENT
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asm("ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} \n\t" \
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"bx lr \n\t");
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#else /* !THUMB_PRESENT */
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asm("ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc} \n\t");
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#endif /* !THUMB_PRESENT */
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#else /* !CH_CURRP_REGISTER_CACHE */
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asm("stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} \n\t" \
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"str sp, [r0, #16] \n\t" \
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"ldr sp, [r1, #16] \n\t");
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#ifdef THUMB_PRESENT
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asm("ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} \n\t" \
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"bx lr \n\t");
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#else /* !THUMB_PRESENT */
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asm("ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} \n\t");
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#endif /* !THUMB_PRESENT */
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#endif /* !CH_CURRP_REGISTER_CACHE */
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}
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/*
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* System console message (not implemented).
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*/
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void chSysPuts(char *msg) {
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}
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/*
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* Common IRQ exit code, \p chSysIRQExitI() just jumps here.
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*
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* System stack frame structure after a context switch in the
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* interrupt handler:
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*
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* High +------------+
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* | LR_USR | -+
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* | R12 | |
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* | R3 | |
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* | R2 | | External context: IRQ handler frame
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* | R1 | |
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* | R0 | |
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* | LR_IRQ | | (user code return address)
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* | SPSR | -+ (user code status)
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* | .... | <- chSchDoRescheduleI() stack frame, optimize it for space
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* | LR | -+ (system code return address)
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* | R11 | |
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* | R10 | |
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* | R9 | |
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* | R8 | | Internal context: chSysSwitchI() frame
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* | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE)
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* | R6 | |
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* | R5 | |
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* SP-> | R4 | -+
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* Low +------------+
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*/
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__attribute__((naked, weak))
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void IrqCommon(void) {
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register BOOL b asm("r0");
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AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)AT91C_BASE_AIC;
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b = chSchRescRequiredI();
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#ifdef THUMB
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asm(".p2align 2,, \n\t" \
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"mov lr, pc \n\t" \
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"bx lr \n\t" \
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".code 32 \n\t");
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#endif
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/*
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* If a reschedulation is not required then just returns from the IRQ.
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*/
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asm("cmp r0, #0 \n\t" \
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"ldmeqfd sp!, {r0-r3, r12, lr} \n\t" \
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"subeqs pc, lr, #4 \n\t");
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/*
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* Reschedulation required, saves the external context on the
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* system/user stack and empties the IRQ stack.
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*/
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asm(".set MODE_IRQ, 0x12 \n\t" \
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".set MODE_SYS, 0x1F \n\t" \
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".set F_BIT, 0x40 \n\t" \
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".set I_BIT, 0x80 \n\t" \
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"ldmfd sp!, {r0-r3, r12, lr} \n\t" \
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"msr CPSR_c, #MODE_SYS | I_BIT \n\t" \
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"stmfd sp!, {r0-r3, r12, lr} \n\t" \
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"msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \
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"mrs r0, SPSR \n\t" \
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"mov r1, lr \n\t" \
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"msr CPSR_c, #MODE_SYS | I_BIT \n\t" \
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"stmfd sp!, {r0, r1} \n\t");
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#ifdef THUMB_NO_INTERWORKING
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asm("add r0, pc, #1 \n\t" \
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"bx r0 \n\t" \
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".code 16 \n\t" \
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"bl chSchDoRescheduleI \n\t" \
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".p2align 2,, \n\t" \
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"mov lr, pc \n\t" \
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"bx lr \n\t" \
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".code 32 \n\t");
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#else
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asm("bl chSchDoRescheduleI \n\t");
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#endif
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/*
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* Restores the external context.
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*/
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asm("ldmfd sp!, {r0, r1} \n\t" \
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"msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \
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"msr SPSR_fsxc, r0 \n\t" \
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"mov lr, r1 \n\t" \
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"msr CPSR_c, #MODE_SYS | I_BIT \n\t" \
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"ldmfd sp!, {r0-r3, r12, lr} \n\t" \
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"msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \
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"subs pc, lr, #4 \n\t");
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/*
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* Threads entry/exit code. It is declared weak so you can easily replace it.
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* NOTE: It is always invoked in ARM mode, it does the mode switching.
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* NOTE: It is included into IrqCommon to make sure the symbol refers to
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* 32 bit code.
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*/
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asm(".weak threadstart \n\t" \
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".globl threadstart \n\t" \
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"threadstart: \n\t" \
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"msr CPSR_c, #MODE_SYS \n\t");
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#ifndef THUMB_NO_INTERWORKING
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asm("mov r0, r5 \n\t" \
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"mov lr, pc \n\t" \
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"bx r4 \n\t" \
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"bl chThdExit \n\t");
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#else
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asm("add r0, pc, #1 \n\t" \
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"bx r0 \n\t" \
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".code 16 \n\t" \
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"mov r0, r5 \n\t" \
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"bl jmpr4 \n\t" \
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"bl chThdExit \n\t" \
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"jmpr4: \n\t" \
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"bx r4 \n\t");
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#endif
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}
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/*
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* System halt.
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*/
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@ -228,8 +46,8 @@ __attribute__((naked, weak))
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void chSysHalt(void) {
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#ifdef THUMB
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asm("ldr r0, =_halt32 \n\t" \
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"bx r0 \n\t");
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asm("b _halt16");
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#else
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asm("b _halt32");
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#endif
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asm("b _halt32 \n\t");
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}
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@ -169,10 +169,4 @@ AbortHandler:
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.globl FiqHandler
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FiqHandler:
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.weak _halt32
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.globl _halt32
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_halt32:
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mrs r0, CPSR
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orr r0, #I_BIT | F_BIT
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msr CPSR_c, r0
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.loop: b .loop
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@ -63,6 +63,7 @@ static void ServeInterrupt(AT91PS_USART u, FullDuplexDriver *com) {
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SetError(u->US_CSR, com);
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u->US_CR = AT91C_US_RSTSTA;
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}
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AT91C_BASE_AIC->AIC_EOICR = 0; \
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}
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__attribute__((naked, weak))
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@ -116,6 +116,10 @@ extern void chSysUnlock(void);
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}
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#endif /* !THUMB */
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#ifdef THUMB
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#define chSysSwitchI chSysSwitchI_thumb
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#endif /* THUMB */
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/* It requires zero bytes, but better be safe.*/
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#define IDLE_THREAD_STACK_SIZE 8
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void _IdleThread(void *p) __attribute__((noreturn));
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@ -0,0 +1,225 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* ARM7 port system code.
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*/
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#include <chconf.h>
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.set MODE_USR, 0x10
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.set MODE_FIQ, 0x11
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.set MODE_IRQ, 0x12
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.set MODE_SVC, 0x13
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.set MODE_ABT, 0x17
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.set MODE_UND, 0x1B
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.set MODE_SYS, 0x1F
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.equ I_BIT, 0x80
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.equ F_BIT, 0x40
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.text
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/*
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* Interrupt enable/disable functions, only present if there is THUMB code in
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* the system because those are inlined in ARM code.
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*/
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#ifdef THUMB_PRESENT
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.balign 16
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.code 16
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.thumb_func
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.global chSysLock
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chSysLock:
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mov r0, pc
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bx r0
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.code 32
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msr CPSR_c, #MODE_SYS | I_BIT
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bx lr
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.balign 16
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.code 16
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.thumb_func
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.global chSysUnlock
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chSysUnlock:
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mov r0, pc
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bx r0
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.code 32
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msr CPSR_c, #MODE_SYS
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bx lr
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#endif
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.balign 16
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#ifdef THUMB_PRESENT
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.code 16
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.thumb_func
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.global chSysSwitchI_thumb
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chSysSwitchI_thumb:
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mov r2, pc
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bx r2
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// Jumps into chSysSwitchI in ARM mode
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#endif
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.code 32
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.global chSysSwitchI
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chSysSwitchI:
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#ifdef CH_CURRP_REGISTER_CACHE
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stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr}
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str sp, [r0, #16]
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ldr sp, [r1, #16]
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#ifdef THUMB_PRESENT
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ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr}
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bx lr
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#else /* !THUMB_PRESENT */
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ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc}
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#endif /* !THUMB_PRESENT */
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#else /* !CH_CURRP_REGISTER_CACHE */
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stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}
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str sp, [r0, #16]
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ldr sp, [r1, #16]
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#ifdef THUMB_PRESENT
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ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}
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bx lr
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#else /* !THUMB_PRESENT */
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ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
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#endif /* !THUMB_PRESENT */
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#endif /* !CH_CURRP_REGISTER_CACHE */
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/*
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* Common exit point for all IRQ routines, it performs the rescheduling if
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* required.
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* System stack frame structure after a context switch in the
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* interrupt handler:
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*
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* High +------------+
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* | LR_USR | -+
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* | R12 | |
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* | R3 | |
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* | R2 | | External context: IRQ handler frame
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* | R1 | |
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* | R0 | |
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* | LR_IRQ | | (user code return address)
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* | SPSR | -+ (user code status)
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* | .... | <- mk_DoRescheduleI() stack frame, optimize it for space
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* | LR | -+ (system code return address)
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* | R11 | |
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* | R10 | |
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* | R9 | |
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* | R8 | | Internal context: mk_SwitchI() frame
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* | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE)
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* | R6 | |
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* | R5 | |
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||||
* SP-> | R4 | -+
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* Low +------------+
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*/
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.balign 16
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#ifdef THUMB_NO_INTERWORKING
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.code 16
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.thumb_func
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.globl IrqCommon
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IrqCommon:
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bl chSchRescRequiredI
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mov lr, pc
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bx lr
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.code 32
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#else /* !THUMB_NO_INTERWORKING */
|
||||
.code 32
|
||||
.globl IrqCommon
|
||||
IrqCommon:
|
||||
bl chSchRescRequiredI
|
||||
#endif /* !THUMB_NO_INTERWORKING */
|
||||
cmp r0, #0 // Simply returns if a
|
||||
ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not
|
||||
subeqs pc, lr, #4 // required.
|
||||
|
||||
// Saves the IRQ mode registers in the system stack.
|
||||
ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty.
|
||||
msr CPSR_c, #MODE_SYS | I_BIT
|
||||
stmfd sp!, {r0-r3, r12, lr} // Registers on System Stack.
|
||||
msr CPSR_c, #MODE_IRQ | I_BIT
|
||||
mrs r0, SPSR
|
||||
mov r1, lr
|
||||
msr CPSR_c, #MODE_SYS | I_BIT
|
||||
stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ.
|
||||
|
||||
// Context switch.
|
||||
#ifdef THUMB_NO_INTERWORKING
|
||||
add r0, pc, #1
|
||||
bx r0
|
||||
.code 16
|
||||
bl chSchDoRescheduleI
|
||||
mov lr, pc
|
||||
bx lr
|
||||
.code 32
|
||||
#else /* !THUMB_NO_INTERWORKING */
|
||||
bl chSchDoRescheduleI
|
||||
#endif /* !THUMB_NO_INTERWORKING */
|
||||
|
||||
// Re-establish the IRQ conditions again.
|
||||
ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ.
|
||||
msr CPSR_c, #MODE_IRQ | I_BIT
|
||||
msr SPSR_fsxc, r0
|
||||
mov lr, r1
|
||||
msr CPSR_c, #MODE_SYS | I_BIT
|
||||
ldmfd sp!, {r0-r3, r12, lr}
|
||||
msr CPSR_c, #MODE_IRQ | I_BIT
|
||||
subs pc, lr, #4
|
||||
|
||||
/*
|
||||
* Threads trampoline code.
|
||||
* NOTE: The threads always start in ARM mode then switch to the thread-function mode.
|
||||
*/
|
||||
.balign 16
|
||||
.code 32
|
||||
.globl threadstart
|
||||
threadstart:
|
||||
msr CPSR_c, #MODE_SYS
|
||||
#ifndef THUMB_NO_INTERWORKING
|
||||
mov r0, r5
|
||||
mov lr, pc
|
||||
bx r4
|
||||
bl chThdExit
|
||||
#else /* !THUMB_NO_INTERWORKING */
|
||||
add r0, pc, #1
|
||||
bx r0
|
||||
.code 16
|
||||
mov r0, r5
|
||||
bl jmpr4
|
||||
bl chThdExit
|
||||
jmpr4:
|
||||
bx r4
|
||||
#endif /* !THUMB_NO_INTERWORKING */
|
||||
|
||||
/*
|
||||
* System stop code.
|
||||
*/
|
||||
.code 16
|
||||
.p2align 2,,
|
||||
.thumb_func
|
||||
.weak _halt16
|
||||
.globl _halt16
|
||||
_halt16:
|
||||
mov r0, pc
|
||||
bx r0
|
||||
.code 32
|
||||
.weak _halt32
|
||||
.globl _halt32
|
||||
_halt32:
|
||||
mrs r0, CPSR
|
||||
orr r0, #I_BIT | F_BIT
|
||||
msr CPSR_c, r0
|
||||
.loop: b .loop
|
Loading…
Reference in New Issue