git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6369 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
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2be22cfd28
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@ -41,9 +41,9 @@
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#define STM32_VDD 300
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#define STM32_VDD 300
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/*
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/*
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* MCU type as defined in the ST header file stm32f4xx.h.
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* MCU type as defined in the ST header.
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*/
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*/
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#define STM32F4XX
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#define STM32F40_41xxx
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/*
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/*
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* IO pins assignments.
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* IO pins assignments.
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@ -1,17 +1,21 @@
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/*
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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Licensed under the Apache License, Version 2.0 (the "License");
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This file is part of ChibiOS/RT.
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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||||||
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(at your option) any later version.
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||||||
|
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||||||
Unless required by applicable law or agreed to in writing, software
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ChibiOS/RT is distributed in the hope that it will be useful,
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distributed under the License is distributed on an "AS IS" BASIS,
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||||
See the License for the specific language governing permissions and
|
GNU General Public License for more details.
|
||||||
limitations under the License.
|
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||||||
|
You should have received a copy of the GNU General Public License
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||||||
|
along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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#include "ch.h"
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#include "ch.h"
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@ -1,17 +1,21 @@
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/*
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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|
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Licensed under the Apache License, Version 2.0 (the "License");
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This file is part of ChibiOS/RT.
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
|
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|
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http://www.apache.org/licenses/LICENSE-2.0
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ChibiOS/RT is free software; you can redistribute it and/or modify
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|
it under the terms of the GNU General Public License as published by
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|
the Free Software Foundation; either version 3 of the License, or
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|
(at your option) any later version.
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||||||
|
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Unless required by applicable law or agreed to in writing, software
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ChibiOS/RT is distributed in the hope that it will be useful,
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distributed under the License is distributed on an "AS IS" BASIS,
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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See the License for the specific language governing permissions and
|
GNU General Public License for more details.
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limitations under the License.
|
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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#ifndef _BOARD_H_
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#ifndef _BOARD_H_
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@ -52,9 +56,9 @@
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#define STM32_VDD 330
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#define STM32_VDD 330
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/*
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/*
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* MCU type as defined in the ST header file stm32f4xx.h.
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* MCU type as defined in the ST header.
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*/
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*/
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#define STM32F4XX
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#define STM32F401xx
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/*
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/*
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* IO pins assignments.
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* IO pins assignments.
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@ -22,6 +22,7 @@
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<identifier>MII_KS8721_ID</identifier>
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<identifier>MII_KS8721_ID</identifier>
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<bus_type>RMII</bus_type>
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<bus_type>RMII</bus_type>
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</ethernet_phy>
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</ethernet_phy>
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<subtype>STM32F40_41xxx</subtype>
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<clocks HSEFrequency="12000000" HSEBypass="false" LSEFrequency="32768"
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<clocks HSEFrequency="12000000" HSEBypass="false" LSEFrequency="32768"
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VDD="330" />
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VDD="330" />
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<ports>
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<ports>
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@ -1,17 +1,21 @@
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/*
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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Licensed under the Apache License, Version 2.0 (the "License");
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This file is part of ChibiOS/RT.
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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ChibiOS/RT is free software; you can redistribute it and/or modify
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|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3 of the License, or
|
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|
(at your option) any later version.
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|
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Unless required by applicable law or agreed to in writing, software
|
ChibiOS/RT is distributed in the hope that it will be useful,
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||||||
distributed under the License is distributed on an "AS IS" BASIS,
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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See the License for the specific language governing permissions and
|
GNU General Public License for more details.
|
||||||
limitations under the License.
|
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|
You should have received a copy of the GNU General Public License
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|
along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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#include "ch.h"
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#include "ch.h"
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@ -1,24 +1,28 @@
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/*
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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|
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Licensed under the Apache License, Version 2.0 (the "License");
|
This file is part of ChibiOS/RT.
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you may not use this file except in compliance with the License.
|
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You may obtain a copy of the License at
|
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|
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http://www.apache.org/licenses/LICENSE-2.0
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ChibiOS/RT is free software; you can redistribute it and/or modify
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|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3 of the License, or
|
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|
(at your option) any later version.
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|
|
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Unless required by applicable law or agreed to in writing, software
|
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||||
distributed under the License is distributed on an "AS IS" BASIS,
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
See the License for the specific language governing permissions and
|
GNU General Public License for more details.
|
||||||
limitations under the License.
|
|
||||||
|
You should have received a copy of the GNU General Public License
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||||||
|
along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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#ifndef _BOARD_H_
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#ifndef _BOARD_H_
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#define _BOARD_H_
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#define _BOARD_H_
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/*
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/*
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* Setup for Olimex STM32-E407 board.
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* Setup for Olimex STM32-H407 board.
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*/
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*/
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/*
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/*
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#define STM32_VDD 330
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#define STM32_VDD 330
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/*
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/*
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* MCU type as defined in the ST header file stm32f4xx.h.
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* MCU type as defined in the ST header.
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*/
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*/
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#define STM32F4XX
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#define STM32F40_41xxx
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/*
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/*
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* IO pins assignments.
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* IO pins assignments.
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@ -69,20 +73,20 @@
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#define GPIOA_ETH_RMII_CRS_DV 7
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#define GPIOA_ETH_RMII_CRS_DV 7
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#define GPIOA_USB_HS_BUSON 8
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#define GPIOA_USB_HS_BUSON 8
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#define GPIOA_OTG_FS_VBUS 9
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#define GPIOA_OTG_FS_VBUS 9
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#define GPIOA_USB_FS_BUSON 10
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#define GPIOA_OTG_FS_ID 10
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#define GPIOA_OTG_FS_DM 11
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#define GPIOA_OTG_FS_DM 11
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#define GPIOA_OTG_FS_DP 12
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#define GPIOA_OTG_FS_DP 12
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#define GPIOA_JTAG_TMS 13
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#define GPIOA_JTAG_TMS 13
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#define GPIOA_JTAG_TCK 14
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#define GPIOA_JTAG_TCK 14
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#define GPIOA_JTAG_TDI 15
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#define GPIOA_JTAG_TDI 15
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#define GPIOB_PIN0 0
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#define GPIOB_USB_FS_BUSON 0
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#define GPIOB_PIN1 1
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#define GPIOB_USB_HS_FAULT 1
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#define GPIOB_BOOT1 2
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#define GPIOB_BOOT1 2
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#define GPIOB_JTAG_TDO 3
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#define GPIOB_JTAG_TDO 3
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#define GPIOB_JTAG_TRST 4
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#define GPIOB_JTAG_TRST 4
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#define GPIOB_USB_HS_FAULT 5
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#define GPIOB_PIN5 5
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#define GPIOB_USB_FS_FAULT 6
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#define GPIOB_PIN6 6
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#define GPIOB_PIN7 7
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#define GPIOB_PIN7 7
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#define GPIOB_I2C1_SCL 8
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#define GPIOB_I2C1_SCL 8
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#define GPIOB_I2C1_SDA 9
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#define GPIOB_I2C1_SDA 9
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#define GPIOF_PIN8 8
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#define GPIOF_PIN8 8
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#define GPIOF_PIN9 9
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#define GPIOF_PIN9 9
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#define GPIOF_PIN10 10
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#define GPIOF_PIN10 10
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#define GPIOF_PIN11 11
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#define GPIOF_USB_FS_FAULT 11
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#define GPIOF_PIN12 12
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#define GPIOF_PIN12 12
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#define GPIOF_PIN13 13
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#define GPIOF_PIN13 13
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#define GPIOF_PIN14 14
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#define GPIOF_PIN14 14
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@ -247,7 +251,7 @@
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* PA7 - ETH_RMII_CRS_DV (alternate 11).
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* PA7 - ETH_RMII_CRS_DV (alternate 11).
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* PA8 - USB_HS_BUSON (output pushpull maximum).
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* PA8 - USB_HS_BUSON (output pushpull maximum).
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* PA9 - OTG_FS_VBUS (input pulldown).
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* PA9 - OTG_FS_VBUS (input pulldown).
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* PA10 - USB_FS_BUSON (output pushpull maximum).
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* PA10 - OTG_FS_ID (alternate 10).
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* PA11 - OTG_FS_DM (alternate 10).
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* PA11 - OTG_FS_DM (alternate 10).
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* PA12 - OTG_FS_DP (alternate 10).
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* PA12 - OTG_FS_DP (alternate 10).
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* PA13 - JTAG_TMS (alternate 0).
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* PA13 - JTAG_TMS (alternate 0).
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@ -264,7 +268,7 @@
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PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) |\
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PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) |\
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PIN_MODE_OUTPUT(GPIOA_USB_HS_BUSON) | \
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PIN_MODE_OUTPUT(GPIOA_USB_HS_BUSON) | \
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PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) | \
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PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) | \
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PIN_MODE_OUTPUT(GPIOA_USB_FS_BUSON) | \
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PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \
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PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
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PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
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PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
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PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
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PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) | \
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PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) | \
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PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_CRS_DV) |\
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PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_CRS_DV) |\
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PIN_OTYPE_PUSHPULL(GPIOA_USB_HS_BUSON) |\
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PIN_OTYPE_PUSHPULL(GPIOA_USB_HS_BUSON) |\
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PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_VBUS) |\
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PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_VBUS) |\
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PIN_OTYPE_PUSHPULL(GPIOA_USB_FS_BUSON) |\
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PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \
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PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
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PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
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PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
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PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
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PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) | \
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PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) | \
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@ -296,7 +300,7 @@
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PIN_OSPEED_100M(GPIOA_ETH_RMII_CRS_DV) |\
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PIN_OSPEED_100M(GPIOA_ETH_RMII_CRS_DV) |\
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PIN_OSPEED_100M(GPIOA_USB_HS_BUSON) | \
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PIN_OSPEED_100M(GPIOA_USB_HS_BUSON) | \
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PIN_OSPEED_100M(GPIOA_OTG_FS_VBUS) | \
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PIN_OSPEED_100M(GPIOA_OTG_FS_VBUS) | \
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PIN_OSPEED_100M(GPIOA_USB_FS_BUSON) | \
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PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \
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PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \
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PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \
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PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \
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PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \
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PIN_OSPEED_100M(GPIOA_JTAG_TMS) | \
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PIN_OSPEED_100M(GPIOA_JTAG_TMS) | \
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@ -312,7 +316,7 @@
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PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_CRS_DV) |\
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PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_CRS_DV) |\
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PIN_PUPDR_FLOATING(GPIOA_USB_HS_BUSON) |\
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PIN_PUPDR_FLOATING(GPIOA_USB_HS_BUSON) |\
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PIN_PUPDR_PULLDOWN(GPIOA_OTG_FS_VBUS) |\
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PIN_PUPDR_PULLDOWN(GPIOA_OTG_FS_VBUS) |\
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||||||
PIN_PUPDR_FLOATING(GPIOA_USB_FS_BUSON) |\
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PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \
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||||||
PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
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PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
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||||||
PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
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PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
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||||||
PIN_PUPDR_FLOATING(GPIOA_JTAG_TMS) | \
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PIN_PUPDR_FLOATING(GPIOA_JTAG_TMS) | \
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@ -328,7 +332,7 @@
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PIN_ODR_HIGH(GPIOA_ETH_RMII_CRS_DV) | \
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PIN_ODR_HIGH(GPIOA_ETH_RMII_CRS_DV) | \
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||||||
PIN_ODR_HIGH(GPIOA_USB_HS_BUSON) | \
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PIN_ODR_HIGH(GPIOA_USB_HS_BUSON) | \
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||||||
PIN_ODR_HIGH(GPIOA_OTG_FS_VBUS) | \
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PIN_ODR_HIGH(GPIOA_OTG_FS_VBUS) | \
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||||||
PIN_ODR_HIGH(GPIOA_USB_FS_BUSON) | \
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PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \
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||||||
PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
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PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
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||||||
PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
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PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
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||||||
PIN_ODR_HIGH(GPIOA_JTAG_TMS) | \
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PIN_ODR_HIGH(GPIOA_JTAG_TMS) | \
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@ -344,7 +348,7 @@
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PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11))
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PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11))
|
||||||
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_HS_BUSON, 0) | \
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#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_HS_BUSON, 0) | \
|
||||||
PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0) | \
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PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0) | \
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PIN_AFIO_AF(GPIOA_USB_FS_BUSON, 0) | \
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PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \
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||||||
PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
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PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
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||||||
PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
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PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
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||||||
PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) | \
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PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) | \
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||||||
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@ -354,13 +358,13 @@
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/*
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/*
|
||||||
* GPIOB setup:
|
* GPIOB setup:
|
||||||
*
|
*
|
||||||
* PB0 - PIN0 (input pullup).
|
* PB0 - USB_FS_BUSON (output pushpull maximum).
|
||||||
* PB1 - PIN1 (input pullup).
|
* PB1 - USB_HS_FAULT (input floating).
|
||||||
* PB2 - BOOT1 (input floating).
|
* PB2 - BOOT1 (input floating).
|
||||||
* PB3 - JTAG_TDO (alternate 0).
|
* PB3 - JTAG_TDO (alternate 0).
|
||||||
* PB4 - JTAG_TRST (alternate 0).
|
* PB4 - JTAG_TRST (alternate 0).
|
||||||
* PB5 - USB_HS_FAULT (input floating).
|
* PB5 - PIN5 (input pullup).
|
||||||
* PB6 - USB_FS_FAULT (input floating).
|
* PB6 - PIN6 (input pullup).
|
||||||
* PB7 - PIN7 (input pullup).
|
* PB7 - PIN7 (input pullup).
|
||||||
* PB8 - I2C1_SCL (alternate 4).
|
* PB8 - I2C1_SCL (alternate 4).
|
||||||
* PB9 - I2C1_SDA (alternate 4).
|
* PB9 - I2C1_SDA (alternate 4).
|
||||||
|
@ -371,13 +375,13 @@
|
||||||
* PB14 - OTG_HS_DM (alternate 12).
|
* PB14 - OTG_HS_DM (alternate 12).
|
||||||
* PB15 - OTG_HS_DP (alternate 12).
|
* PB15 - OTG_HS_DP (alternate 12).
|
||||||
*/
|
*/
|
||||||
#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
|
#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_USB_FS_BUSON) | \
|
||||||
PIN_MODE_INPUT(GPIOB_PIN1) | \
|
PIN_MODE_INPUT(GPIOB_USB_HS_FAULT) | \
|
||||||
PIN_MODE_INPUT(GPIOB_BOOT1) | \
|
PIN_MODE_INPUT(GPIOB_BOOT1) | \
|
||||||
PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) | \
|
PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) | \
|
||||||
PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) | \
|
PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) | \
|
||||||
PIN_MODE_INPUT(GPIOB_USB_HS_FAULT) | \
|
PIN_MODE_INPUT(GPIOB_PIN5) | \
|
||||||
PIN_MODE_INPUT(GPIOB_USB_FS_FAULT) | \
|
PIN_MODE_INPUT(GPIOB_PIN6) | \
|
||||||
PIN_MODE_INPUT(GPIOB_PIN7) | \
|
PIN_MODE_INPUT(GPIOB_PIN7) | \
|
||||||
PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \
|
PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \
|
||||||
PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \
|
PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \
|
||||||
|
@ -387,13 +391,13 @@
|
||||||
PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \
|
PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \
|
||||||
PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \
|
PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \
|
||||||
PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP))
|
PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP))
|
||||||
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
|
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_USB_FS_BUSON) |\
|
||||||
PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
|
PIN_OTYPE_PUSHPULL(GPIOB_USB_HS_FAULT) |\
|
||||||
PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \
|
PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \
|
||||||
PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) | \
|
PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) | \
|
||||||
PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) | \
|
PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) | \
|
||||||
PIN_OTYPE_PUSHPULL(GPIOB_USB_HS_FAULT) |\
|
PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
|
||||||
PIN_OTYPE_PUSHPULL(GPIOB_USB_FS_FAULT) |\
|
PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
|
||||||
PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
|
PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
|
||||||
PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \
|
PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \
|
||||||
PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \
|
PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \
|
||||||
|
@ -403,13 +407,13 @@
|
||||||
PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\
|
PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\
|
||||||
PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \
|
PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \
|
||||||
PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP))
|
PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP))
|
||||||
#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \
|
#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_USB_FS_BUSON) | \
|
||||||
PIN_OSPEED_100M(GPIOB_PIN1) | \
|
PIN_OSPEED_100M(GPIOB_USB_HS_FAULT) | \
|
||||||
PIN_OSPEED_100M(GPIOB_BOOT1) | \
|
PIN_OSPEED_100M(GPIOB_BOOT1) | \
|
||||||
PIN_OSPEED_100M(GPIOB_JTAG_TDO) | \
|
PIN_OSPEED_100M(GPIOB_JTAG_TDO) | \
|
||||||
PIN_OSPEED_100M(GPIOB_JTAG_TRST) | \
|
PIN_OSPEED_100M(GPIOB_JTAG_TRST) | \
|
||||||
PIN_OSPEED_100M(GPIOB_USB_HS_FAULT) | \
|
PIN_OSPEED_100M(GPIOB_PIN5) | \
|
||||||
PIN_OSPEED_100M(GPIOB_USB_FS_FAULT) | \
|
PIN_OSPEED_100M(GPIOB_PIN6) | \
|
||||||
PIN_OSPEED_100M(GPIOB_PIN7) | \
|
PIN_OSPEED_100M(GPIOB_PIN7) | \
|
||||||
PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \
|
PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \
|
||||||
PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \
|
PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \
|
||||||
|
@ -419,13 +423,13 @@
|
||||||
PIN_OSPEED_100M(GPIOB_OTG_HS_VBUS) | \
|
PIN_OSPEED_100M(GPIOB_OTG_HS_VBUS) | \
|
||||||
PIN_OSPEED_100M(GPIOB_OTG_HS_DM) | \
|
PIN_OSPEED_100M(GPIOB_OTG_HS_DM) | \
|
||||||
PIN_OSPEED_100M(GPIOB_OTG_HS_DP))
|
PIN_OSPEED_100M(GPIOB_OTG_HS_DP))
|
||||||
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
|
#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_USB_FS_BUSON) |\
|
||||||
PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
|
PIN_PUPDR_FLOATING(GPIOB_USB_HS_FAULT) |\
|
||||||
PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \
|
PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \
|
||||||
PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) | \
|
PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) | \
|
||||||
PIN_PUPDR_FLOATING(GPIOB_JTAG_TRST) | \
|
PIN_PUPDR_FLOATING(GPIOB_JTAG_TRST) | \
|
||||||
PIN_PUPDR_FLOATING(GPIOB_USB_HS_FAULT) |\
|
PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
|
||||||
PIN_PUPDR_FLOATING(GPIOB_USB_FS_FAULT) |\
|
PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
|
||||||
PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
|
PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
|
||||||
PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \
|
PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \
|
||||||
PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \
|
PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \
|
||||||
|
@ -435,13 +439,13 @@
|
||||||
PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\
|
PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\
|
||||||
PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \
|
PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \
|
||||||
PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP))
|
PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP))
|
||||||
#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
|
#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_USB_FS_BUSON) | \
|
||||||
PIN_ODR_HIGH(GPIOB_PIN1) | \
|
PIN_ODR_HIGH(GPIOB_USB_HS_FAULT) | \
|
||||||
PIN_ODR_HIGH(GPIOB_BOOT1) | \
|
PIN_ODR_HIGH(GPIOB_BOOT1) | \
|
||||||
PIN_ODR_HIGH(GPIOB_JTAG_TDO) | \
|
PIN_ODR_HIGH(GPIOB_JTAG_TDO) | \
|
||||||
PIN_ODR_HIGH(GPIOB_JTAG_TRST) | \
|
PIN_ODR_HIGH(GPIOB_JTAG_TRST) | \
|
||||||
PIN_ODR_HIGH(GPIOB_USB_HS_FAULT) | \
|
PIN_ODR_HIGH(GPIOB_PIN5) | \
|
||||||
PIN_ODR_HIGH(GPIOB_USB_FS_FAULT) | \
|
PIN_ODR_HIGH(GPIOB_PIN6) | \
|
||||||
PIN_ODR_HIGH(GPIOB_PIN7) | \
|
PIN_ODR_HIGH(GPIOB_PIN7) | \
|
||||||
PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \
|
PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \
|
||||||
PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \
|
PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \
|
||||||
|
@ -451,13 +455,13 @@
|
||||||
PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) | \
|
PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) | \
|
||||||
PIN_ODR_HIGH(GPIOB_OTG_HS_DM) | \
|
PIN_ODR_HIGH(GPIOB_OTG_HS_DM) | \
|
||||||
PIN_ODR_HIGH(GPIOB_OTG_HS_DP))
|
PIN_ODR_HIGH(GPIOB_OTG_HS_DP))
|
||||||
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \
|
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_USB_FS_BUSON, 0) | \
|
||||||
PIN_AFIO_AF(GPIOB_PIN1, 0) | \
|
PIN_AFIO_AF(GPIOB_USB_HS_FAULT, 0) | \
|
||||||
PIN_AFIO_AF(GPIOB_BOOT1, 0) | \
|
PIN_AFIO_AF(GPIOB_BOOT1, 0) | \
|
||||||
PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) | \
|
PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) | \
|
||||||
PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) | \
|
PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) | \
|
||||||
PIN_AFIO_AF(GPIOB_USB_HS_FAULT, 0) | \
|
PIN_AFIO_AF(GPIOB_PIN5, 0) | \
|
||||||
PIN_AFIO_AF(GPIOB_USB_FS_FAULT, 0) | \
|
PIN_AFIO_AF(GPIOB_PIN6, 0) | \
|
||||||
PIN_AFIO_AF(GPIOB_PIN7, 0))
|
PIN_AFIO_AF(GPIOB_PIN7, 0))
|
||||||
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \
|
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \
|
||||||
PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) | \
|
PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) | \
|
||||||
|
@ -833,7 +837,7 @@
|
||||||
* PF8 - PIN8 (input pullup).
|
* PF8 - PIN8 (input pullup).
|
||||||
* PF9 - PIN9 (input pullup).
|
* PF9 - PIN9 (input pullup).
|
||||||
* PF10 - PIN10 (input pullup).
|
* PF10 - PIN10 (input pullup).
|
||||||
* PF11 - PIN11 (input pullup).
|
* PF11 - USB_FS_FAULT (input floating).
|
||||||
* PF12 - PIN12 (input pullup).
|
* PF12 - PIN12 (input pullup).
|
||||||
* PF13 - PIN13 (input pullup).
|
* PF13 - PIN13 (input pullup).
|
||||||
* PF14 - PIN14 (input pullup).
|
* PF14 - PIN14 (input pullup).
|
||||||
|
@ -850,7 +854,7 @@
|
||||||
PIN_MODE_INPUT(GPIOF_PIN8) | \
|
PIN_MODE_INPUT(GPIOF_PIN8) | \
|
||||||
PIN_MODE_INPUT(GPIOF_PIN9) | \
|
PIN_MODE_INPUT(GPIOF_PIN9) | \
|
||||||
PIN_MODE_INPUT(GPIOF_PIN10) | \
|
PIN_MODE_INPUT(GPIOF_PIN10) | \
|
||||||
PIN_MODE_INPUT(GPIOF_PIN11) | \
|
PIN_MODE_INPUT(GPIOF_USB_FS_FAULT) | \
|
||||||
PIN_MODE_INPUT(GPIOF_PIN12) | \
|
PIN_MODE_INPUT(GPIOF_PIN12) | \
|
||||||
PIN_MODE_INPUT(GPIOF_PIN13) | \
|
PIN_MODE_INPUT(GPIOF_PIN13) | \
|
||||||
PIN_MODE_INPUT(GPIOF_PIN14) | \
|
PIN_MODE_INPUT(GPIOF_PIN14) | \
|
||||||
|
@ -866,7 +870,7 @@
|
||||||
PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
|
PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
|
||||||
PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
|
PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
|
||||||
PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
|
PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
|
||||||
PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
|
PIN_OTYPE_PUSHPULL(GPIOF_USB_FS_FAULT) |\
|
||||||
PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
|
PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
|
||||||
PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
|
PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
|
||||||
PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
|
PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
|
||||||
|
@ -882,7 +886,7 @@
|
||||||
PIN_OSPEED_100M(GPIOF_PIN8) | \
|
PIN_OSPEED_100M(GPIOF_PIN8) | \
|
||||||
PIN_OSPEED_100M(GPIOF_PIN9) | \
|
PIN_OSPEED_100M(GPIOF_PIN9) | \
|
||||||
PIN_OSPEED_100M(GPIOF_PIN10) | \
|
PIN_OSPEED_100M(GPIOF_PIN10) | \
|
||||||
PIN_OSPEED_100M(GPIOF_PIN11) | \
|
PIN_OSPEED_100M(GPIOF_USB_FS_FAULT) | \
|
||||||
PIN_OSPEED_100M(GPIOF_PIN12) | \
|
PIN_OSPEED_100M(GPIOF_PIN12) | \
|
||||||
PIN_OSPEED_100M(GPIOF_PIN13) | \
|
PIN_OSPEED_100M(GPIOF_PIN13) | \
|
||||||
PIN_OSPEED_100M(GPIOF_PIN14) | \
|
PIN_OSPEED_100M(GPIOF_PIN14) | \
|
||||||
|
@ -898,7 +902,7 @@
|
||||||
PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
|
PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
|
||||||
PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
|
PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
|
||||||
PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
|
PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
|
||||||
PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
|
PIN_PUPDR_FLOATING(GPIOF_USB_FS_FAULT) |\
|
||||||
PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
|
PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
|
||||||
PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
|
PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
|
||||||
PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
|
PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
|
||||||
|
@ -914,7 +918,7 @@
|
||||||
PIN_ODR_HIGH(GPIOF_PIN8) | \
|
PIN_ODR_HIGH(GPIOF_PIN8) | \
|
||||||
PIN_ODR_HIGH(GPIOF_PIN9) | \
|
PIN_ODR_HIGH(GPIOF_PIN9) | \
|
||||||
PIN_ODR_HIGH(GPIOF_PIN10) | \
|
PIN_ODR_HIGH(GPIOF_PIN10) | \
|
||||||
PIN_ODR_HIGH(GPIOF_PIN11) | \
|
PIN_ODR_HIGH(GPIOF_USB_FS_FAULT) | \
|
||||||
PIN_ODR_HIGH(GPIOF_PIN12) | \
|
PIN_ODR_HIGH(GPIOF_PIN12) | \
|
||||||
PIN_ODR_HIGH(GPIOF_PIN13) | \
|
PIN_ODR_HIGH(GPIOF_PIN13) | \
|
||||||
PIN_ODR_HIGH(GPIOF_PIN14) | \
|
PIN_ODR_HIGH(GPIOF_PIN14) | \
|
||||||
|
@ -930,7 +934,7 @@
|
||||||
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
|
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
|
||||||
PIN_AFIO_AF(GPIOF_PIN9, 0) | \
|
PIN_AFIO_AF(GPIOF_PIN9, 0) | \
|
||||||
PIN_AFIO_AF(GPIOF_PIN10, 0) | \
|
PIN_AFIO_AF(GPIOF_PIN10, 0) | \
|
||||||
PIN_AFIO_AF(GPIOF_PIN11, 0) | \
|
PIN_AFIO_AF(GPIOF_USB_FS_FAULT, 0) | \
|
||||||
PIN_AFIO_AF(GPIOF_PIN12, 0) | \
|
PIN_AFIO_AF(GPIOF_PIN12, 0) | \
|
||||||
PIN_AFIO_AF(GPIOF_PIN13, 0) | \
|
PIN_AFIO_AF(GPIOF_PIN13, 0) | \
|
||||||
PIN_AFIO_AF(GPIOF_PIN14, 0) | \
|
PIN_AFIO_AF(GPIOF_PIN14, 0) | \
|
||||||
|
|
|
@ -22,6 +22,7 @@
|
||||||
<identifier>MII_KS8721_ID</identifier>
|
<identifier>MII_KS8721_ID</identifier>
|
||||||
<bus_type>RMII</bus_type>
|
<bus_type>RMII</bus_type>
|
||||||
</ethernet_phy>
|
</ethernet_phy>
|
||||||
|
<subtype>STM32F40_41xxx</subtype>
|
||||||
<clocks HSEFrequency="12000000" HSEBypass="false" LSEFrequency="32768"
|
<clocks HSEFrequency="12000000" HSEBypass="false" LSEFrequency="32768"
|
||||||
VDD="330" />
|
VDD="330" />
|
||||||
<ports>
|
<ports>
|
||||||
|
|
|
@ -49,9 +49,9 @@
|
||||||
#define STM32_VDD 330
|
#define STM32_VDD 330
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MCU type as defined in the ST header file stm32f4xx.h.
|
* MCU type as defined in the ST header.
|
||||||
*/
|
*/
|
||||||
#define STM32F4XX
|
#define STM32F40_41xxx
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* IO pins assignments.
|
* IO pins assignments.
|
||||||
|
|
|
@ -1,17 +1,21 @@
|
||||||
/*
|
/*
|
||||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||||
|
2011,2012,2013 Giovanni Di Sirio.
|
||||||
|
|
||||||
Licensed under the Apache License, Version 2.0 (the "License");
|
This file is part of ChibiOS/RT.
|
||||||
you may not use this file except in compliance with the License.
|
|
||||||
You may obtain a copy of the License at
|
|
||||||
|
|
||||||
http://www.apache.org/licenses/LICENSE-2.0
|
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
Unless required by applicable law or agreed to in writing, software
|
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||||
distributed under the License is distributed on an "AS IS" BASIS,
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
See the License for the specific language governing permissions and
|
GNU General Public License for more details.
|
||||||
limitations under the License.
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "ch.h"
|
#include "ch.h"
|
||||||
|
|
|
@ -1,17 +1,21 @@
|
||||||
/*
|
/*
|
||||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||||
|
2011,2012,2013 Giovanni Di Sirio.
|
||||||
|
|
||||||
Licensed under the Apache License, Version 2.0 (the "License");
|
This file is part of ChibiOS/RT.
|
||||||
you may not use this file except in compliance with the License.
|
|
||||||
You may obtain a copy of the License at
|
|
||||||
|
|
||||||
http://www.apache.org/licenses/LICENSE-2.0
|
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
Unless required by applicable law or agreed to in writing, software
|
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||||
distributed under the License is distributed on an "AS IS" BASIS,
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
See the License for the specific language governing permissions and
|
GNU General Public License for more details.
|
||||||
limitations under the License.
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef _BOARD_H_
|
#ifndef _BOARD_H_
|
||||||
|
@ -48,9 +52,9 @@
|
||||||
#define STM32_VDD 300
|
#define STM32_VDD 300
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MCU type as defined in the ST header file stm32f4xx.h.
|
* MCU type as defined in the ST header.
|
||||||
*/
|
*/
|
||||||
#define STM32F4XX
|
#define STM32F40_41xxx
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* IO pins assignments.
|
* IO pins assignments.
|
||||||
|
|
|
@ -10,6 +10,7 @@
|
||||||
<board_name>STMicroelectronics STM32F4-Discovery</board_name>
|
<board_name>STMicroelectronics STM32F4-Discovery</board_name>
|
||||||
<board_id>ST_STM32F4_DISCOVERY</board_id>
|
<board_id>ST_STM32F4_DISCOVERY</board_id>
|
||||||
<board_functions></board_functions>
|
<board_functions></board_functions>
|
||||||
|
<subtype>STM32F40_41xxx</subtype>
|
||||||
<clocks HSEFrequency="8000000" HSEBypass="false" LSEFrequency="0" VDD="300" />
|
<clocks HSEFrequency="8000000" HSEBypass="false" LSEFrequency="0" VDD="300" />
|
||||||
<ports>
|
<ports>
|
||||||
<GPIOA>
|
<GPIOA>
|
||||||
|
|
|
@ -57,7 +57,7 @@
|
||||||
#define STM32_I2SSRC STM32_I2SSRC_CKIN
|
#define STM32_I2SSRC STM32_I2SSRC_CKIN
|
||||||
#define STM32_PLLI2SN_VALUE 192
|
#define STM32_PLLI2SN_VALUE 192
|
||||||
#define STM32_PLLI2SR_VALUE 5
|
#define STM32_PLLI2SR_VALUE 5
|
||||||
#define STM32_VOS STM32_VOS_HIGH
|
#define STM32_VOS STM32_VOS_SCALE1
|
||||||
#define STM32_PVD_ENABLE FALSE
|
#define STM32_PVD_ENABLE FALSE
|
||||||
#define STM32_PLS STM32_PLS_LEV0
|
#define STM32_PLS STM32_PLS_LEV0
|
||||||
#define STM32_BKPRAM_ENABLE FALSE
|
#define STM32_BKPRAM_ENABLE FALSE
|
||||||
|
|
|
@ -61,7 +61,8 @@
|
||||||
#elif defined(STM32F37X)
|
#elif defined(STM32F37X)
|
||||||
#include "stm32f37x.h"
|
#include "stm32f37x.h"
|
||||||
|
|
||||||
#elif defined(STM32F4XX)
|
#elif defined(STM32F401xx) || defined(STM32F40_41xxx) || \
|
||||||
|
defined(STM32F427_437xx) || defined(STM32F429_439xx)
|
||||||
#include "stm32f4xx.h"
|
#include "stm32f4xx.h"
|
||||||
|
|
||||||
#elif defined(STM32L1XX_MD)
|
#elif defined(STM32L1XX_MD)
|
||||||
|
|
|
@ -153,7 +153,7 @@ void stm32_clock_init(void) {
|
||||||
|
|
||||||
/* PWR initialization.*/
|
/* PWR initialization.*/
|
||||||
#if defined(STM32F4XX) || defined(__DOXYGEN__)
|
#if defined(STM32F4XX) || defined(__DOXYGEN__)
|
||||||
PWR->CR = STM32_VOS;
|
PWR->CR = STM32_VOS & STM32_VOS_MASK;
|
||||||
while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
|
while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
|
||||||
; /* Waits until power regulator is stable. */
|
; /* Waits until power regulator is stable. */
|
||||||
#else
|
#else
|
||||||
|
|
|
@ -20,13 +20,18 @@
|
||||||
* @pre This module requires the following macros to be defined in the
|
* @pre This module requires the following macros to be defined in the
|
||||||
* @p board.h file:
|
* @p board.h file:
|
||||||
* - STM32_LSECLK.
|
* - STM32_LSECLK.
|
||||||
|
* - STM32_LSEDRV.
|
||||||
|
* - STM32_LSE_BYPASS (optionally).
|
||||||
* - STM32_HSECLK.
|
* - STM32_HSECLK.
|
||||||
* - STM32_HSE_BYPASS (optionally).
|
* - STM32_HSE_BYPASS (optionally).
|
||||||
* - STM32_VDD (as hundredths of Volt).
|
* - STM32_VDD (as hundredths of Volt).
|
||||||
* .
|
* .
|
||||||
* One of the following macros must also be defined:
|
* One of the following macros must also be defined:
|
||||||
* - STM32F2XX for High-performance STM32 F-2 devices.
|
* - STM32F2XX for High-performance STM32 F-2 devices.
|
||||||
* - STM32F4XX for High-performance STM32 F-4 devices.
|
* - STM32F401xx for High-performance STM32 F-4 devices.
|
||||||
|
* - STM32F40_41xxx for High-performance STM32 F-4 devices.
|
||||||
|
* - STM32F427_437xx for High-performance STM32 F-4 devices.
|
||||||
|
* - STM32F429_439xx for High-performance STM32 F-4 devices.
|
||||||
* .
|
* .
|
||||||
*
|
*
|
||||||
* @addtogroup HAL
|
* @addtogroup HAL
|
||||||
|
@ -51,32 +56,60 @@
|
||||||
* @name Platform identification
|
* @name Platform identification
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#if defined(STM32F4XX) || defined(__DOXYGEN__)
|
#if defined(STM32F429_439xx) || defined(__DOXYGEN__)
|
||||||
#define PLATFORM_NAME "STM32F4xx High Performance"
|
#define PLATFORM_NAME "STM32F429/F439 High Performance with DSP and FPU"
|
||||||
#else /* !defined(STM32F4XX) */
|
#elif defined(STM32F427_437xx) || defined(__DOXYGEN__)
|
||||||
|
#define PLATFORM_NAME "STM32F427/F437 High Performance with DSP and FPU"
|
||||||
|
#elif defined(STM32F40_41xxx) || defined(__DOXYGEN__)
|
||||||
|
#define PLATFORM_NAME "STM32F407/F417 High Performance with DSP and FPU"
|
||||||
|
#elif defined(STM32F401) || defined(__DOXYGEN__)
|
||||||
|
#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU"
|
||||||
|
#elif defined(STM32F2XX) || defined(__DOXYGEN__)
|
||||||
#define PLATFORM_NAME "STM32F2xx High Performance"
|
#define PLATFORM_NAME "STM32F2xx High Performance"
|
||||||
#endif /* !defined(STM32F4XX) */
|
#else
|
||||||
|
#error "STM32F2xx/F4xx device not specified"
|
||||||
|
#endif
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @name Absolute Maximum Ratings
|
* @name Absolute Maximum Ratings
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#if defined(STM32F4XX) || defined(__DOXYGEN__)
|
/**
|
||||||
|
* @name Absolute Maximum Ratings
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined(STM32F429_439xx) || defined(STM32F429_439xx) || \
|
||||||
|
defined(__DOXYGEN__)
|
||||||
/**
|
/**
|
||||||
* @brief Maximum HSE clock frequency.
|
* @brief Maximum HSE clock frequency.
|
||||||
*/
|
*/
|
||||||
#define STM32_HSECLK_MAX 26000000
|
#define STM32_HSECLK_MAX 26000000
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Maximum HSE clock frequency using an external source.
|
||||||
|
*/
|
||||||
|
#define STM32_HSECLK_BYP_MAX 50000000
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Minimum HSE clock frequency.
|
* @brief Minimum HSE clock frequency.
|
||||||
*/
|
*/
|
||||||
#define STM32_HSECLK_MIN 1000000
|
#define STM32_HSECLK_MIN 4000000
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Minimum HSE clock frequency.
|
||||||
|
*/
|
||||||
|
#define STM32_HSECLK_BYP_MIN 1000000
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Maximum LSE clock frequency.
|
* @brief Maximum LSE clock frequency.
|
||||||
*/
|
*/
|
||||||
#define STM32_LSECLK_MAX 1000000
|
#define STM32_LSECLK_MAX 32768
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Maximum LSE clock frequency.
|
||||||
|
*/
|
||||||
|
#define STM32_LSECLK_BYP_MAX 1000000
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Minimum LSE clock frequency.
|
* @brief Minimum LSE clock frequency.
|
||||||
|
@ -86,7 +119,7 @@
|
||||||
/**
|
/**
|
||||||
* @brief Maximum PLLs input clock frequency.
|
* @brief Maximum PLLs input clock frequency.
|
||||||
*/
|
*/
|
||||||
#define STM32_PLLIN_MAX 2000000
|
#define STM32_PLLIN_MAX 2100000
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Minimum PLLs input clock frequency.
|
* @brief Minimum PLLs input clock frequency.
|
||||||
|
@ -106,7 +139,7 @@
|
||||||
/**
|
/**
|
||||||
* @brief Maximum PLL output clock frequency.
|
* @brief Maximum PLL output clock frequency.
|
||||||
*/
|
*/
|
||||||
#define STM32_PLLOUT_MAX 168000000
|
#define STM32_PLLOUT_MAX 180000000
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Minimum PLL output clock frequency.
|
* @brief Minimum PLL output clock frequency.
|
||||||
|
@ -116,23 +149,65 @@
|
||||||
/**
|
/**
|
||||||
* @brief Maximum APB1 clock frequency.
|
* @brief Maximum APB1 clock frequency.
|
||||||
*/
|
*/
|
||||||
#define STM32_PCLK1_MAX 42000000
|
#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX /4)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Maximum APB2 clock frequency.
|
* @brief Maximum APB2 clock frequency.
|
||||||
*/
|
*/
|
||||||
#define STM32_PCLK2_MAX 84000000
|
#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Maximum SPI/I2S clock frequency.
|
* @brief Maximum SPI/I2S clock frequency.
|
||||||
*/
|
*/
|
||||||
#define STM32_SPII2S_MAX 37500000
|
#define STM32_SPII2S_MAX 37500000
|
||||||
|
#endif /* STM32F40_41xxx */
|
||||||
|
|
||||||
#else /* !defined(STM32F4XX) */
|
#if defined(STM32F40_41xxx) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_HSECLK_MAX 26000000
|
||||||
|
#define STM32_HSECLK_BYP_MAX 50000000
|
||||||
|
#define STM32_HSECLK_MIN 4000000
|
||||||
|
#define STM32_HSECLK_BYP_MIN 1000000
|
||||||
|
#define STM32_LSECLK_MAX 32768
|
||||||
|
#define STM32_LSECLK_BYP_MAX 1000000
|
||||||
|
#define STM32_LSECLK_MIN 32768
|
||||||
|
#define STM32_PLLIN_MAX 2100000
|
||||||
|
#define STM32_PLLIN_MIN 950000
|
||||||
|
#define STM32_PLLVCO_MAX 432000000
|
||||||
|
#define STM32_PLLVCO_MIN 192000000
|
||||||
|
#define STM32_PLLOUT_MAX 168000000
|
||||||
|
#define STM32_PLLOUT_MIN 24000000
|
||||||
|
#define STM32_PCLK1_MAX 42000000
|
||||||
|
#define STM32_PCLK2_MAX 84000000
|
||||||
|
#define STM32_SPII2S_MAX 37500000
|
||||||
|
#endif /* STM32F40_41xxx */
|
||||||
|
|
||||||
|
#if defined(STM32F401) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_HSECLK_MAX 26000000
|
||||||
|
#define STM32_HSECLK_BYP_MAX 50000000
|
||||||
|
#define STM32_HSECLK_MIN 4000000
|
||||||
|
#define STM32_HSECLK_BYP_MIN 1000000
|
||||||
|
#define STM32_LSECLK_MAX 32768
|
||||||
|
#define STM32_LSECLK_BYP_MAX 1000000
|
||||||
|
#define STM32_LSECLK_MIN 32768
|
||||||
|
#define STM32_PLLIN_MAX 2100000
|
||||||
|
#define STM32_PLLIN_MIN 950000
|
||||||
|
#define STM32_PLLVCO_MAX 432000000
|
||||||
|
#define STM32_PLLVCO_MIN 192000000
|
||||||
|
#define STM32_PLLOUT_MAX 168000000
|
||||||
|
#define STM32_PLLOUT_MIN 24000000
|
||||||
|
#define STM32_PCLK1_MAX 42000000
|
||||||
|
#define STM32_PCLK2_MAX 84000000
|
||||||
|
#define STM32_SPII2S_MAX 37500000
|
||||||
|
#endif /* STM32F40_41xxx */
|
||||||
|
|
||||||
|
#if defined(STM32F2XX)
|
||||||
#define STM32_SYSCLK_MAX 120000000
|
#define STM32_SYSCLK_MAX 120000000
|
||||||
#define STM32_HSECLK_MAX 26000000
|
#define STM32_HSECLK_MAX 26000000
|
||||||
|
#define STM32_HSECLK_BYP_MAX 26000000
|
||||||
#define STM32_HSECLK_MIN 1000000
|
#define STM32_HSECLK_MIN 1000000
|
||||||
#define STM32_LSECLK_MAX 1000000
|
#define STM32_HSECLK_BYP_MIN 1000000
|
||||||
|
#define STM32_LSECLK_MAX 32768
|
||||||
|
#define STM32_LSECLK_BYP_MAX 1000000
|
||||||
#define STM32_LSECLK_MIN 32768
|
#define STM32_LSECLK_MIN 32768
|
||||||
#define STM32_PLLIN_MAX 2000000
|
#define STM32_PLLIN_MAX 2000000
|
||||||
#define STM32_PLLIN_MIN 950000
|
#define STM32_PLLIN_MIN 950000
|
||||||
|
@ -143,7 +218,7 @@
|
||||||
#define STM32_PCLK1_MAX 30000000
|
#define STM32_PCLK1_MAX 30000000
|
||||||
#define STM32_PCLK2_MAX 60000000
|
#define STM32_PCLK2_MAX 60000000
|
||||||
#define STM32_SPII2S_MAX 37500000
|
#define STM32_SPII2S_MAX 37500000
|
||||||
#endif /* !defined(STM32F4XX) */
|
#endif /* defined(STM32F2XX) */
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -163,6 +238,19 @@
|
||||||
#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */
|
#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */
|
||||||
#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */
|
#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
|
||||||
|
defined(STM32F401) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_VOS_MASK (3 << 14) /**< Scale Mode mask. */
|
||||||
|
#elif defined(STM32F40_41xxx) || defined(__DOXYGEN__)
|
||||||
|
#define STM32_VOS_MASK (1 << 14) /**< Scale Mode mask. */
|
||||||
|
#else
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define STM32_VOS_SCALE3 (1 << 14) /**< Scale 3 mode. */
|
||||||
|
#define STM32_VOS_SCALE2 (2 << 14) /**< Scale 2 mode. */
|
||||||
|
#define STM32_VOS_SCALE1 (3 << 14) /**< Scale 2 mode. */
|
||||||
|
|
||||||
#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
|
#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
|
||||||
#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
|
#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
|
||||||
#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
|
#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
|
||||||
|
@ -859,6 +947,14 @@
|
||||||
/* Derived constants and error checks. */
|
/* Derived constants and error checks. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Generic STM32F4XX identifier for backward compatibility.
|
||||||
|
*/
|
||||||
|
#if defined(STM32F401xx) || defined(STM32F40_41xxx) || \
|
||||||
|
defined(STM32F427_437xx) || defined(STM32F429_439xx)
|
||||||
|
#define STM32F4XX
|
||||||
|
#endif
|
||||||
|
|
||||||
#if defined(STM32F4XX) || defined(__DOXYGEN__)
|
#if defined(STM32F4XX) || defined(__DOXYGEN__)
|
||||||
/*
|
/*
|
||||||
* Configuration-related checks.
|
* Configuration-related checks.
|
||||||
|
@ -871,7 +967,7 @@
|
||||||
* @brief Maximum SYSCLK.
|
* @brief Maximum SYSCLK.
|
||||||
* @note It is a function of the core voltage setting.
|
* @note It is a function of the core voltage setting.
|
||||||
*/
|
*/
|
||||||
#if (STM32_VOS == STM32_VOS_HIGH) || defined(__DOXYGEN__)
|
#if (STM32_VOS == STM32_VOS_SCALE1) || defined(__DOXYGEN__)
|
||||||
#define STM32_SYSCLK_MAX 168000000
|
#define STM32_SYSCLK_MAX 168000000
|
||||||
#else
|
#else
|
||||||
#define STM32_SYSCLK_MAX 144000000
|
#define STM32_SYSCLK_MAX 144000000
|
||||||
|
|
File diff suppressed because it is too large
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Reference in New Issue