Improved RCC related bit-masks in STM32F4xx hal_lld.h
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9532 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi
parent
bca1476912
commit
5e34b6470a
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@ -428,10 +428,24 @@
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* @name RCC_PLLI2SCFGR register bits definitions
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* @{
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*/
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#define STM32_PLLI2SM_MASK (31 << 0) /**< PLLI2SM mask. */
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#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */
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#define STM32_PLLI2SP_MASK (3 << 16) /**< PLLI2SP mask. */
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#define STM32_PLLI2SQ_MASK (15 << 24) /**< PLLI2SQ mask. */
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#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
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/** @} */
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/**
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* @name RCC_PLLSAICFGR register bits definitions
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* @{
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*/
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#define STM32_PLLSAIM_MASK (31 << 0) /**< PLLSAIM mask. */
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#define STM32_PLLSAIN_MASK (511 << 6) /**< PLLSAIN mask. */
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#define STM32_PLLSAIP_MASK (3 << 16) /**< PLLSAIP mask. */
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#define STM32_PLLSAIQ_MASK (15 << 24) /**< PLLSAIQ mask. */
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#define STM32_PLLSAIR_MASK (7 << 28) /**< PLLSAIR mask. */
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/** @} */
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/**
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* @name RCC_BDCR register bits definitions
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* @{
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@ -443,6 +457,80 @@
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#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
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/** @} */
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/**
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* @name RCC_DCKCFGR register bits definitions
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* @{
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*/
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#define STM32_PLLI2SDIVQ_MASK (31 << 0) /**< PLLSAIDIVQ mask. */
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#define STM32_PLLSAIDIVQ_MASK (31 << 8) /**< PLLSAIDIVQ mask. */
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#define STM32_PLLSAIDIVR_MASK (3 << 16) /**< PLLSAIDIVR mask. */
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#define STM32_PLLSAIDIVR_DIV2 (0 << 16) /**< LCD_CLK is R divided by 2. */
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#define STM32_PLLSAIDIVR_DIV4 (1 << 16) /**< LCD_CLK is R divided by 4. */
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#define STM32_PLLSAIDIVR_DIV8 (2 << 16) /**< LCD_CLK is R divided by 8. */
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#define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/
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#define STM32_PLLSAIDIVR_OFF 0xFFFFFFFFU /**< LCD CLK is not required. */
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#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */
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#define STM32_SAI1SEL_SAIPLL (0 << 20) /**< SAI1 source is SAIPLL. */
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#define STM32_SAI1SEL_I2SPLL (1 << 20) /**< SAI1 source is I2SPLL. */
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#define STM32_SAI1SEL_PLLR (2 << 20) /**< SAI1 source is PLLR. */
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#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
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#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */
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#define STM32_SAI2SEL_SAIPLL (0 << 22) /**< SAI2 source is SAIPLL. */
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#define STM32_SAI2SEL_I2SPLL (1 << 22) /**< SAI2 source is I2SPLL. */
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#define STM32_SAI2SEL_PLLR (2 << 22) /**< SAI2 source is PLLR. */
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#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
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#define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */
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#define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */
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#define STM32_TIMPRE_HCLK (1 << 24) /**< TIM clocks from HCLK. */
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#define STM32_I2S1SEL_MASK (3 << 25) /**< I2S1SEL mask. */
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#define STM32_I2S1SEL_PLLR (0 << 25) /**< I2S1 source is PLLR. */
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#define STM32_I2S1SEL_AFIN (1 << 25) /**< I2S1 source is AF Input. */
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#define STM32_I2S1SEL_MCO1 (2 << 25) /**< I2S1 source is MCO1. */
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#define STM32_I2S1SEL_OFF 0xFFFFFFFFU /**< I2S1 clock is not required.*/
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#define STM32_I2S2SEL_MASK (3 << 27) /**< I2S2SEL mask. */
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#define STM32_I2S2SEL_PLLR (0 << 27) /**< I2S2 source is PLLR. */
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#define STM32_I2S2SEL_AFIN (1 << 27) /**< I2S2 source is AF Input. */
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#define STM32_I2S2SEL_MCO1 (2 << 27) /**< I2S2 source is MCO1. */
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#define STM32_I2S2SEL_OFF 0xFFFFFFFFU /**< I2S2 clock is not required.*/
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#define STM32_DSISEL_MASK (1 << 28) /**< DSISEL mask. */
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#define STM32_DSISEL_PHY (0 << 28) /**< DSI source is DSI-PSY. */
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#define STM32_DSISEL_PLLR (1 << 28) /**< DSI source is PLLR. */
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/** @} */
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/**
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* @name RCC_DCKCFGR2 register bits definitions
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* @{
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*/
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#define STM32_I2C1SEL_MASK (3 << 22) /**< I2C1SEL mask. */
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#define STM32_I2C1SEL_PCLK1 (0 << 22) /**< I2C1 source is PCLK1. */
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#define STM32_I2C1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */
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#define STM32_I2C1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */
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#define STM32_CECSEL_MASK (1 << 26) /**< CECSEL mask. */
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#define STM32_CECSEL_LSE (0 << 26) /**< CEC source is LSE. */
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#define STM32_CECSEL_HSIDIV488 (1 << 26) /**< CEC source is HSI/488. */
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#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
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#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
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#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */
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#define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */
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#define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */
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#define STM32_SDMMCSEL_SYSCLK (1 << 28) /**< SDMMC source is SYSCLK. */
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#define STM32_SPDIFSEL_MASK (1 << 29) /**< SPDIFSEL mask. */
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#define STM32_SPDIFSEL_PLLI2S (0 << 29) /**< SPDIF source is PLLI2S. */
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#define STM32_SPDIFSEL_PLL (1 << 29) /**< SPDIF source is PLL. */
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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