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Fixed Bug #746 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9531 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi 2016-05-26 11:08:54 +00:00
parent e9e97281a1
commit bca1476912
3 changed files with 31 additions and 29 deletions
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16
os/hal/ports/STM32/STM32F4xx/hal_lld.h
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@ -666,32 +666,32 @@
#endif
/**
* @brief MC01 clock source value.
* @note The default value outputs HSI clock on MC01 pin.
* @brief MCO1 clock source value.
* @note The default value outputs HSI clock on MCO1 pin.
*/
#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#endif
/**
* @brief MC01 prescaler value.
* @note The default value outputs HSI clock on MC01 pin.
* @brief MCO1 prescaler value.
* @note The default value outputs HSI clock on MCO1 pin.
*/
#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#endif
/**
* @brief MC02 clock source value.
* @note The default value outputs SYSCLK / 5 on MC02 pin.
* @brief MCO2 clock source value.
* @note The default value outputs SYSCLK / 5 on MCO2 pin.
*/
#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#endif
/**
* @brief MC02 prescaler value.
* @note The default value outputs SYSCLK / 5 on MC02 pin.
* @brief MCO2 prescaler value.
* @note The default value outputs SYSCLK / 5 on MCO2 pin.
*/
#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5

42
os/hal/ports/STM32/STM32F7xx/hal_lld.h
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@ -194,11 +194,11 @@
* @name RCC_PLLCFGR register bits definitions
* @{
*/
#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */
#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */
#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */
#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */
#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */
#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */
#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */
#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */
#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */
#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */
#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */
#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */
@ -224,14 +224,14 @@
#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */
#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */
#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */
#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */
#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */
#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */
#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */
#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */
#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */
#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */
#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */
#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */
@ -264,11 +264,11 @@
#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */
#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */
#define STM32_MCO2SEL_MASK (3U << 30) /**< MCO2 mask. */
#define STM32_MCO2SEL_SYSCLK (0U << 30) /**< SYSCLK clock on MCO2 pin. */
#define STM32_MCO2SEL_PLLI2S (1U << 30) /**< PLLI2S clock on MCO2 pin. */
#define STM32_MCO2SEL_HSE (2U << 30) /**< HSE clock on MCO2 pin. */
#define STM32_MCO2SEL_PLL (3U << 30) /**< PLL clock on MCO2 pin. */
#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */
#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */
#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */
#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */
#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */
/**
* @name RCC_PLLI2SCFGR register bits definitions
@ -582,32 +582,32 @@
#endif
/**
* @brief MC01 clock source value.
* @note The default value outputs HSI clock on MC01 pin.
* @brief MCO1 clock source value.
* @note The default value outputs HSI clock on MCO1 pin.
*/
#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#endif
/**
* @brief MC01 prescaler value.
* @note The default value outputs HSI clock on MC01 pin.
* @brief MCO1 prescaler value.
* @note The default value outputs HSI clock on MCO1 pin.
*/
#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#endif
/**
* @brief MC02 clock source value.
* @note The default value outputs SYSCLK / 4 on MC02 pin.
* @brief MCO2 clock source value.
* @note The default value outputs SYSCLK / 4 on MCO2 pin.
*/
#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#endif
/**
* @brief MC02 prescaler value.
* @note The default value outputs SYSCLK / 4 on MC02 pin.
* @brief MCO2 prescaler value.
* @note The default value outputs SYSCLK / 4 on MCO2 pin.
*/
#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
@ -944,7 +944,7 @@
#if STM32_HSE_ENABLED
#if STM32_HSECLK == 0
#error "HSE frequency not defined"
#error "HSE frequency not defined"
#else /* STM32_HSECLK != 0 */
#if defined(STM32_HSE_BYPASS)
#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)

2
readme.txt
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@ -113,6 +113,8 @@
- RT: Merged RT4.
- NIL: Merged NIL2.
- NIL: Added STM32F7 demo.
- HAL: Fixed wrong comments and indent in STM32F4xx and STM32F7xx
hal_lld.h (bug #746).
- HAL: Removed wrong SAI masks in STM32F4xx hal_lld.h (bug #745).
- HAL: Fixed wrong mask placement in STM32F4xx hal_lld.h (bug #744).
- HAL: Fixed wrong indent in STM32F4xx hal_lld.h (bug #743).