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[AVR] Fix code style in AVR low level driver. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15927 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Theodore Ateba 2022-12-27 00:54:14 +00:00
parent 0b1d16e646
commit 6a0b2f377e
33 changed files with 166 additions and 196 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
os/hal/ports/AVR/MEGA/LLD/ADCv1/hal_adc_lld.c
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@ -68,7 +68,7 @@ static size_t getAdcChannelNumberFromMask(uint8_t mask,
mask >>= 1; mask >>= 1;
} }
/* error, should never reach this line */ /* Error, should never reach this line */
return -1; return -1;
} }
@ -132,7 +132,7 @@ void adc_lld_init(void) {
/* Prescaler 128, only value possible at 20Mhz, interrupt. */ /* Prescaler 128, only value possible at 20Mhz, interrupt. */
ADCSRA = (1 << ADPS2) | (1 << ADPS1) | (1 << ADPS0) | (1 << ADIE); ADCSRA = (1 << ADPS2) | (1 << ADPS1) | (1 << ADPS0) | (1 << ADIE);
/* uso aref, only valid for arduino. arduino ha aref collegato. */ /* Uso aref, only valid for arduino. arduino ha aref collegato. */
ADMUX = (0 << REFS1) | (0 << REFS0); ADMUX = (0 << REFS1) | (0 << REFS0);
} }

2
os/hal/ports/AVR/MEGA/LLD/GPIOv1/hal_pal_lld.h
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@ -276,7 +276,7 @@ typedef uint8_t ioeventmode_t;
/*==========================================================================*/ /*==========================================================================*/
/* Implementation, some of the following macros could be implemented as */ /* Implementation, some of the following macros could be implemented as */
/* functions, if so please put them in hal_pal_lld.c. */ /* Functions, if so please put them in hal_pal_lld.c. */
/*==========================================================================*/ /*==========================================================================*/
/** /**

1
os/hal/ports/AVR/MEGA/LLD/SPIv1/hal_spi_lld.c
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@ -206,7 +206,6 @@ void spi_lld_unselect(SPIDriver *spip) {
} }
/** /**
* @brief Exchanges data on the SPI bus. * @brief Exchanges data on the SPI bus.
* @details This asynchronous function starts a simultaneous transmit/receive * @details This asynchronous function starts a simultaneous transmit/receive

1
os/hal/ports/AVR/MEGA/LLD/SPIv1/hal_spi_lld.h
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@ -112,7 +112,6 @@
size_t exbytes; \ size_t exbytes; \
size_t exidx; size_t exidx;
/** /**
* @brief Low level fields of the SPI configuration structure. * @brief Low level fields of the SPI configuration structure.
*/ */

2
os/hal/ports/AVR/MEGA/LLD/SYSTICKv1/hal_st_lld.c
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@ -193,7 +193,7 @@ void st_lld_init(void) {
TCCR1A = 0; TCCR1A = 0;
TCCR1B = _BV(WGM12); TCCR1B = _BV(WGM12);
/* start disabled. */ /* Start disabled. */
TCCR1C = 0; TCCR1C = 0;
OCR1A = 0; OCR1A = 0;
TCNT1 = 0; TCNT1 = 0;

11
os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_gpt_lld.c
View File

@ -94,8 +94,11 @@ GPTDriver GPTD5;
static uint16_t ratio_base[] = { 1024, 256, 64, 8, 1 }; static uint16_t ratio_base[] = { 1024, 256, 64, 8, 1 };
static uint8_t clock_source_base[] = { 5, 4, 3, 2, 1 }; static uint8_t clock_source_base[] = { 5, 4, 3, 2, 1 };
//static uint16_t ratio_extended[] = { 1024, 256, 128, 64, 32, 8, 1 };
//static uint8_t clock_source_extended[] = { 7, 6, 5, 4, 3, 2, 1 }; /* Extended tables.
* static uint16_t ratio_extended[] = { 1024, 256, 128, 64, 32, 8, 1 };
* static uint8_t clock_source_extended[] = { 7, 6, 5, 4, 3, 2, 1 };
*/
/*==========================================================================*/ /*==========================================================================*/
/* Driver local functions. */ /* Driver local functions. */
@ -334,7 +337,7 @@ void gpt_lld_start(GPTDriver *gptp) {
*/ */
void gpt_lld_stop(GPTDriver *gptp) { void gpt_lld_stop(GPTDriver *gptp) {
/* nothing to be done */ /* Nothing to be done */
if (gptp->state == GPT_READY) { if (gptp->state == GPT_READY) {
/* Clock de-activation.*/ /* Clock de-activation.*/
} }
@ -393,7 +396,7 @@ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
gptp->callback = gpt_lld_dummy_callback; gptp->callback = gpt_lld_dummy_callback;
gpt_lld_start_timer(gptp, interval); gpt_lld_start_timer(gptp, interval);
//FIX /* FIX */
while (gptp->state != GPT_READY) {} while (gptp->state != GPT_READY) {}
} }

1
os/hal/ports/AVR/MEGA/LLD/TIMv1/hal_icu_lld.h
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@ -157,7 +157,6 @@ struct ICUDriver {
/* Driver macros. */ /* Driver macros. */
/*==========================================================================*/ /*==========================================================================*/
/** /**
* @brief Returns the width of the latest pulse. * @brief Returns the width of the latest pulse.
* @details The pulse width is defined as number of ticks between the start * @details The pulse width is defined as number of ticks between the start

4
os/hal/ports/AVR/MEGA/LLD/USBv1/hal_usb_lld.c
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@ -249,7 +249,7 @@ static void usb_fifo_write(USBDriver *usbp, usbep_t ep, size_t n) {
if (n > epcp->in_maxsize) if (n > epcp->in_maxsize)
n = epcp->in_maxsize; n = epcp->in_maxsize;
/* i is number of bytes remaining to transmit minus 1 (to handle 256b case). */ /* I is number of bytes remaining to transmit minus 1 (to handle 256b case). */
uint8_t i = n - 1; uint8_t i = n - 1;
/* Must lock for entire operation to ensure nothing changes the ENUM value. */ /* Must lock for entire operation to ensure nothing changes the ENUM value. */
@ -271,7 +271,7 @@ static void usb_fifo_read(USBDriver *usbp, usbep_t ep, size_t n) {
return; return;
if (n > epcp->out_maxsize) if (n > epcp->out_maxsize)
n = epcp->out_maxsize; n = epcp->out_maxsize;
/* i is number of bytes remaining to receive minus 1 (to handle 256b case). */ /* I is number of bytes remaining to receive minus 1 (to handle 256b case). */
uint8_t i = n - 1; uint8_t i = n - 1;
/* Must lock for entire operation to ensure nothing changes the ENUM value. */ /* Must lock for entire operation to ensure nothing changes the ENUM value. */

1
os/hal/ports/AVR/TINY/LLD/GPIOv1/hal_pal_lld.c
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@ -189,7 +189,6 @@ void _pal_lld_enablepadevent(ioportid_t port,
#else #else
#error The selected port dont have an EXT INTx pin. #error The selected port dont have an EXT INTx pin.
*/ */
//}
} }
/** /**

2
os/hal/ports/AVR/TINY/LLD/GPIOv1/hal_pal_lld.h
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@ -276,7 +276,7 @@ typedef uint8_t ioeventmode_t;
/*===========================================================================*/ /*===========================================================================*/
/* Implementation, some of the following macros could be implemented as */ /* Implementation, some of the following macros could be implemented as */
/* functions, if so please put them in hal_pal_lld.c. */ /* Functions, if so please put them in hal_pal_lld.c. */
/*===========================================================================*/ /*===========================================================================*/
/** /**

2
os/hal/ports/AVR/TINY/LLD/SYSTICKv1/hal_st_lld.h
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@ -106,7 +106,7 @@ static inline void st_lld_start_alarm(systime_t time) {
/* Reset pending. */ /* Reset pending. */
TIFR_REG = _BV(OCF1A); TIFR_REG = _BV(OCF1A);
/* enable interrupt */ /* Enable interrupt */
TIMSK_REG = _BV(OCIE1A); TIMSK_REG = _BV(OCIE1A);
} }

2
os/hal/ports/AVR/XMEGA/LLD/CRYPv1/hal_crypto_lld.c
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@ -196,7 +196,7 @@ cryerror_t cry_lld_aes_loadkey(CRYDriver *cryp,
(void)cryp; (void)cryp;
if (size != AES_BLOCK_SIZE) { if (size != AES_BLOCK_SIZE) {
return CRY_ERR_INV_KEY_SIZE; /* invalid size error code. */ return CRY_ERR_INV_KEY_SIZE; /* Invalid size error code. */
} }
/* Load the Key into the AES key memory. */ /* Load the Key into the AES key memory. */

5
os/hal/ports/AVR/XMEGA/LLD/CRYPv1/hal_crypto_lld.h
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@ -65,6 +65,7 @@
* @name AVR configuration options * @name AVR configuration options
* @{ * @{
*/ */
/** /**
* @brief CRY1 driver enable switch. * @brief CRY1 driver enable switch.
* @details If set to @p TRUE the support for CRY1 is included. * @details If set to @p TRUE the support for CRY1 is included.
@ -98,8 +99,8 @@ typedef struct CRYDriver CRYDriver;
* @note It could be empty on some architectures. * @note It could be empty on some architectures.
*/ */
typedef struct { typedef struct {
bool autof; // Auto start feature bool autof; /* Auto start feature. */
bool xorf; // XOR feature bool xorf; /* XOR feature. */
} CRYConfig; } CRYConfig;
/** /**

2
os/hal/ports/AVR/XMEGA/LLD/DACv1/hal_dac_lld.h
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@ -181,7 +181,7 @@ typedef struct {
*/ */
typedef struct { typedef struct {
dacchan_t ch; /* DAC channel id. */ dacchan_t ch; /* DAC channel id. */
dactrigmode_t tm; /* register write/event trigger. */ dactrigmode_t tm; /* Register write/event trigger. */
dacopmode_t om; /* DAC operation mode. */ dacopmode_t om; /* DAC operation mode. */
dacajustmode_t da; /* DAC (left/rigth) ajustement. */ dacajustmode_t da; /* DAC (left/rigth) ajustement. */
dacrefsel_t vr; /* DAC voltage reference. */ dacrefsel_t vr; /* DAC voltage reference. */

22
os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.c
View File

@ -88,28 +88,6 @@ OSAL_IRQ_HANDLER(DMA_CH3_vect) {
/* Driver exported functions. */ /* Driver exported functions. */
/*==========================================================================*/ /*==========================================================================*/
// Optional reload of source and destination addresses at the end of each:
// - Burst
// - Block
// - Tansaction
// Optional interrupt at the end of transaction
// Optional connection to CRC generator for CRC on DMA data
// void dma_lld_set_transfer_src() /* source. */
// void dma_lld_set_transfer_dst() /* Destination. */
// void dma_lld_set_transfer_trg() /* Trigger. */
// void dma_lld_set_transfer_siz() /* Size. (1, 2, 4 or 8). */
// void dma_lld_read()
// void dma_lld_write()
// void isr_on_transfer_complate()
// void dma_lld_set_double_buffer_mode()
// void isr_on_error_during_tranfer()
/** /**
* @brief Enable DMA controller. * @brief Enable DMA controller.
* *

1
os/hal/ports/AVR/XMEGA/LLD/DMAv1/xmega_dma_lld.h
View File

@ -41,7 +41,6 @@
/* Driver data structures and types. */ /* Driver data structures and types. */
/*==========================================================================*/ /*==========================================================================*/
/** /**
* @brief Programmable channel priority * @brief Programmable channel priority
*/ */

1
os/hal/ports/AVR/XMEGA/LLD/GPIOv1/hal_pal_lld.c
View File

@ -189,7 +189,6 @@ void _pal_lld_enablepadevent(ioportid_t port,
#else #else
#error The selected port dont have an EXT INTx pin. #error The selected port dont have an EXT INTx pin.
*/ */
//}
} }
/** /**

2
os/hal/ports/AVR/XMEGA/LLD/GPIOv1/hal_pal_lld.h
View File

@ -260,7 +260,7 @@ typedef uint8_t ioeventmode_t;
/*==========================================================================*/ /*==========================================================================*/
/* Implementation, some of the following macros could be implemented as */ /* Implementation, some of the following macros could be implemented as */
/* functions, if so please put them in hal_pal_lld.c. */ /* Functions, if so please put them in hal_pal_lld.c. */
/*==========================================================================*/ /*==========================================================================*/
/** /**

115
os/hal/ports/AVR/XMEGA/LLD/SPIv1/hal_spi_lld.c
View File

@ -57,54 +57,59 @@ SPIDriver SPID2;
/*==========================================================================*/ /*==========================================================================*/
/* Driver local functions. */ /* Driver local functions. */
/*==========================================================================*/ /*==========================================================================*/
/*
// Configure the speed of the SPI interface.
static void spi_set_speed(uint8_t ds) {
// We must make a test to see if we are in master mode.
// ds = double speed; /* Configure the speed of the SPI interface. */
/*
Static void spi_set_speed(uint8_t ds) {
We must make a test to see if we are in master mode.
ds = double speed;
if (ds == SPI_SPEED_DOUBLE) { if (ds == SPI_SPEED_DOUBLE) {
SPIC.CTRL |= (1 << SPI_CLK2X_bp); // double speed. SPIC.CTRL |= (1 << SPI_CLK2X_bp); double speed.
} }
else { else {
SPIC.CTRL &= ~(1 << SPI_CLK2X_bp); // simple speed. SPIC.CTRL &= ~(1 << SPI_CLK2X_bp); simple speed.
} }
} }
*/ */
/* Enable the SPI module. */
// Enable the SPI module.
//static void spi_lld_enable(SPIDriver *spip) {
// spip->spi->CTRL |= (1 << SPI_ENABLE_bp);
//}
/* /*
// Disable the SPI interface. Static void spi_lld_enable(SPIDriver *spip) {
static void spi_disable(void) { spip->spi->CTRL |= (1 << SPI_ENABLE_bp);
}
*/
/* Disable the SPI interface. */
/*
Static void spi_disable(void) {
SPIC.CTRL &= ~(1 << SPI_ENABLE_bp); SPIC.CTRL &= ~(1 << SPI_ENABLE_bp);
} }
*/ */
/* Configure the SPI bit order, LSB/MSB first. */
/* /*
// Configure the SPI bit order, LSB/MSB first. Static void spi_set_bit_order(uint8_t bo) {
static void spi_set_bit_order(uint8_t bo) {
// bo = bit order // bo = bit order
if (bo == SPI_MSB_FIRST) if (bo == SPI_MSB_FIRST)
SPIC.CTRL &= ~(1 << SPI_DORD_bp); SPIC.CTRL &= ~(1 << SPI_DORD_bp);
else else
SPIC.CTRL |= (1 << SPI_DORD_bp); SPIC.CTRL |= (1 << SPI_DORD_bp);
} }
*/
// Configure the SPI interface to Master or slave. /* Configure the SPI interface to Master or slave. */
static void spi_set_mode(uint8_t mode) { /*
Static void spi_set_mode(uint8_t mode) {
if (mode == SPI_MODE_SLAVE) if (mode == SPI_MODE_SLAVE)
SPIC.CTRL &= ~(1 << SPI_MASTER_bp); SPIC.CTRL &= ~(1 << SPI_MASTER_bp);
else else
SPIC.CTRL |= (1 << SPI_MASTER_bp); SPIC.CTRL |= (1 << SPI_MASTER_bp);
} }
*/
static void spi_set_stransfer_mode(SPI_MODE_t mode) { /*
Static void spi_set_stransfer_mode(SPI_MODE_t mode) {
switch(mode) { switch(mode) {
case SPI_TRANSFER_MODE0: case SPI_TRANSFER_MODE0:
SPIC.CTRL = (SPIC.CTRL & ~SPI_MODE_gm) | SPI_MODE_0_gc; SPIC.CTRL = (SPIC.CTRL & ~SPI_MODE_gm) | SPI_MODE_0_gc;
@ -126,14 +131,16 @@ static void spi_set_stransfer_mode(SPI_MODE_t mode) {
SPIC.CTRL = (SPIC.CTRL & ~SPI_MODE_gm) | SPI_MODE_0_gc; SPIC.CTRL = (SPIC.CTRL & ~SPI_MODE_gm) | SPI_MODE_0_gc;
break; break;
} }
}*/ }
*/
/** /**
* @brief Configure the SPI colck from the System clock. * @brief Configure the SPI colck from the System clock.
* *
* @param[in] prescaler the prescaler used to divide the system clock * @param[in] prescaler the prescaler used to divide the system clock
*//* */
static void spi_set_clock_prescaler(SPI_PRESCALER_t prescaler) { /*
Static void spi_set_clock_prescaler(SPI_PRESCALER_t prescaler) {
switch(prescaler) { switch(prescaler) {
case SPI_PRESCALER_4: case SPI_PRESCALER_4:
SPIC.CTRL = (SPIC.CTRL & ~SPI_PRESCALER_gm) | SPI_PRESCALER_DIV4_gc; SPIC.CTRL = (SPIC.CTRL & ~SPI_PRESCALER_gm) | SPI_PRESCALER_DIV4_gc;
@ -162,7 +169,8 @@ static void spi_set_clock_prescaler(SPI_PRESCALER_t prescaler) {
* *
* @param[in] il the interrupt level * @param[in] il the interrupt level
*/ */
/*static void spi_set_irq_level(SPI_INTLVL_t il) { /*
Static void spi_set_irq_level(SPI_INTLVL_t il) {
switch(il) { switch(il) {
case SPI_INT_DISABLE: case SPI_INT_DISABLE:
SPIC.INTCTRL = (SPIC.INTCTRL & ~SPI_INTLVL_gm) | SPI_INTLVL_OFF_gc; SPIC.INTCTRL = (SPIC.INTCTRL & ~SPI_INTLVL_gm) | SPI_INTLVL_OFF_gc;
@ -186,25 +194,27 @@ static void spi_set_clock_prescaler(SPI_PRESCALER_t prescaler) {
} }
} }
Void spi_send_byte(uint8_t data) {
void spi_send_byte(uint8_t data) {
SPIC.DATA = data; SPIC.DATA = data;
while(!(SPIC.STATUS & SPI_IF_bm)); while(!(SPIC.STATUS & SPI_IF_bm));
} }
*/ */
/*
spi_set_speed(SPI_SPEED_SIMPLE); // Configure the speed double.
spi_set_bit_order(SPI_MSB_FIRST); // Configure the bit order.
spi_set_mode(SPI_MODE_MASTER); // Configure the mode to master.
spi_set_stransfer_mode(SPI_TRANSFER_MODE0); // Configure the transfer mode.
spi_set_clock_prescaler(SPI_PRESCALER_4); // Configure the clock prescaler.
spi_set_irq_level(SPI_INT_LEVEL_LOW); // Configure the irq level.
spi_enable(); // Enable the SPI interface.
//spi_select(); // For the chip select. // TODO /*
spi_send_byte(0xAA); // For the chip select. *
//spi_deselect(); // for the chip select. // TODO * Spi_set_speed(SPI_SPEED_SIMPLE); Configure the speed double.
* Spi_set_bit_order(SPI_MSB_FIRST); Configure the bit order.
* Spi_set_mode(SPI_MODE_MASTER); Configure the mode to master.
* Spi_set_stransfer_mode(SPI_TRANSFER_MODE0); Configure the transfer mode.
* Spi_set_clock_prescaler(SPI_PRESCALER_4); Configure the clock prescaler.
* Spi_set_irq_level(SPI_INT_LEVEL_LOW); Configure the irq level.
* Spi_enable(); Enable the SPI interface.
*
* Spi_select(); For the chip select.
* Spi_send_byte(0xAA); For the chip select.
* Spi_deselect(); For the chip select.
*/ */
/*==========================================================================*/ /*==========================================================================*/
/* Driver interrupt handlers. */ /* Driver interrupt handlers. */
/*==========================================================================*/ /*==========================================================================*/
@ -273,11 +283,11 @@ void spi_lld_start(SPIDriver *spip) {
uint8_t dummy; uint8_t dummy;
if (&SPID1 == spip) { if (&SPID1 == spip) {
// Configures the peripheral. /* Configures the peripheral, */
// Note that some bits are forced: /* Note that some bits are forced, */
// SPI interrupt disabled, /* SPI interrupt disabled, */
// SPI enabled, /* SPI enabled, */
// SPI master enabled. /* SPI master enabled, */
spip->spi->INTCTRL = SPI_INTLVL_OFF_gc; spip->spi->INTCTRL = SPI_INTLVL_OFF_gc;
@ -288,12 +298,12 @@ void spi_lld_start(SPIDriver *spip) {
(spip->config->mode) | (spip->config->mode) |
(spip->config->prescaler); (spip->config->prescaler);
// Dummy reads before enabling interrupt. /* Dummy reads before enabling interrupt. */
dummy = spip->spi->STATUS; dummy = spip->spi->STATUS;
dummy = spip->spi->DATA; dummy = spip->spi->DATA;
(void) dummy; // Suppress warning about unused variable. (void) dummy; /* Suppress warning about unused variable. */
// Enable SPI interrupts. /* Enable SPI interrupts. */
spip->spi->INTCTRL = spip->config->irqlevel; spip->spi->INTCTRL = spip->config->irqlevel;
} }
} }
@ -307,7 +317,7 @@ void spi_lld_start(SPIDriver *spip) {
*/ */
void spi_lld_stop(SPIDriver *spip) { void spi_lld_stop(SPIDriver *spip) {
if (spip->state == SPI_READY) { if (spip->state == SPI_READY) {
// Disable the peripheral. /* Disable the peripheral. */
spip->spi->CTRL &= ~(1 << SPI_ENABLE_bp); spip->spi->CTRL &= ~(1 << SPI_ENABLE_bp);
} }
} }
@ -324,7 +334,7 @@ void spi_lld_select(SPIDriver *spip) {
/** /**
* NOTE: This should only be called in master mode. * NOTE: This should only be called in master mode.
*/ */
//spip->config->ssport->out &= ~(1 << spip->config->sspad); /* Spip->config->ssport->out &= ~(1 << spip->config->sspad); */
} }
@ -341,11 +351,12 @@ void spi_lld_unselect(SPIDriver *spip) {
/** /**
* NOTE: This should only be called in master mode. * NOTE: This should only be called in master mode.
*/ */
//spip->config->ssport->out |= (1 << spip->config->sspad); /*
* Spip->config->ssport->out |= (1 << spip->config->sspad);
*/
} }
/** /**
* @brief Exchanges data on the SPI bus. * @brief Exchanges data on the SPI bus.
* @details This asynchronous function starts a simultaneous transmit/receive * @details This asynchronous function starts a simultaneous transmit/receive
@ -403,7 +414,7 @@ uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame) {
uint8_t dummy; uint8_t dummy;
(void)spip; (void)spip;
// Disable interrupt. /* Disable interrupt. */
spip->spi->INTCTRL = SPI_INTLVL_OFF_gc; spip->spi->INTCTRL = SPI_INTLVL_OFF_gc;
spip->spi->DATA = frame; spip->spi->DATA = frame;
@ -412,7 +423,7 @@ uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame) {
dummy = spip->spi->STATUS; dummy = spip->spi->STATUS;
dummy = spip->spi->DATA; dummy = spip->spi->DATA;
(void) dummy; // Suppress warning about unused variable. (void) dummy; /* Suppress warning about unused variable. */
spip->spi->INTCTRL = SPI_INTLVL_LO_gc; spip->spi->INTCTRL = SPI_INTLVL_LO_gc;
return spdr; return spdr;

17
os/hal/ports/AVR/XMEGA/LLD/SPIv1/hal_spi_lld.h
View File

@ -35,7 +35,8 @@
* @name SPI Configuration Register * @name SPI Configuration Register
* @{ * @{
*/ */
/*#define SPI_CR_SPIE (1 << SPIE) /*
#define SPI_CR_SPIE (1 << SPIE)
#define SPI_CR_SPE (1 << SPE) #define SPI_CR_SPE (1 << SPE)
@ -55,7 +56,6 @@
#define SPI_CR_SCK_FOSC_128 (3 << SPR0) #define SPI_CR_SCK_FOSC_128 (3 << SPR0)
*/ */
#define SPI_SPEED_SIMPLE 0 #define SPI_SPEED_SIMPLE 0
#define SPI_SPEED_DOUBLE 1 #define SPI_SPEED_DOUBLE 1
@ -141,7 +141,6 @@
size_t exbytes; \ size_t exbytes; \
size_t exidx; size_t exidx;
/** /**
* @brief Low level fields of the SPI configuration structure. * @brief Low level fields of the SPI configuration structure.
*/ */
@ -223,11 +222,15 @@ extern "C" {
void spi_lld_abort(SPIDriver *spip); void spi_lld_abort(SPIDriver *spip);
#endif #endif
//#if AVR_SPI_USE_16BIT_POLLED_EXCHANGE /*
// uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); #if AVR_SPI_USE_16BIT_POLLED_EXCHANGE
//#else uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
#else
*/
uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame); uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame);
//#endif /*
#endif
*/
#ifdef __cplusplus #ifdef __cplusplus
} }

2
os/hal/ports/AVR/XMEGA/LLD/USARTv1/hal_serial_lld.c
View File

@ -263,7 +263,7 @@ static void usart_start(SerialDriver *sdp, const SerialConfig *config) {
/* Resetting eventual pending status flags. */ /* Resetting eventual pending status flags. */
/* Starting the receiver idle loop. */ /* Starting the receiver idle loop. */
/*uart_enter_rx_idle_loop(uartp);*/ /* Uart_enter_rx_idle_loop(uartp); */
usart_cfg_mpcm(sdp, config); usart_cfg_mpcm(sdp, config);
usart_cfg_clk2x(sdp, config); usart_cfg_clk2x(sdp, config);

19
os/hal/ports/AVR/XMEGA/LLD/USARTv1/hal_uart_lld.c
View File

@ -232,10 +232,8 @@ static void usart_cfg_baudrate(UARTDriver *uartp) {
static void usart_stop(UARTDriver *uartp) { static void usart_stop(UARTDriver *uartp) {
/* Stops RX and TX DMA channels. */ /* Stops RX and TX DMA channels. */
/* /* DmaStreamDisable(uartp->dmarx); */
dmaStreamDisable(uartp->dmarx); /* DmaStreamDisable(uartp->dmatx); */
dmaStreamDisable(uartp->dmatx);
*/
/* Stops USART operations. */ /* Stops USART operations. */
uartp->usart->CTRLB &= ~(USART_RXEN_bm); /* Disable the USART receiver. */ uartp->usart->CTRLB &= ~(USART_RXEN_bm); /* Disable the USART receiver. */
@ -256,7 +254,7 @@ static void usart_start(UARTDriver *uartp) {
/* Resetting eventual pending status flags. */ /* Resetting eventual pending status flags. */
/* Starting the receiver idle loop. */ /* Starting the receiver idle loop. */
/*uart_enter_rx_idle_loop(uartp);*/ /* Uart_enter_rx_idle_loop(uartp); */
usart_cfg_mpcm(uartp); /* Set the multi processor communication mode. */ usart_cfg_mpcm(uartp); /* Set the multi processor communication mode. */
usart_cfg_clk2x(uartp); /* Set the USART speed (Normal/Double). */ usart_cfg_clk2x(uartp); /* Set the USART speed (Normal/Double). */
@ -266,8 +264,8 @@ static void usart_start(UARTDriver *uartp) {
usart_cfg_pmode(uartp); /* Set the parity mode. */ usart_cfg_pmode(uartp); /* Set the parity mode. */
usart_cfg_chsize(uartp);/* Set the character size. */ usart_cfg_chsize(uartp);/* Set the character size. */
usart_cfg_baudrate(uartp); /* Set the baud rate. */ usart_cfg_baudrate(uartp); /* Set the baud rate. */
uartp->usart->CTRLB |= (USART_RXEN_bm); /* enable the USART receiver. */ uartp->usart->CTRLB |= (USART_RXEN_bm); /* Enable the USART receiver. */
uartp->usart->CTRLB |= (USART_TXEN_bm); /* enable the USART transmitter. */ uartp->usart->CTRLB |= (USART_TXEN_bm); /* Enable the USART transmitter. */
} }
/*==========================================================================*/ /*==========================================================================*/
@ -284,7 +282,7 @@ OSAL_IRQ_HANDLER(USARTC0_TXC_vect) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
/*serve_usart_irq(&UARTD1);*/ /* @TODO serve_usart_irq(&UARTD1);*/
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
@ -298,7 +296,7 @@ OSAL_IRQ_HANDLER(USARTC0_RXC_vect) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
/*serve_usart_irq(&UARTD1);*/ /* @TODO serve_usart_irq(&UARTD1);*/
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
@ -312,7 +310,7 @@ OSAL_IRQ_HANDLER(USARTC0_DRE_vect) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
/*serve_usart_irq(&UARTD1);*/ /* @TODO serve_usart_irq(&UARTD1);*/
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
@ -457,7 +455,6 @@ void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
(void)uartp; (void)uartp;
(void)n; (void)n;
(void)rxbuf; (void)rxbuf;
} }
/** /**

17
os/hal/ports/AVR/XMEGA/LLD/WDGv1/hal_wdg_lld.c
View File

@ -102,23 +102,6 @@ static void wdg_disable(WDGDriver *wdgp) {
wdgp->wdg->CTRL = cfg; wdgp->wdg->CTRL = cfg;
} }
/**
* @brief Return status of window mode enable bit.
*
* @param[in] wdgp pointer to the @p WDGDriver object
* @return The status of the watchdog module
* @retval true The WD Window Mode is enabled.
* @retval false The WD Eindow Mode is not enabled.
*/
/*static bool wdg_is_window_mode_enabled(WDGDriver *wdgp) {
if (wdgp->wdg->WINCTRL & WDT_WEN_bm)
return true;
else
return false;
}
*/
/** /**
* @brief Enable watchdog window mode. * @brief Enable watchdog window mode.
* *