Added support for STM32F030xx/050xx/060xx devices.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6593 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
5925c74839
commit
6dc60afb96
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@ -47,7 +47,7 @@
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/*
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/*
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* MCU type as defined in the ST header file stm32f0xx.h.
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* MCU type as defined in the ST header file stm32f0xx.h.
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*/
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*/
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#define STM32F0XX
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#define STM32F0XX_MD
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/*
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/*
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* IO pins assignments.
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* IO pins assignments.
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@ -36,21 +36,29 @@
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN)
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RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN)
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#define AHB_LPEN_MASK AHB_EN_MASK
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#define AHB_LPEN_MASK AHB_EN_MASK
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#elif defined(STM32F0XX)
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#elif defined(STM32F030) || defined(STM32F0XX_MD)
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOFEN)
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RCC_AHBENR_GPIOFEN)
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#elif defined(STM32F0XX_LD)
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIOFEN)
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#elif defined(STM32F2XX)
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#elif defined(STM32F2XX)
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \
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RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \
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RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOIEN)
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RCC_AHB1ENR_GPIOIEN)
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#define AHB1_LPEN_MASK AHB1_EN_MASK
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#define AHB1_LPEN_MASK AHB1_EN_MASK
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#elif defined(STM32F30X) || defined(STM32F37X)
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#elif defined(STM32F30X) || defined(STM32F37X)
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN)
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RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN)
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#elif defined(STM32F4XX)
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#elif defined(STM32F4XX)
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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@ -58,6 +66,7 @@
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RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOIEN)
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RCC_AHB1ENR_GPIOIEN)
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#define AHB1_LPEN_MASK AHB1_EN_MASK
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#define AHB1_LPEN_MASK AHB1_EN_MASK
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#else
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#else
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#error "missing or unsupported platform for GPIOv2 PAL driver"
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#error "missing or unsupported platform for GPIOv2 PAL driver"
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#endif
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#endif
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@ -42,7 +42,8 @@
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#ifndef _STM32_H_
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#ifndef _STM32_H_
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#define _STM32_H_
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#define _STM32_H_
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#if defined(STM32F0XX)
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#if defined(STM32F030) || defined(STM32F0XX_LD) || \
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defined(STM32F0XX_MD)
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#include "stm32f0xx.h"
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#include "stm32f0xx.h"
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#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
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#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
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@ -26,7 +26,9 @@
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* - STM32_HSE_BYPASS (optionally).
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* - STM32_HSE_BYPASS (optionally).
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* .
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* .
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* One of the following macros must also be defined:
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* One of the following macros must also be defined:
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* - STM32F0XX for Entry Level devices.
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* - STM32F030 for Value Line devices.
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* - STM32F0XX_LD for Low Density devices.
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* - STM32F0XX_MD for Medium Density devices.
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* .
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* .
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*
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*
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* @addtogroup HAL
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* @addtogroup HAL
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@ -49,10 +51,24 @@
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#define HAL_IMPLEMENTS_COUNTERS FALSE
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#define HAL_IMPLEMENTS_COUNTERS FALSE
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/**
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/**
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* @name Platform identification
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* @name Platform identification macros
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* @{
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* @{
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*/
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*/
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#define PLATFORM_NAME "STM32F05x Entry Level"
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#if defined(STM32F0XX_MD) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32F051xx/F061xx Entry Level Medium Density devices"
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#define STM32F0XX
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#elif defined(STM32F0XX_LD)
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#define PLATFORM_NAME "STM32F050xx/F060xx Entry Level Low Density devices"
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#define STM32F0XX
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#elif defined(STM32F030)
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#define PLATFORM_NAME "STM32F050xx/F060xx Entry Level Value Line devices"
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#define STM32F0XX
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#else
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#error "STM32F0xx device not specified"
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#endif
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/** @} */
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/** @} */
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/**
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/**
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@ -33,6 +33,8 @@
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* @name STM32F0xx capabilities
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* @name STM32F0xx capabilities
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* @{
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* @{
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*/
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*/
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#if defined(STM32F0XX_MD) || defined(__DOXYGEN__)
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/* ADC attributes.*/
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_ADC2_DMA_MSK 0x00000000
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#define STM32_ADC2_DMA_CHN 0x00000000
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_ADC3_DMA_MSK 0x00000000
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#define STM32_ADC3_DMA_CHN 0x00000000
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#define STM32_HAS_ADC4 FALSE
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#define STM32_HAS_ADC4 FALSE
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#define STM32_ADC4_DMA_MSK 0x00000000
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#define STM32_ADC4_DMA_CHN 0x00000000
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/* CAN attributes.*/
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN1 FALSE
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@ -95,10 +89,6 @@
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#define STM32_I2C2_TX_DMA_CHN 0x00000000
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#define STM32_I2C2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C3 FALSE
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#define STM32_HAS_I2C3 FALSE
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#define STM32_I2C3_RX_DMA_MSK 0
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#define STM32_I2C3_RX_DMA_CHN 0x00000000
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#define STM32_I2C3_TX_DMA_MSK 0
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#define STM32_I2C3_TX_DMA_CHN 0x00000000
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/* RTC attributes.*/
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_HAS_RTC TRUE
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#define STM32_USART2_TX_DMA_CHN 0x00000000
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#define STM32_USART2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_USART3 FALSE
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#define STM32_HAS_USART3 FALSE
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#define STM32_USART3_RX_DMA_MSK 0
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#define STM32_USART3_RX_DMA_CHN 0x00000000
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#define STM32_USART3_TX_DMA_MSK 0
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#define STM32_USART3_TX_DMA_CHN 0x00000000
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_UART4_RX_DMA_MSK 0
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#define STM32_UART4_RX_DMA_CHN 0x00000000
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#define STM32_UART4_TX_DMA_MSK 0
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#define STM32_UART4_TX_DMA_CHN 0x00000000
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_UART5_RX_DMA_MSK 0
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#define STM32_UART5_RX_DMA_CHN 0x00000000
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#define STM32_UART5_TX_DMA_MSK 0
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#define STM32_UART5_TX_DMA_CHN 0x00000000
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_USART6 FALSE
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#define STM32_USART6_RX_DMA_MSK 0
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#define STM32_USART6_RX_DMA_CHN 0x00000000
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#define STM32_USART6_TX_DMA_MSK 0
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#define STM32_USART6_TX_DMA_CHN 0x00000000
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/* USB attributes.*/
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/* USB attributes.*/
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#define STM32_HAS_USB TRUE
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#define STM32_HAS_USB TRUE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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#define STM32_HAS_OTG2 FALSE
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#elif defined(STM32F0XX_LD)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \
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STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_CAN_MAX_FILTERS 0
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/* DAC attributes.*/
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#define STM32_HAS_DAC FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 FALSE
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_CHANNELS 28
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD FALSE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_I2C1_RX_DMA_CHN 0x00000000
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_I2C1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C2 FALSE
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#define STM32_HAS_I2C3 FALSE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS FALSE
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#define STM32_RTC_IS_CALENDAR TRUE
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_SPI1_RX_DMA_CHN 0x00000000
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#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_SPI1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI2 FALSE
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define STM32_HAS_TIM1 TRUE
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#define STM32_HAS_TIM2 TRUE
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#define STM32_HAS_TIM3 TRUE
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#define STM32_HAS_TIM4 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM6 FALSE
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#define STM32_HAS_TIM7 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 TRUE
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#define STM32_HAS_TIM15 FALSE
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#define STM32_HAS_TIM16 TRUE
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#define STM32_HAS_TIM17 TRUE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \
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STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_USART1_RX_DMA_CHN 0x00000000
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#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \
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STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_USART1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_USART2 FALSE
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#define STM32_HAS_USART3 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 FALSE
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/* USB attributes.*/
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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#else /* STM32F030 */
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \
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STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_CAN_MAX_FILTERS 0
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/* DAC attributes.*/
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#define STM32_HAS_DAC FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA FALSE
|
||||||
|
#define STM32_HAS_DMA1 TRUE
|
||||||
|
#define STM32_HAS_DMA2 FALSE
|
||||||
|
|
||||||
|
/* ETH attributes.*/
|
||||||
|
#define STM32_HAS_ETH FALSE
|
||||||
|
|
||||||
|
/* EXTI attributes.*/
|
||||||
|
#define STM32_EXTI_NUM_CHANNELS 28
|
||||||
|
|
||||||
|
/* GPIO attributes.*/
|
||||||
|
#define STM32_HAS_GPIOA TRUE
|
||||||
|
#define STM32_HAS_GPIOB TRUE
|
||||||
|
#define STM32_HAS_GPIOC TRUE
|
||||||
|
#define STM32_HAS_GPIOD TRUE
|
||||||
|
#define STM32_HAS_GPIOE FALSE
|
||||||
|
#define STM32_HAS_GPIOF TRUE
|
||||||
|
#define STM32_HAS_GPIOG FALSE
|
||||||
|
#define STM32_HAS_GPIOH FALSE
|
||||||
|
#define STM32_HAS_GPIOI FALSE
|
||||||
|
|
||||||
|
/* I2C attributes.*/
|
||||||
|
#define STM32_HAS_I2C1 TRUE
|
||||||
|
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
|
||||||
|
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
||||||
|
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
|
||||||
|
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
||||||
|
|
||||||
|
#define STM32_HAS_I2C2 TRUE
|
||||||
|
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||||
|
#define STM32_I2C2_RX_DMA_CHN 0x00000000
|
||||||
|
#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||||
|
#define STM32_I2C2_TX_DMA_CHN 0x00000000
|
||||||
|
|
||||||
|
#define STM32_HAS_I2C3 FALSE
|
||||||
|
|
||||||
|
/* RTC attributes.*/
|
||||||
|
#define STM32_HAS_RTC TRUE
|
||||||
|
#define STM32_RTC_HAS_SUBSECONDS FALSE
|
||||||
|
#define STM32_RTC_IS_CALENDAR TRUE
|
||||||
|
|
||||||
|
/* SDIO attributes.*/
|
||||||
|
#define STM32_HAS_SDIO FALSE
|
||||||
|
|
||||||
|
/* SPI attributes.*/
|
||||||
|
#define STM32_HAS_SPI1 TRUE
|
||||||
|
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||||
|
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
||||||
|
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||||
|
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
||||||
|
|
||||||
|
#define STM32_HAS_SPI2 TRUE
|
||||||
|
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||||
|
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
||||||
|
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||||
|
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
||||||
|
|
||||||
|
#define STM32_HAS_SPI3 FALSE
|
||||||
|
#define STM32_HAS_SPI4 FALSE
|
||||||
|
#define STM32_HAS_SPI5 FALSE
|
||||||
|
#define STM32_HAS_SPI6 FALSE
|
||||||
|
|
||||||
|
/* TIM attributes.*/
|
||||||
|
#define STM32_HAS_TIM1 TRUE
|
||||||
|
#define STM32_HAS_TIM2 FALSE
|
||||||
|
#define STM32_HAS_TIM3 TRUE
|
||||||
|
#define STM32_HAS_TIM4 FALSE
|
||||||
|
#define STM32_HAS_TIM5 FALSE
|
||||||
|
#define STM32_HAS_TIM6 TRUE
|
||||||
|
#define STM32_HAS_TIM7 FALSE
|
||||||
|
#define STM32_HAS_TIM8 FALSE
|
||||||
|
#define STM32_HAS_TIM9 FALSE
|
||||||
|
#define STM32_HAS_TIM10 FALSE
|
||||||
|
#define STM32_HAS_TIM11 FALSE
|
||||||
|
#define STM32_HAS_TIM12 FALSE
|
||||||
|
#define STM32_HAS_TIM13 FALSE
|
||||||
|
#define STM32_HAS_TIM14 TRUE
|
||||||
|
#define STM32_HAS_TIM15 TRUE
|
||||||
|
#define STM32_HAS_TIM16 TRUE
|
||||||
|
#define STM32_HAS_TIM17 TRUE
|
||||||
|
#define STM32_HAS_TIM18 FALSE
|
||||||
|
#define STM32_HAS_TIM19 FALSE
|
||||||
|
|
||||||
|
/* USART attributes.*/
|
||||||
|
#define STM32_HAS_USART1 TRUE
|
||||||
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \
|
||||||
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||||
|
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
||||||
|
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \
|
||||||
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||||
|
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
||||||
|
|
||||||
|
#define STM32_HAS_USART2 TRUE
|
||||||
|
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||||
|
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
||||||
|
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||||
|
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
||||||
|
|
||||||
|
#define STM32_HAS_USART3 FALSE
|
||||||
|
#define STM32_HAS_UART4 FALSE
|
||||||
|
#define STM32_HAS_UART5 FALSE
|
||||||
|
#define STM32_HAS_USART6 FALSE
|
||||||
|
|
||||||
|
/* USB attributes.*/
|
||||||
|
#define STM32_HAS_USB TRUE
|
||||||
|
#define STM32_HAS_OTG1 FALSE
|
||||||
|
#define STM32_HAS_OTG2 FALSE
|
||||||
|
|
||||||
|
#endif /* STM32F030 */
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
#endif /* _STM32_REGISTRY_H_ */
|
#endif /* _STM32_REGISTRY_H_ */
|
||||||
|
|
|
||||||
|
|
@ -2,8 +2,8 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file stm32f0xx.h
|
* @file stm32f0xx.h
|
||||||
* @author MCD Application Team
|
* @author MCD Application Team
|
||||||
* @version V1.0.1
|
* @version V1.2.1
|
||||||
* @date 20-April-2012
|
* @date 22-November-2013
|
||||||
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
|
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
|
||||||
* This file contains all the peripheral register's definitions, bits
|
* This file contains all the peripheral register's definitions, bits
|
||||||
* definitions and memory mapping for STM32F0xx devices.
|
* definitions and memory mapping for STM32F0xx devices.
|
||||||
|
|
@ -25,7 +25,7 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||||
*
|
*
|
||||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||||
* You may not use this file except in compliance with the License.
|
* You may not use this file except in compliance with the License.
|
||||||
|
|
@ -65,21 +65,29 @@
|
||||||
application
|
application
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if !defined (STM32F0XX)
|
#if !defined (STM32F0XX_LD) && !defined (STM32F0XX_MD) && !defined (STM32F030)
|
||||||
#define STM32F0XX /*!< STM32F0XX: STM32F0xx devices */
|
/* #define STM32F0XX_LD */ /*!< STM32F0xx Low-density devices are STM32F050xx and STM32F060xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes */
|
||||||
|
/* #define STM32F0XX_MD */ /*!< STM32F0xx Medium-density devices are STM32F051xx and STM32F061xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes */
|
||||||
|
#define STM32F030 /*!< STM32F030 devices are STM32F030xx value line microcontrollers */
|
||||||
#endif
|
#endif
|
||||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||||
devices, you can define the device in your toolchain compiler preprocessor.
|
devices, you can define the device in your toolchain compiler preprocessor.
|
||||||
|
|
||||||
STM32F0xx devices are:
|
|
||||||
- STM32F050xx microcontrollers where the Flash memory density can go up to 32 Kbytes.
|
|
||||||
- STM32F051xx microcontrollers where the Flash memory density can go up to 64 Kbytes.
|
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if !defined (STM32F0XX)
|
/* Old STM32F0XX definition, maintained for legacy purpose */
|
||||||
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
|
#if defined(STM32F0XX)
|
||||||
|
#define STM32F0XX_MD
|
||||||
#endif /* STM32F0XX */
|
#endif /* STM32F0XX */
|
||||||
|
|
||||||
|
/* Old STM32F030X6/X8 definition, maintained for legacy purpose */
|
||||||
|
#if defined (STM32F030X8) || defined (STM32F030X6)
|
||||||
|
#define STM32F030
|
||||||
|
#endif /* STM32F030X8 or STM32F030X6 */
|
||||||
|
|
||||||
|
#if !defined (STM32F0XX_LD) && !defined (STM32F0XX_MD) && !defined (STM32F030)
|
||||||
|
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
|
||||||
|
#endif
|
||||||
|
|
||||||
#if !defined USE_STDPERIPH_DRIVER
|
#if !defined USE_STDPERIPH_DRIVER
|
||||||
/**
|
/**
|
||||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||||
|
|
@ -105,7 +113,7 @@
|
||||||
Timeout value
|
Timeout value
|
||||||
*/
|
*/
|
||||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||||
#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
|
#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
|
||||||
#endif /* HSE_STARTUP_TIMEOUT */
|
#endif /* HSE_STARTUP_TIMEOUT */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -113,7 +121,7 @@
|
||||||
Timeout value
|
Timeout value
|
||||||
*/
|
*/
|
||||||
#if !defined (HSI_STARTUP_TIMEOUT)
|
#if !defined (HSI_STARTUP_TIMEOUT)
|
||||||
#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */
|
#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */
|
||||||
#endif /* HSI_STARTUP_TIMEOUT */
|
#endif /* HSI_STARTUP_TIMEOUT */
|
||||||
|
|
||||||
#if !defined (HSI_VALUE)
|
#if !defined (HSI_VALUE)
|
||||||
|
|
@ -139,10 +147,10 @@
|
||||||
#endif /* LSE_VALUE */
|
#endif /* LSE_VALUE */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief STM32F0xx Standard Peripheral Library version number V1.0.1
|
* @brief STM32F0xx Standard Peripheral Library version number V1.2.1
|
||||||
*/
|
*/
|
||||||
#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||||
#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||||
#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||||
#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||||
#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
|
#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
|
||||||
|
|
@ -176,8 +184,8 @@ typedef enum IRQn
|
||||||
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
|
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
|
||||||
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
|
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
|
||||||
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
|
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
|
||||||
|
#if defined (STM32F0XX_MD)
|
||||||
/****** STM32F-0 specific Interrupt Numbers *********************************************************/
|
/****** STM32F0XX_MD specific Interrupt Numbers ****************************************************/
|
||||||
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
|
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
|
||||||
PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
|
PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
|
||||||
RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
|
RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
|
||||||
|
|
@ -186,7 +194,7 @@ typedef enum IRQn
|
||||||
EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
|
EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
|
||||||
EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
|
EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
|
||||||
EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
|
EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
|
||||||
TS_IRQn = 8, /*!< TS Interrupt */
|
TS_IRQn = 8, /*!< Touch sense controller Interrupt */
|
||||||
DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
|
DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
|
||||||
DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
|
DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
|
||||||
DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
|
DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
|
||||||
|
|
@ -207,6 +215,57 @@ typedef enum IRQn
|
||||||
USART1_IRQn = 27, /*!< USART1 Interrupt */
|
USART1_IRQn = 27, /*!< USART1 Interrupt */
|
||||||
USART2_IRQn = 28, /*!< USART2 Interrupt */
|
USART2_IRQn = 28, /*!< USART2 Interrupt */
|
||||||
CEC_IRQn = 30 /*!< CEC Interrupt */
|
CEC_IRQn = 30 /*!< CEC Interrupt */
|
||||||
|
#elif defined (STM32F0XX_LD)
|
||||||
|
/****** STM32F0XX_LD specific Interrupt Numbers *****************************************************/
|
||||||
|
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
|
||||||
|
PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
|
||||||
|
RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
|
||||||
|
FLASH_IRQn = 3, /*!< FLASH Interrupt */
|
||||||
|
RCC_IRQn = 4, /*!< RCC Interrupt */
|
||||||
|
EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
|
||||||
|
EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
|
||||||
|
EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
|
||||||
|
DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
|
||||||
|
DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
|
||||||
|
DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
|
||||||
|
ADC1_IRQn = 12, /*!< ADC1 Interrupt */
|
||||||
|
TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
|
||||||
|
TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
|
||||||
|
TIM2_IRQn = 15, /*!< TIM2 Interrupt */
|
||||||
|
TIM3_IRQn = 16, /*!< TIM3 Interrupt */
|
||||||
|
TIM14_IRQn = 19, /*!< TIM14 Interrupt */
|
||||||
|
TIM16_IRQn = 21, /*!< TIM16 Interrupt */
|
||||||
|
TIM17_IRQn = 22, /*!< TIM17 Interrupt */
|
||||||
|
I2C1_IRQn = 23, /*!< I2C1 Interrupt */
|
||||||
|
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
|
||||||
|
USART1_IRQn = 27 /*!< USART1 Interrupt */
|
||||||
|
#elif defined (STM32F030)
|
||||||
|
/****** STM32F030 specific Interrupt Numbers ********************************************************/
|
||||||
|
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
|
||||||
|
RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
|
||||||
|
FLASH_IRQn = 3, /*!< FLASH Interrupt */
|
||||||
|
RCC_IRQn = 4, /*!< RCC Interrupt */
|
||||||
|
EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
|
||||||
|
EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
|
||||||
|
EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
|
||||||
|
DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
|
||||||
|
DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
|
||||||
|
DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
|
||||||
|
ADC1_IRQn = 12, /*!< ADC1 Interrupt */
|
||||||
|
TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
|
||||||
|
TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
|
||||||
|
TIM3_IRQn = 16, /*!< TIM3 Interrupt */
|
||||||
|
TIM14_IRQn = 19, /*!< TIM14 Interrupt */
|
||||||
|
TIM15_IRQn = 20, /*!< TIM15 Interrupt */
|
||||||
|
TIM16_IRQn = 21, /*!< TIM16 Interrupt */
|
||||||
|
TIM17_IRQn = 22, /*!< TIM17 Interrupt */
|
||||||
|
I2C1_IRQn = 23, /*!< I2C1 Interrupt */
|
||||||
|
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
|
||||||
|
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
|
||||||
|
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
|
||||||
|
USART1_IRQn = 27, /*!< USART1 Interrupt */
|
||||||
|
USART2_IRQn = 28 /*!< USART2 Interrupt */
|
||||||
|
#endif /* STM32F0XX_MD */
|
||||||
} IRQn_Type;
|
} IRQn_Type;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -1392,7 +1451,7 @@ typedef struct
|
||||||
/* Old BOOT1 bit definition, maintained for legacy purpose */
|
/* Old BOOT1 bit definition, maintained for legacy purpose */
|
||||||
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
|
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
|
||||||
|
|
||||||
/* Old BOOT1 bit definition, maintained for legacy purpose */
|
/* Old OBR_VDDA bit definition, maintained for legacy purpose */
|
||||||
#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
|
#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
|
||||||
|
|
||||||
/****************** Bit definition for FLASH_WRPR register ******************/
|
/****************** Bit definition for FLASH_WRPR register ******************/
|
||||||
|
|
@ -2005,6 +2064,18 @@ typedef struct
|
||||||
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
|
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
|
||||||
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
|
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
|
||||||
|
|
||||||
|
#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler (only for STM32F0XX_LD and STM32FO30X6 devices)*/
|
||||||
|
#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
|
||||||
|
#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
|
||||||
|
#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
|
||||||
|
#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
|
||||||
|
#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
|
||||||
|
#define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
|
||||||
|
#define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
|
||||||
|
#define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
|
||||||
|
|
||||||
|
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO (only for STM32F0XX_LD and STM32FO30X6 devices) */
|
||||||
|
|
||||||
/*!<****************** Bit definition for RCC_CIR register ********************/
|
/*!<****************** Bit definition for RCC_CIR register ********************/
|
||||||
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
|
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
|
||||||
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
|
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
|
||||||
|
|
@ -2548,6 +2619,9 @@ typedef struct
|
||||||
#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
|
#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
|
||||||
#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
|
#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
|
||||||
#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
|
#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
|
||||||
|
#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0XX_LD and STM32FO30X6 devices) */
|
||||||
|
#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F0XX_LD and STM32FO30X6 devices) */
|
||||||
|
#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F0XX_LD and STM32FO30X6 devices) */
|
||||||
|
|
||||||
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
|
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
|
||||||
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
|
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
|
||||||
|
|
|
||||||
|
|
@ -58,17 +58,22 @@
|
||||||
#if defined(STM32F429_439xx) || defined(__DOXYGEN__)
|
#if defined(STM32F429_439xx) || defined(__DOXYGEN__)
|
||||||
#define PLATFORM_NAME "STM32F429/F439 High Performance with DSP and FPU"
|
#define PLATFORM_NAME "STM32F429/F439 High Performance with DSP and FPU"
|
||||||
#define STM32F4XX
|
#define STM32F4XX
|
||||||
#elif defined(STM32F427_437xx) || defined(__DOXYGEN__)
|
|
||||||
|
#elif defined(STM32F427_437xx)
|
||||||
#define PLATFORM_NAME "STM32F427/F437 High Performance with DSP and FPU"
|
#define PLATFORM_NAME "STM32F427/F437 High Performance with DSP and FPU"
|
||||||
#define STM32F4XX
|
#define STM32F4XX
|
||||||
#elif defined(STM32F40_41xxx) || defined(__DOXYGEN__)
|
|
||||||
|
#elif defined(STM32F40_41xxx)
|
||||||
#define PLATFORM_NAME "STM32F407/F417 High Performance with DSP and FPU"
|
#define PLATFORM_NAME "STM32F407/F417 High Performance with DSP and FPU"
|
||||||
#define STM32F4XX
|
#define STM32F4XX
|
||||||
#elif defined(STM32F401xx) || defined(__DOXYGEN__)
|
|
||||||
|
#elif defined(STM32F401xx)
|
||||||
#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU"
|
#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU"
|
||||||
#define STM32F4XX
|
#define STM32F4XX
|
||||||
#elif defined(STM32F2XX) || defined(__DOXYGEN__)
|
|
||||||
|
#elif defined(STM32F2XX)
|
||||||
#define PLATFORM_NAME "STM32F2xx High Performance"
|
#define PLATFORM_NAME "STM32F2xx High Performance"
|
||||||
|
|
||||||
#else
|
#else
|
||||||
#error "STM32F2xx/F4xx device not specified"
|
#error "STM32F2xx/F4xx device not specified"
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -145,6 +145,7 @@
|
||||||
(backported to 2.6.0).
|
(backported to 2.6.0).
|
||||||
- FIX: Fixed MS2ST() and US2ST() macros error (bug #415)(backported to 2.6.0,
|
- FIX: Fixed MS2ST() and US2ST() macros error (bug #415)(backported to 2.6.0,
|
||||||
2.4.4, 2.2.10, NilRTOS).
|
2.4.4, 2.2.10, NilRTOS).
|
||||||
|
- NEW: Added support for STM32F030xx/050xx/060xx devices.
|
||||||
- NEW: Added BOARD_OTG_NOVBUSSENS board option for STM32 OTG.
|
- NEW: Added BOARD_OTG_NOVBUSSENS board option for STM32 OTG.
|
||||||
- NEW: Added SPI4/SPI5/SPI6 support to the STM32v1 SPIv1 low level driver.
|
- NEW: Added SPI4/SPI5/SPI6 support to the STM32v1 SPIv1 low level driver.
|
||||||
- NEW: Added chvprintf() and chsnprintf() functions to the chprintf module.
|
- NEW: Added chvprintf() and chsnprintf() functions to the chprintf module.
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue