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ChibiOS
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This commit is contained in:
Andrey Gusakov 2023-05-31 22:59:40 +03:00 committed by rusefillc
parent 2bbee81c28
commit 86cacdf737
2 changed files with 177 additions and 99 deletions
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274
os/hal/ports/AT32/AT32F4xx/at32_isr.c
View File

@ -51,38 +51,166 @@
/* Driver interrupt handlers. */ /* Driver interrupt handlers. */
/*===========================================================================*/ /*===========================================================================*/
#include "stm32_exti0.inc" #if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__)
#include "stm32_exti1.inc" #if !defined(STM32_DISABLE_EXTI0_HANDLER)
#include "stm32_exti2.inc" /**
#include "stm32_exti3.inc" * @brief EXTI[0] interrupt handler.
#include "stm32_exti4.inc" *
#include "stm32_exti5_9.inc" * @isr
#include "stm32_exti10_15.inc" */
#include "stm32_exti16.inc" OSAL_IRQ_HANDLER(Vector58) {
#include "stm32_exti17.inc" uint32_t pr;
#include "stm32_exti18.inc"
#include "stm32_exti19.inc"
#include "stm32_exti20.inc"
#include "stm32_exti21.inc"
#include "stm32_exti22.inc"
#include "stm32_usart1.inc" OSAL_IRQ_PROLOGUE();
#include "stm32_usart2.inc"
#include "stm32_usart3.inc"
#include "stm32_uart4.inc"
#include "stm32_uart5.inc"
#include "stm32_usart6.inc"
#include "stm32_uart7.inc"
#include "stm32_uart8.inc"
#include "stm32_tim1_9_10_11.inc" pr = EXTI->PR;
#include "stm32_tim2.inc" pr &= EXTI->IMR & (1U << 0);
#include "stm32_tim3.inc" EXTI->PR = pr;
#include "stm32_tim4.inc"
#include "stm32_tim5.inc" exti_serve_irq(pr, 0);
#include "stm32_tim6.inc"
#include "stm32_tim7.inc" OSAL_IRQ_EPILOGUE();
#include "stm32_tim8_12_13_14.inc" }
#endif
#if !defined(STM32_DISABLE_EXTI1_HANDLER)
/**
* @brief EXTI[1] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector5C) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & (1U << 1);
EXTI->PR = pr;
exti_serve_irq(pr, 1);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(STM32_DISABLE_EXTI2_HANDLER)
/**
* @brief EXTI[2] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector60) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & (1U << 2);
EXTI->PR = pr;
exti_serve_irq(pr, 2);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(STM32_DISABLE_EXTI3_HANDLER)
/**
* @brief EXTI[3] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector64) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & (1U << 3);
EXTI->PR = pr;
exti_serve_irq(pr, 3);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(STM32_DISABLE_EXTI4_HANDLER)
/**
* @brief EXTI[4] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector68) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & (1U << 4);
EXTI->PR = pr;
exti_serve_irq(pr, 4);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
/**
* @brief EXTI[5]...EXTI[9] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector9C) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
(1U << 9));
EXTI->PR = pr;
exti_serve_irq(pr, 5);
exti_serve_irq(pr, 6);
exti_serve_irq(pr, 7);
exti_serve_irq(pr, 8);
exti_serve_irq(pr, 9);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
/**
* @brief EXTI[10]...EXTI[15] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(VectorE0) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
(1U << 14) | (1U << 15));
EXTI->PR = pr;
exti_serve_irq(pr, 10);
exti_serve_irq(pr, 11);
exti_serve_irq(pr, 12);
exti_serve_irq(pr, 13);
exti_serve_irq(pr, 14);
exti_serve_irq(pr, 15);
OSAL_IRQ_EPILOGUE();
}
#endif
#endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported functions. */ /* Driver exported functions. */
@ -95,40 +223,15 @@
*/ */
void irqInit(void) { void irqInit(void) {
exti0_irq_init(); #if HAL_USE_PAL
exti1_irq_init(); nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY);
exti2_irq_init(); nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY);
exti3_irq_init(); nvicEnableVector(EXTI2_IRQn, STM32_IRQ_EXTI2_PRIORITY);
exti4_irq_init(); nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY);
exti5_9_irq_init(); nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY);
exti10_15_irq_init(); nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY);
exti16_irq_init(); nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY);
exti17_irq_init(); #endif
exti18_irq_init();
exti19_irq_init();
exti20_irq_init();
exti21_irq_init();
exti22_irq_init();
tim1_tim9_tim10_tim11_irq_init();
tim2_irq_init();
tim3_irq_init();
tim4_irq_init();
tim5_irq_init();
tim6_irq_init();
tim7_irq_init();
tim8_tim12_tim13_tim14_irq_init();
usart1_irq_init();
usart2_irq_init();
usart3_irq_init();
uart4_irq_init();
uart5_irq_init();
usart6_irq_init();
uart7_irq_init();
uart8_irq_init();
uart9_irq_init();
uart10_irq_init();
} }
/** /**
@ -138,40 +241,15 @@ void irqInit(void) {
*/ */
void irqDeinit(void) { void irqDeinit(void) {
exti0_irq_deinit(); #if HAL_USE_PAL
exti1_irq_deinit(); nvicDisableVector(EXTI0_IRQn);
exti2_irq_deinit(); nvicDisableVector(EXTI1_IRQn);
exti3_irq_deinit(); nvicDisableVector(EXTI2_IRQn);
exti4_irq_deinit(); nvicDisableVector(EXTI3_IRQn);
exti5_9_irq_deinit(); nvicDisableVector(EXTI4_IRQn);
exti10_15_irq_deinit(); nvicDisableVector(EXTI9_5_IRQn);
exti16_irq_deinit(); nvicDisableVector(EXTI15_10_IRQn);
exti17_irq_deinit(); #endif
exti18_irq_deinit();
exti19_irq_deinit();
exti20_irq_deinit();
exti21_irq_deinit();
exti22_irq_deinit();
tim1_tim9_tim10_tim11_irq_deinit();
tim2_irq_deinit();
tim3_irq_deinit();
tim4_irq_deinit();
tim5_irq_deinit();
tim6_irq_deinit();
tim7_irq_deinit();
tim8_tim12_tim13_tim14_irq_deinit();
usart1_irq_deinit();
usart2_irq_deinit();
usart3_irq_deinit();
uart4_irq_deinit();
uart5_irq_deinit();
usart6_irq_deinit();
uart7_irq_deinit();
uart8_irq_deinit();
uart9_irq_deinit();
uart10_irq_deinit();
} }
/** @} */ /** @} */

2
os/hal/ports/AT32/AT32F4xx/platform.mk
View File

@ -38,7 +38,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/driver_v2.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/driver.mk