STM32F7 working... almost.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8151 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2015-08-03 13:11:07 +00:00
parent 15e182dd82
commit 942a0696ce
3 changed files with 23 additions and 1 deletions

View File

@ -494,6 +494,8 @@
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#define CORTEX_VTOR_INIT 0x08000000U
#endif /* _CHCONF_H_ */
/** @} */

View File

@ -100,7 +100,7 @@ void _pal_lld_init(const PALConfig *config) {
rccEnableAHB(AHB_EN_MASK, TRUE);
#elif defined(STM32F3XX) || defined(STM32F37X)
rccEnableAHB(AHB_EN_MASK, TRUE);
#elif defined(STM32F2XX) || defined(STM32F4XX)
#elif defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX)
RCC->AHB1ENR |= AHB1_EN_MASK;
RCC->AHB1LPENR |= AHB1_LPEN_MASK;
#endif
@ -135,6 +135,12 @@ void _pal_lld_init(const PALConfig *config) {
#if STM32_HAS_GPIOI
initgpio(GPIOI, &config->PIData);
#endif
#if STM32_HAS_GPIOJ
initgpio(GPIOJ, &config->PJData);
#endif
#if STM32_HAS_GPIOK
initgpio(GPIOK, &config->PKData);
#endif
}
/**

View File

@ -363,6 +363,20 @@ typedef stm32_gpio_t * ioportid_t;
#define IOPORT9 GPIOI
#endif
/**
* @brief GPIO port J identifier.
*/
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
#define IOPORT10 GPIOJ
#endif
/**
* @brief GPIO port K identifier.
*/
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
#define IOPORT11 GPIOK
#endif
/*===========================================================================*/
/* Implementation, some of the following macros could be implemented as */
/* functions, if so please put them in pal_lld.c. */