Updates to STM32WBxx support
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13952 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -114,7 +114,7 @@
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_USE_ADC2 FALSE
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#define STM32_ADC_USE_ADC3 FALSE
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC12_IRQ_PRIORITY 5
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
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@ -134,10 +134,10 @@
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_USE_I2C3 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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@ -182,10 +182,10 @@
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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@ -207,8 +207,8 @@
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* UART driver system settings.
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*/
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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@ -222,6 +222,6 @@
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* WSPI driver system settings.
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#endif /* MCUCONF_H */
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@ -114,7 +114,7 @@
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_USE_ADC2 FALSE
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#define STM32_ADC_USE_ADC3 FALSE
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC12_IRQ_PRIORITY 5
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
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@ -134,10 +134,10 @@
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_USE_I2C3 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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@ -182,10 +182,10 @@
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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@ -207,8 +207,8 @@
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* UART driver system settings.
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*/
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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@ -222,6 +222,6 @@
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* WSPI driver system settings.
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#endif /* MCUCONF_H */
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@ -1,5 +1,5 @@
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/*
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ChibiOS - Copyright (C) 2006..2020 Ilya Kharin
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -1,5 +1,5 @@
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/*
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ChibiOS - Copyright (C) 2006..2020 Ilya Kharin
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -208,7 +208,9 @@
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#define GPIOG_PIN15 15U
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#define GPIOH_PIN0 0U
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#define GPIOH_OSC_IN 0U
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#define GPIOH_PIN1 1U
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#define GPIOH_OSC_OUT 1U
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#define GPIOH_PIN2 2U
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#define GPIOH_PIN3 3U
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#define GPIOH_PIN4 4U
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@ -248,6 +250,9 @@
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#define LINE_OSC32_IN PAL_LINE(GPIOC, GPIOC_PIN14)
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#define LINE_OSC32_OUT PAL_LINE(GPIOC, GPIOC_PIN15)
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#define LINE_OSC_IN PAL_LINE(GPIOH, GPIOH_PIN0)
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#define LINE_OSC_OUT PAL_LINE(GPIOH, GPIOH_PIN1)
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*
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ChibiOS - Copyright (C) 2006..2019 Ilya Kharin
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -1,5 +1,5 @@
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/*
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ChibiOS - Copyright (C) 2006..2019 Ilya Kharin
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -235,7 +235,9 @@
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#define GPIOG_PIN14 14U
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#define GPIOG_PIN15 15U
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#define GPIOH_PIN0 0U
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#define GPIOH_OSC_IN 0U
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#define GPIOH_PIN1 1U
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#define GPIOH_OSC_OUT 1U
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#define GPIOH_PIN2 2U
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#define GPIOH_PIN3 3U
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@ -280,6 +282,9 @@
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#define LINE_B3 PAL_LINE(GPIOD, GPIOD_PIN1)
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#define LINE_BUTTON_3 PAL_LINE(GPIOD, GPIOD_PIN1)
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#define LINE_OSC_IN PAL_LINE(GPIOH, GPIOH_PIN0)
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#define LINE_OSC_OUT PAL_LINE(GPIOH, GPIOH_PIN1)
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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@ -1,244 +1,264 @@
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/*
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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Concepts and parts of this file have been contributed by Ilya Kharin.
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*/
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/**
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* @file STM32WBxx/stm32_registry.h
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* @brief STM32WBxx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef STM32_REGISTRY_H
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#define STM32_REGISTRY_H
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name STM32WBxx capabilities
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* @{
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*/
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/*===========================================================================*/
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/* Common. */
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/*===========================================================================*/
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/* RNG attributes.*/
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#define STM32_HAS_RNG1 TRUE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
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#define STM32_RTC_NUM_ALARMS 2
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#define STM32_RTC_STORAGE_SIZE 80
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#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
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#define STM32_RTC_WKUP_HANDLER Vector4C
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#define STM32_RTC_ALARM_HANDLER VectorE4
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#define STM32_RTC_TAMP_STAMP_NUMBER 2
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#define STM32_RTC_WKUP_NUMBER 3
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#define STM32_RTC_ALARM_NUMBER 41
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#define STM32_RTC_ALARM_EXTI 17
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#define STM32_RTC_TAMP_STAMP_EXTI 18
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#define STM32_RTC_WKUP_EXTI 19
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#define STM32_RTC_IRQ_ENABLE() do { \
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nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
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nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
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nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \
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} while (false)
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#define STM32_HAS_HASH1 TRUE
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#define STM32_HAS_CRYP1 TRUE
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/*===========================================================================*/
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/* STM32WB55xx. */
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/*===========================================================================*/
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#if defined(STM32WB55xx) || defined(__DOXYGEN__)
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/* Clock attributes.*/
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#define STM32_CLOCK_HAS_HSI48 TRUE
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_HAS_CAN3 FALSE
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 FALSE
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#define STM32_HAS_DAC1_CH2 FALSE
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_DMAMUX TRUE
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#define STM32_DMA_SUPPORTS_CSELR FALSE
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#define STM32_DMA1_NUM_CHANNELS 7
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#define STM32_DMA2_NUM_CHANNELS 7
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_LINES 40
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#define STM32_EXTI_IMR1_MASK 0x7FC00000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
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/* Flash attributes.*/
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#define STM32_FLASH_NUMBER_OF_BANKS 1
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#define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
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RCC_AHB2ENR_GPIOBEN | \
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RCC_AHB2ENR_GPIOCEN | \
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RCC_AHB2ENR_GPIODEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C3 TRUE
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#define STM32_I2C_USE_I2C2 FALSE
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/* QUADSPI attributes.*/
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#define STM32_HAS_QUADSPI1 TRUE
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/* SDMMC attributes.*/
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#define STM32_HAS_SDMMC1 FALSE
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#define STM32_HAS_SDMMC2 FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 4
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 4
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 2
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 2
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#define STM32_HAS_TIM3 FALSE
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#define STM32_HAS_TIM4 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM6 FALSE
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#define STM32_HAS_TIM7 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM15 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_HAS_LPUART1 TRUE
|
||||
#define STM32_HAS_USART2 FALSE
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_HAS_UART7 FALSE
|
||||
#define STM32_HAS_UART8 FALSE
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
|
||||
#define STM32_USB_PMA_SIZE 1024
|
||||
#define STM32_USB_HAS_BCDR TRUE
|
||||
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* IWDG attributes.*/
|
||||
#define STM32_HAS_IWDG TRUE
|
||||
#define STM32_IWDG_IS_WINDOWED TRUE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
|
||||
/* CRC attributes.*/
|
||||
#define STM32_HAS_CRC TRUE
|
||||
#define STM32_CRC_PROGRAMMABLE TRUE
|
||||
#endif /* defined(STM32WB50xx) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32WB50xx. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if defined(STM32WB50xx) || defined(__DOXYGEN__)
|
||||
#error "STM32WB50xx is not supported"
|
||||
#endif /* defined(STM32WB50xx) */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* STM32_REGISTRY_H */
|
||||
|
||||
/** @} */
|
||||
/*
|
||||
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
/*
|
||||
Concepts and parts of this file have been contributed by Ilya Kharin.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32WBxx/stm32_registry.h
|
||||
* @brief STM32WBxx capabilities registry.
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef STM32_REGISTRY_H
|
||||
#define STM32_REGISTRY_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name STM32WBxx capabilities
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Common. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* RNG attributes.*/
|
||||
#define STM32_HAS_RNG1 TRUE
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
||||
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
||||
#define STM32_RTC_NUM_ALARMS 2
|
||||
#define STM32_RTC_STORAGE_SIZE 80
|
||||
#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
|
||||
#define STM32_RTC_WKUP_HANDLER Vector4C
|
||||
#define STM32_RTC_ALARM_HANDLER VectorE4
|
||||
#define STM32_RTC_TAMP_STAMP_NUMBER 2
|
||||
#define STM32_RTC_WKUP_NUMBER 3
|
||||
#define STM32_RTC_ALARM_NUMBER 41
|
||||
#define STM32_RTC_ALARM_EXTI 17
|
||||
#define STM32_RTC_TAMP_STAMP_EXTI 18
|
||||
#define STM32_RTC_WKUP_EXTI 19
|
||||
#define STM32_RTC_IRQ_ENABLE() do { \
|
||||
nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
|
||||
nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \
|
||||
nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \
|
||||
} while (false)
|
||||
|
||||
#define STM32_HAS_HASH1 TRUE
|
||||
#define STM32_HAS_CRYP1 TRUE
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32WB55xx. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if defined(STM32WB55xx) || defined(__DOXYGEN__)
|
||||
|
||||
/* Clock attributes.*/
|
||||
#define STM32_CLOCK_HAS_HSI48 TRUE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 FALSE
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
#define STM32_HAS_ADC4 FALSE
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_CAN1 FALSE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
#define STM32_HAS_CAN3 FALSE
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC1_CH1 FALSE
|
||||
#define STM32_HAS_DAC1_CH2 FALSE
|
||||
#define STM32_HAS_DAC2_CH1 FALSE
|
||||
#define STM32_HAS_DAC2_CH2 FALSE
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA TRUE
|
||||
#define STM32_DMA_SUPPORTS_DMAMUX TRUE
|
||||
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
||||
#define STM32_DMA1_NUM_CHANNELS 7
|
||||
#define STM32_DMA2_NUM_CHANNELS 7
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_NUM_LINES 49
|
||||
#define STM32_EXTI_IMR1_MASK 0x7FC00000U
|
||||
#define STM32_EXTI_IMR2_MASK 0xFFFFFCFDU
|
||||
|
||||
/* Flash attributes.*/
|
||||
#define STM32_FLASH_NUMBER_OF_BANKS 1
|
||||
#define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF FALSE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
#define STM32_HAS_GPIOJ FALSE
|
||||
#define STM32_HAS_GPIOK FALSE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
|
||||
RCC_AHB2ENR_GPIOBEN | \
|
||||
RCC_AHB2ENR_GPIOCEN | \
|
||||
RCC_AHB2ENR_GPIODEN | \
|
||||
RCC_AHB2ENR_GPIOEEN | \
|
||||
RCC_AHB2ENR_GPIOHEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_HAS_I2C3 TRUE
|
||||
|
||||
#define STM32_HAS_I2C2 FALSE
|
||||
#define STM32_HAS_I2C4 FALSE
|
||||
|
||||
/* QUADSPI attributes.*/
|
||||
#define STM32_HAS_QUADSPI1 TRUE
|
||||
|
||||
/* SDMMC attributes.*/
|
||||
#define STM32_HAS_SDMMC1 FALSE
|
||||
#define STM32_HAS_SDMMC2 FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_SUPPORTS_I2S FALSE
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI2_SUPPORTS_I2S FALSE
|
||||
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
#define STM32_HAS_SPI5 FALSE
|
||||
#define STM32_HAS_SPI6 FALSE
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_TIM_MAX_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_TIM1_IS_32BITS FALSE
|
||||
#define STM32_TIM1_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_TIM2_IS_32BITS TRUE
|
||||
#define STM32_TIM2_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM3 FALSE
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM6 FALSE
|
||||
#define STM32_HAS_TIM7 FALSE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM15 FALSE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
#define STM32_HAS_TIM20 FALSE
|
||||
#define STM32_HAS_TIM21 FALSE
|
||||
#define STM32_HAS_TIM22 FALSE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_HAS_LPUART1 TRUE
|
||||
#define STM32_HAS_USART2 FALSE
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_HAS_UART7 FALSE
|
||||
#define STM32_HAS_UART8 FALSE
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
|
||||
#define STM32_USB_PMA_SIZE 1024
|
||||
#define STM32_USB_HAS_BCDR TRUE
|
||||
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* IWDG attributes.*/
|
||||
#define STM32_HAS_IWDG TRUE
|
||||
#define STM32_IWDG_IS_WINDOWED TRUE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC FALSE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
|
||||
/* CRC attributes.*/
|
||||
#define STM32_HAS_CRC TRUE
|
||||
#define STM32_CRC_PROGRAMMABLE TRUE
|
||||
#endif /* defined(STM32WB55xx) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32WB50xx. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if defined(STM32WB50xx) || defined(__DOXYGEN__)
|
||||
#error "STM32WB50xx is not supported"
|
||||
#endif /* defined(STM32WB50xx) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32WB35xx. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if defined(STM32WB35xx) || defined(__DOXYGEN__)
|
||||
#error "STM32WB35xx is not supported"
|
||||
#endif /* defined(STM32WB35xx) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32WB30xx. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if defined(STM32WB30xx) || defined(__DOXYGEN__)
|
||||
#error "STM32WB30xx is not supported"
|
||||
#endif /* defined(STM32WB30xx) */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* STM32_REGISTRY_H */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
Loading…
Reference in New Issue