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Updates to STM32WBxx support 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13952 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
cinsights 2020-12-15 11:31:26 +00:00
parent 2d27c48c91
commit 9447149dfb
7 changed files with 302 additions and 272 deletions
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24
demos/STM32/RT-STM32WB55CG-NUCLEO-USBDongle/cfg/mcuconf.h
View File

@ -114,7 +114,7 @@
#define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE #define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE #define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@ -134,10 +134,10 @@
#define STM32_I2C_USE_I2C1 FALSE #define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C3 FALSE #define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50 #define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5 #define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3 #define STM32_I2C_I2C1_DMA_PRIORITY 3
@ -182,10 +182,10 @@
*/ */
#define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10 #define STM32_SPI_SPI1_IRQ_PRIORITY 10
@ -207,8 +207,8 @@
* UART driver system settings. * UART driver system settings.
*/ */
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
@ -222,6 +222,6 @@
* WSPI driver system settings. * WSPI driver system settings.
*/ */
#define STM32_WSPI_USE_QUADSPI1 FALSE #define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#endif /* MCUCONF_H */ #endif /* MCUCONF_H */

24
demos/STM32/RT-STM32WB55RG-NUCLEO/cfg/mcuconf.h
View File

@ -114,7 +114,7 @@
#define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE #define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE #define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
@ -134,10 +134,10 @@
#define STM32_I2C_USE_I2C1 FALSE #define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C3 FALSE #define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50 #define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_I2C_I2C1_IRQ_PRIORITY 5 #define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3 #define STM32_I2C_I2C1_DMA_PRIORITY 3
@ -182,10 +182,10 @@
*/ */
#define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10 #define STM32_SPI_SPI1_IRQ_PRIORITY 10
@ -207,8 +207,8 @@
* UART driver system settings. * UART driver system settings.
*/ */
#define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
@ -222,6 +222,6 @@
* WSPI driver system settings. * WSPI driver system settings.
*/ */
#define STM32_WSPI_USE_QUADSPI1 FALSE #define STM32_WSPI_USE_QUADSPI1 FALSE
#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#endif /* MCUCONF_H */ #endif /* MCUCONF_H */

2
os/hal/boards/ST_NUCLEO_WB55CG_USBDongle/board.c
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@ -1,5 +1,5 @@
/* /*
ChibiOS - Copyright (C) 2006..2020 Ilya Kharin ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.

7
os/hal/boards/ST_NUCLEO_WB55CG_USBDongle/board.h
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@ -1,5 +1,5 @@
/* /*
ChibiOS - Copyright (C) 2006..2020 Ilya Kharin ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
@ -208,7 +208,9 @@
#define GPIOG_PIN15 15U #define GPIOG_PIN15 15U
#define GPIOH_PIN0 0U #define GPIOH_PIN0 0U
#define GPIOH_OSC_IN 0U
#define GPIOH_PIN1 1U #define GPIOH_PIN1 1U
#define GPIOH_OSC_OUT 1U
#define GPIOH_PIN2 2U #define GPIOH_PIN2 2U
#define GPIOH_PIN3 3U #define GPIOH_PIN3 3U
#define GPIOH_PIN4 4U #define GPIOH_PIN4 4U
@ -248,6 +250,9 @@
#define LINE_OSC32_IN PAL_LINE(GPIOC, GPIOC_PIN14) #define LINE_OSC32_IN PAL_LINE(GPIOC, GPIOC_PIN14)
#define LINE_OSC32_OUT PAL_LINE(GPIOC, GPIOC_PIN15) #define LINE_OSC32_OUT PAL_LINE(GPIOC, GPIOC_PIN15)
#define LINE_OSC_IN PAL_LINE(GPIOH, GPIOH_PIN0)
#define LINE_OSC_OUT PAL_LINE(GPIOH, GPIOH_PIN1)
/*===========================================================================*/ /*===========================================================================*/
/* Driver pre-compile time settings. */ /* Driver pre-compile time settings. */
/*===========================================================================*/ /*===========================================================================*/

2
os/hal/boards/ST_NUCLEO_WB55RG/board.c
View File

@ -1,5 +1,5 @@
/* /*
ChibiOS - Copyright (C) 2006..2019 Ilya Kharin ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.

7
os/hal/boards/ST_NUCLEO_WB55RG/board.h
View File

@ -1,5 +1,5 @@
/* /*
ChibiOS - Copyright (C) 2006..2019 Ilya Kharin ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
@ -235,7 +235,9 @@
#define GPIOG_PIN14 14U #define GPIOG_PIN14 14U
#define GPIOG_PIN15 15U #define GPIOG_PIN15 15U
#define GPIOH_PIN0 0U
#define GPIOH_OSC_IN 0U #define GPIOH_OSC_IN 0U
#define GPIOH_PIN1 1U
#define GPIOH_OSC_OUT 1U #define GPIOH_OSC_OUT 1U
#define GPIOH_PIN2 2U #define GPIOH_PIN2 2U
#define GPIOH_PIN3 3U #define GPIOH_PIN3 3U
@ -280,6 +282,9 @@
#define LINE_B3 PAL_LINE(GPIOD, GPIOD_PIN1) #define LINE_B3 PAL_LINE(GPIOD, GPIOD_PIN1)
#define LINE_BUTTON_3 PAL_LINE(GPIOD, GPIOD_PIN1) #define LINE_BUTTON_3 PAL_LINE(GPIOD, GPIOD_PIN1)
#define LINE_OSC_IN PAL_LINE(GPIOH, GPIOH_PIN0)
#define LINE_OSC_OUT PAL_LINE(GPIOH, GPIOH_PIN1)
/*===========================================================================*/ /*===========================================================================*/
/* Driver pre-compile time settings. */ /* Driver pre-compile time settings. */
/*===========================================================================*/ /*===========================================================================*/

34
os/hal/ports/STM32/STM32WBxx/stm32_registry.h
View File

@ -105,9 +105,9 @@
#define STM32_HAS_ETH FALSE #define STM32_HAS_ETH FALSE
/* EXTI attributes.*/ /* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 40 #define STM32_EXTI_NUM_LINES 49
#define STM32_EXTI_IMR1_MASK 0x7FC00000U #define STM32_EXTI_IMR1_MASK 0x7FC00000U
#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U #define STM32_EXTI_IMR2_MASK 0xFFFFFCFDU
/* Flash attributes.*/ /* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 1 #define STM32_FLASH_NUMBER_OF_BANKS 1
@ -118,22 +118,26 @@
#define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOB TRUE
#define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOC TRUE
#define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOD TRUE
#define STM32_HAS_GPIOE FALSE #define STM32_HAS_GPIOE TRUE
#define STM32_HAS_GPIOF FALSE #define STM32_HAS_GPIOF FALSE
#define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOG FALSE
#define STM32_HAS_GPIOH FALSE #define STM32_HAS_GPIOH TRUE
#define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOI FALSE
#define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOJ FALSE
#define STM32_HAS_GPIOK FALSE #define STM32_HAS_GPIOK FALSE
#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ #define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
RCC_AHB2ENR_GPIOBEN | \ RCC_AHB2ENR_GPIOBEN | \
RCC_AHB2ENR_GPIOCEN | \ RCC_AHB2ENR_GPIOCEN | \
RCC_AHB2ENR_GPIODEN) RCC_AHB2ENR_GPIODEN | \
RCC_AHB2ENR_GPIOEEN | \
RCC_AHB2ENR_GPIOHEN)
/* I2C attributes.*/ /* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C3 TRUE #define STM32_HAS_I2C3 TRUE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_HAS_I2C2 FALSE
#define STM32_HAS_I2C4 FALSE
/* QUADSPI attributes.*/ /* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 TRUE #define STM32_HAS_QUADSPI1 TRUE
@ -227,7 +231,7 @@
/* CRC attributes.*/ /* CRC attributes.*/
#define STM32_HAS_CRC TRUE #define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE TRUE #define STM32_CRC_PROGRAMMABLE TRUE
#endif /* defined(STM32WB50xx) */ #endif /* defined(STM32WB55xx) */
/*===========================================================================*/ /*===========================================================================*/
/* STM32WB50xx. */ /* STM32WB50xx. */
@ -237,6 +241,22 @@
#error "STM32WB50xx is not supported" #error "STM32WB50xx is not supported"
#endif /* defined(STM32WB50xx) */ #endif /* defined(STM32WB50xx) */
/*===========================================================================*/
/* STM32WB35xx. */
/*===========================================================================*/
#if defined(STM32WB35xx) || defined(__DOXYGEN__)
#error "STM32WB35xx is not supported"
#endif /* defined(STM32WB35xx) */
/*===========================================================================*/
/* STM32WB30xx. */
/*===========================================================================*/
#if defined(STM32WB30xx) || defined(__DOXYGEN__)
#error "STM32WB30xx is not supported"
#endif /* defined(STM32WB30xx) */
/** @} */ /** @} */
#endif /* STM32_REGISTRY_H */ #endif /* STM32_REGISTRY_H */