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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13523 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2020-04-10 13:24:24 +00:00
parent ca41e9e0a4
commit 9650f55a1a
6 changed files with 156 additions and 177 deletions
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2
demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/Makefile
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@ -5,7 +5,7 @@
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).

95
demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/cfg/mcuconf.h
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@ -23,6 +23,7 @@
*
* IRQ priorities:
* 7...0 Lowest...Highest.
* 3...0 Lowest...Highest (trusted mode).
*
* DMA priorities:
* 0...3 Lowest...Highest.
@ -126,55 +127,55 @@
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_PRIORITY 3
#define STM32_IRQ_EXTI1_PRIORITY 3
#define STM32_IRQ_EXTI2_PRIORITY 3
#define STM32_IRQ_EXTI3_PRIORITY 3
#define STM32_IRQ_EXTI4_PRIORITY 3
#define STM32_IRQ_EXTI5_PRIORITY 3
#define STM32_IRQ_EXTI6_PRIORITY 3
#define STM32_IRQ_EXTI7_PRIORITY 3
#define STM32_IRQ_EXTI8_PRIORITY 3
#define STM32_IRQ_EXTI9_PRIORITY 3
#define STM32_IRQ_EXTI10_PRIORITY 3
#define STM32_IRQ_EXTI11_PRIORITY 3
#define STM32_IRQ_EXTI12_PRIORITY 3
#define STM32_IRQ_EXTI13_PRIORITY 3
#define STM32_IRQ_EXTI14_PRIORITY 3
#define STM32_IRQ_EXTI15_PRIORITY 3
#define STM32_IRQ_EXTI1635_38_PRIORITY 3
#define STM32_IRQ_EXTI17_PRIORITY 3
#define STM32_IRQ_EXTI18_PRIORITY 3
#define STM32_IRQ_EXTI19_PRIORITY 3
#define STM32_IRQ_EXTI20_PRIORITY 3
#define STM32_IRQ_EXTI21_22_PRIORITY 3
#define STM32_IRQ_EXTI0_PRIORITY 2
#define STM32_IRQ_EXTI1_PRIORITY 2
#define STM32_IRQ_EXTI2_PRIORITY 2
#define STM32_IRQ_EXTI3_PRIORITY 2
#define STM32_IRQ_EXTI4_PRIORITY 2
#define STM32_IRQ_EXTI5_PRIORITY 2
#define STM32_IRQ_EXTI6_PRIORITY 2
#define STM32_IRQ_EXTI7_PRIORITY 2
#define STM32_IRQ_EXTI8_PRIORITY 2
#define STM32_IRQ_EXTI9_PRIORITY 2
#define STM32_IRQ_EXTI10_PRIORITY 2
#define STM32_IRQ_EXTI11_PRIORITY 2
#define STM32_IRQ_EXTI12_PRIORITY 2
#define STM32_IRQ_EXTI13_PRIORITY 2
#define STM32_IRQ_EXTI14_PRIORITY 2
#define STM32_IRQ_EXTI15_PRIORITY 2
#define STM32_IRQ_EXTI1635_38_PRIORITY 2
#define STM32_IRQ_EXTI17_PRIORITY 2
#define STM32_IRQ_EXTI18_PRIORITY 2
#define STM32_IRQ_EXTI19_PRIORITY 2
#define STM32_IRQ_EXTI20_PRIORITY 2
#define STM32_IRQ_EXTI21_22_PRIORITY 2
#define STM32_IRQ_FDCAN1_PRIORITY 5
#define STM32_IRQ_FDCAN1_PRIORITY 1
#define STM32_IRQ_TIM1_BRK_PRIORITY 4
#define STM32_IRQ_TIM1_UP_PRIORITY 4
#define STM32_IRQ_TIM1_TRGCO_PRIORITY 4
#define STM32_IRQ_TIM1_CC_PRIORITY 4
#define STM32_IRQ_TIM2_PRIORITY 4
#define STM32_IRQ_TIM3_PRIORITY 4
#define STM32_IRQ_TIM4_PRIORITY 4
#define STM32_IRQ_TIM5_PRIORITY 4
#define STM32_IRQ_TIM6_PRIORITY 4
#define STM32_IRQ_TIM7_PRIORITY 4
#define STM32_IRQ_TIM8_UP_PRIORITY 4
#define STM32_IRQ_TIM8_CC_PRIORITY 4
#define STM32_IRQ_TIM15_PRIORITY 4
#define STM32_IRQ_TIM16_PRIORITY 4
#define STM32_IRQ_TIM17_PRIORITY 4
#define STM32_IRQ_TIM20_UP_PRIORITY 4
#define STM32_IRQ_TIM20_CC_PRIORITY 4
#define STM32_IRQ_TIM1_BRK_PRIORITY 1
#define STM32_IRQ_TIM1_UP_PRIORITY 1
#define STM32_IRQ_TIM1_TRGCO_PRIORITY 1
#define STM32_IRQ_TIM1_CC_PRIORITY 1
#define STM32_IRQ_TIM2_PRIORITY 1
#define STM32_IRQ_TIM3_PRIORITY 1
#define STM32_IRQ_TIM4_PRIORITY 1
#define STM32_IRQ_TIM5_PRIORITY 1
#define STM32_IRQ_TIM6_PRIORITY 1
#define STM32_IRQ_TIM7_PRIORITY 1
#define STM32_IRQ_TIM8_UP_PRIORITY 1
#define STM32_IRQ_TIM8_CC_PRIORITY 1
#define STM32_IRQ_TIM15_PRIORITY 1
#define STM32_IRQ_TIM16_PRIORITY 1
#define STM32_IRQ_TIM17_PRIORITY 1
#define STM32_IRQ_TIM20_UP_PRIORITY 1
#define STM32_IRQ_TIM20_CC_PRIORITY 1
#define STM32_IRQ_USART1_PRIORITY 5
#define STM32_IRQ_USART2_PRIORITY 5
#define STM32_IRQ_USART3_PRIORITY 5
#define STM32_IRQ_UART4_PRIORITY 5
#define STM32_IRQ_UART5_PRIORITY 5
#define STM32_IRQ_LPUART1_PRIORITY 5
#define STM32_IRQ_USART1_PRIORITY 1
#define STM32_IRQ_USART2_PRIORITY 1
#define STM32_IRQ_USART3_PRIORITY 1
#define STM32_IRQ_UART4_PRIORITY 1
#define STM32_IRQ_UART5_PRIORITY 1
#define STM32_IRQ_LPUART1_PRIORITY 1
/*
* ADC driver system settings.
@ -276,7 +277,7 @@
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 4
#define STM32_ST_IRQ_PRIORITY 1
#define STM32_ST_USE_TIMER 2
/*

2
demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/debug/RT-STM32L552ZE-NUCLEO144-TEST (ST-Link GDB Server, Flash and Run).launch
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File diff suppressed because one or more lines are too long

11
os/common/ports/ARMv8-M-ML/chcore.c
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@ -74,6 +74,17 @@ thread_t *port_schedule_next(void) {
*/
void port_init(void) {
#if PORT_KERNEL_MODE == PORT_KERNEL_MODE_HOST
{
/* Enabling PRIS in order to have two separate priority ranges for
secure and non-secure states.*/
uint32_t aircr = SCB->AIRCR;
aircr &= ~(uint32_t)SCB_AIRCR_VECTKEY_Msk;
aircr |= (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_PRIS_Msk);
SCB->AIRCR = aircr;
}
#endif
/* Starting in a known IRQ configuration.*/
port_suspend();

172
os/common/ports/ARMv8-M-ML/chcore.h
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@ -129,6 +129,29 @@
#define PORT_KERNEL_MODE_GUEST 2U
/** @} */
/**
* @name Priority boundaries
* @{
*/
/**
* @brief Total priority levels.
*/
#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
/**
* @brief Maximum priority level.
* @details The maximum allowed priority level is always zero.
*/
#define CORTEX_MAXIMUM_PRIORITY 0
/**
* @brief Minimum priority level.
* @details This minimum priority level is calculated from the number of
* priority bits supported by the specific Cortex-Mx implementation.
*/
#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
/** @} */
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
@ -137,7 +160,7 @@
* @brief Kernel mode selection.
*/
#if !defined(PORT_KERNEL_MODE) || defined(__DOXYGEN__)
#define PORT_KERNEL_MODE PORT_KERNEL_MODE_NORMAL
#define PORT_KERNEL_MODE PORT_KERNEL_MODE_HOST
#endif
/**
@ -191,6 +214,14 @@
#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif
/**
* @brief Number of upper priority levels reserved as fast interrupts.
* @note The default reserves no priority levels for fast interrupts.
*/
#if !defined(CORTEX_FAST_PRIORITIES)
#define CORTEX_FAST_PRIORITIES 0
#endif
/**
* @brief FPU support in context switch.
* @details Activating this option activates the FPU support in the kernel.
@ -207,6 +238,7 @@
* @brief NVIC PRIGROUP initialization expression.
* @details The default assigns all available priority bits as preemption
* priority with no sub-priority.
* @note Changing this value is not recommended.
*/
#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__)
#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS)
@ -216,17 +248,71 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if (CORTEX_FAST_PRIORITIES < 0) || \
(CORTEX_FAST_PRIORITIES > (CORTEX_PRIORITY_LEVELS / 8))
#error "invalid CORTEX_FAST_PRIORITIES value specified"
#endif
/**
* @brief SVCALL handler priority.
*/
#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + \
CORTEX_FAST_PRIORITIES)
/**
* @brief Maximum usable priority for normal ISRs.
* @note Must be lower than @p CORTEX_PRIORITY_SVCALL.
*/
#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)
/**
* @brief BASEPRI level within kernel lock.
*/
#define CORTEX_BASEPRI_KERNEL CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
#if PORT_KERNEL_MODE == PORT_KERNEL_MODE_NORMAL
/**
* @brief EXC_RETURN to be used when starting a thread.
*/
#define PORT_EXC_RETURN 0xFFFFFFFD
#define PORT_STORE_BASEPRI_NS FALSE
/**
* @brief Context save area for each thread.
*/
#define PORT_CONTEXT_RESERVED_SIZE (sizeof (struct port_intctx))
/**
* @brief Port-specific information string.
*/
#define PORT_INFO "Normal mode"
/**
* @brief Disabled value for BASEPRI register.
*/
#define CORTEX_BASEPRI_DISABLED CORTEX_PRIO_MASK(0)
/**
* @brief PENDSV handler priority.
*/
#define CORTEX_PRIORITY_PENDSV (CORTEX_MINIMUM_PRIORITY)
#elif PORT_KERNEL_MODE == PORT_KERNEL_MODE_HOST
#define PORT_EXC_RETURN 0xFFFFFFFD
#define PORT_STORE_BASEPRI_NS TRUE
#if CORTEX_USE_FPU == TRUE
/* Extended secure context size with FPU.*/
#define PORT_CONTEXT_RESERVED_SIZE 0xD0
#else
/* Extended secure context size without FPU.*/
#define PORT_CONTEXT_RESERVED_SIZE 0x48
#endif
#define PORT_INFO "Secure host mode"
#define CORTEX_BASEPRI_DISABLED CORTEX_PRIO_MASK(CORTEX_MINIMUM_PRIORITY)
#define CORTEX_PRIORITY_PENDSV (CORTEX_MINIMUM_PRIORITY / 2)
#elif PORT_KERNEL_MODE == PORT_KERNEL_MODE_GUEST
#define PORT_EXC_RETURN 0xFFFFFFBC
#define PORT_STORE_BASEPRI_NS FALSE
#define PORT_CONTEXT_RESERVED_SIZE (sizeof (struct port_intctx))
#define PORT_INFO "Non-secure guest mode"
#else
#error "invalid kernel security mode"
@ -278,12 +364,6 @@
#error "unknown ARMv8-M core variant"
#endif
/**
* @brief Port-specific information string.
*/
#define PORT_INFO "In-ISR switch mode"
/** @} */
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
@ -352,9 +432,6 @@ struct port_intctx {
*/
struct port_context {
struct port_intctx *sp;
#if (PORT_STORE_BASEPRI_NS == TRUE) || defined(__DOXYGEN__)
uint32_t basepri_ns;
#endif
uint32_t basepri;
uint32_t r4;
uint32_t r5;
@ -394,67 +471,22 @@ struct port_context {
/* Module macros. */
/*===========================================================================*/
/**
* @brief Disabled value for BASEPRI register.
*/
#define CORTEX_BASEPRI_DISABLED 0U
/**
* @brief Total priority levels.
*/
#define CORTEX_PRIORITY_LEVELS (1U << CORTEX_PRIORITY_BITS)
/**
* @brief Minimum priority level.
* @details This minimum priority level is calculated from the number of
* priority bits supported by the specific Cortex-Mx implementation.
*/
#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1U)
/**
* @brief Maximum priority level.
* @details The maximum allowed priority level is always zero.
*/
#define CORTEX_MAXIMUM_PRIORITY 0U
/**
* @brief SVCALL handler priority.
* @note The default reserves priority level 0 for fast interrupts.
*/
#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1U)
/**
* @brief PENDSV handler priority.
*/
#define CORTEX_PRIORITY_PENDSV (CORTEX_MINIMUM_PRIORITY)
/**
* @brief Maximum usable priority for normal ISRs.
* @note Must be lower than @p CORTEX_PRIORITY_SVCALL.
*/
#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1U)
/**
* @brief BASEPRI level within kernel lock.
*/
#define CORTEX_BASEPRI_KERNEL CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)
/**
* @brief Priority level to priority mask conversion macro.
*/
#define CORTEX_PRIO_MASK(n) ((n) << (8U - (unsigned)CORTEX_PRIORITY_BITS))
#define CORTEX_PRIO_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
/**
* @brief Priority level verification macro.
*/
#define PORT_IRQ_IS_VALID_PRIORITY(n) \
(((n) >= 0U) && ((n) < CORTEX_PRIORITY_LEVELS))
(((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
/**
* @brief Priority level verification macro.
*/
#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) \
(((n) >= CORTEX_PRIORITY_SVCALL) && ((n) < CORTEX_PRIORITY_PENDSV))
(((n) > CORTEX_PRIORITY_SVCALL) && ((n) <= CORTEX_PRIORITY_PENDSV))
/**
* @brief Initialization of stack check part of thread context.
@ -485,20 +517,6 @@ struct port_context {
#define PORT_SETUP_CONTEXT_MPU(tp)
#endif
/**
* @brief Initialization of BASEPRI_NS part of thread context.
* @note All secure threads have BASEPRI_NS set to mask PendSV, this
* way a guest RTOS cannot reschedule while a secure thread
* is running, reschedule is delayed to when the non-secure
* thread running the guest is activated again.
*/
#if (PORT_STORE_BASEPRI_NS == TRUE) || defined(__DOXYGEN__)
#define PORT_SETUP_CONTEXT_BASEPRI_NS(tp) \
(tp)->ctx.basepri_ns = (uint32_t)CORTEX_PRIO_MASK(CORTEX_PRIORITY_PENDSV)
#else
#define PORT_SETUP_CONTEXT_BASEPRI_NS(tp)
#endif
/**
* @brief Platform dependent part of the @p chThdCreateI() API.
* @details This code usually setup the context switching frame represented
@ -507,7 +525,6 @@ struct port_context {
#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) do { \
(tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \
sizeof (struct port_intctx)); \
PORT_SETUP_CONTEXT_BASEPRI_NS(tp); \
(tp)->ctx.basepri = CORTEX_BASEPRI_KERNEL; \
(tp)->ctx.r5 = (uint32_t)(arg); \
(tp)->ctx.r4 = (uint32_t)(pf); \
@ -523,8 +540,7 @@ struct port_context {
* @brief Computes the thread working area global size.
* @note There is no need to perform alignments in this macro.
*/
#define PORT_WA_SIZE(n) (sizeof (struct port_intctx) + \
sizeof (struct port_extctx) + \
#define PORT_WA_SIZE(n) (PORT_CONTEXT_RESERVED_SIZE + \
(size_t)(n) + \
(size_t)PORT_INT_REQUIRED_STACK)

51
os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S
View File

@ -82,8 +82,6 @@
* Context switch macros depending on various options.
*--------------------------------------------------------------------------*/
#if !PORT_STORE_BASEPRI_NS
#if !CH_DBG_ENABLE_STACK_CHECK
.macro PORT_STORE_INTEGER_CONTEXT_R1
mrs r2, PSP
@ -121,53 +119,6 @@
.endm
#endif
#else /* PORT_STORE_BASEPRI_NS */
#if !CH_DBG_ENABLE_STACK_CHECK
.macro PORT_STORE_INTEGER_CONTEXT_R1
mrs r2, BASEPRI_NS
stmia r1!, {r2}
mrs r2, PSP
mrs r3, BASEPRI
stmia r1!, {r2-r11,lr}
.endm
.macro PORT_RESTORE_INTEGER_CONTEXT_R0
ldmia r0!, {r1-r11, lr}
msr BASEPRI_NS, r1
msr PSP, r2
msr BASEPRI, r3
.endm
#else /* CH_DBG_ENABLE_STACK_CHECK */
.macro PORT_STORE_INTEGER_CONTEXT_R1
mrs r2, BASEPRI_NS
stmia r1!, {r2}
mrs r2, PSP
mrs r3, BASEPRI
mrs r12, PSPLIM
stmia r1!, {r2-r12,lr}
.endm
.macro PORT_RESTORE_INTEGER_CONTEXT_R0
ldmia r0!, {r1-r12, lr}
msr BASEPRI_NS, r1
/* Note the following is not required because this sentence
in the ARMv8-M architecture manual:
Updates to the stack pointer by the MSR instruction
targeting SP_NS are subject to stack limit checking.
Updates to the stack pointer and stack pointer limit
by any other MSR instruction are not subject to
stack limit checking.*/
// movs r1, #0
// msr PSPLIM, r1 /* Temporarily disabling stack check.*/
msr PSP, r2
msr BASEPRI, r3
msr PSPLIM, r12
.endm
#endif
#endif /* PORT_STORE_BASEPRI_NS */
#if CORTEX_USE_FPU
.macro PORT_STORE_FLOAT_CONTEXT_R1
vstmia r1!, {s16-s31}
@ -259,7 +210,7 @@ __port_thread_start:
#if CH_DBG_STATISTICS
bl _stats_stop_measure_crit_thd
#endif
movs r3, #0 /* CORTEX_BASEPRI_DISABLED */
movs r3, #CORTEX_BASEPRI_DISABLED
msr BASEPRI, r3
mov r0, r5
blx r4